From: Tomasz Kulasek <tomaszx.kulasek@intel.com>
To: dev@dpdk.org
Cc: helin.zhang@intel.com, konstantin.ananyev@intel.com
Subject: [dpdk-dev] [PATCH] ixgbe: fix bad shift operation in ixgbe_set_pool_tx
Date: Fri, 15 Apr 2016 16:32:59 +0200 [thread overview]
Message-ID: <1460730779-8200-1-git-send-email-tomaszx.kulasek@intel.com> (raw)
CID 13190 (#1 of 1): Bad bit shift operation (BAD_SHIFT)
large_shift: In expression 1 << pool, left shifting by more than 31 bits
has undefined behavior. The shift amount, pool, is at least 32.
This patch limits mask shift to be in range of 32 bit PFVFTE[1] register,
for pool > 31.
Fixes: fe3a45fd4104 ("ixgbe: add VMDq support")
Signed-off-by: Tomasz Kulasek <tomaszx.kulasek@intel.com>
---
drivers/net/ixgbe/ixgbe_ethdev.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ixgbe/ixgbe_ethdev.c b/drivers/net/ixgbe/ixgbe_ethdev.c
index f676a64..6ae82e7 100644
--- a/drivers/net/ixgbe/ixgbe_ethdev.c
+++ b/drivers/net/ixgbe/ixgbe_ethdev.c
@@ -4428,7 +4428,7 @@ ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
reg = IXGBE_READ_REG(hw, addr);
- val = bit1 << pool;
+ val = bit1 << (pool & 0x01F);
if (on)
reg |= val;
--
1.7.9.5
next reply other threads:[~2016-04-15 14:33 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-04-15 14:32 Tomasz Kulasek [this message]
2016-04-18 1:58 ` Lu, Wenzhuo
2016-04-21 13:53 ` Bruce Richardson
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