From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by dpdk.org (Postfix) with ESMTP id D35822C3F for ; Sat, 11 Jun 2016 17:11:59 +0200 (CEST) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga103.jf.intel.com with ESMTP; 11 Jun 2016 08:11:59 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.26,456,1459839600"; d="scan'208";a="995663837" Received: from sie-lab-212-251.ir.intel.com (HELO silpixa00381635.ir.intel.com) ([10.237.212.251]) by orsmga002.jf.intel.com with ESMTP; 11 Jun 2016 08:11:57 -0700 From: Jasvinder Singh To: dev@dpdk.org Cc: cristian.dumitrescu@intel.com Date: Sat, 11 Jun 2016 16:19:16 +0100 Message-Id: <1465658356-59012-1-git-send-email-jasvinder.singh@intel.com> X-Mailer: git-send-email 2.5.5 Subject: [dpdk-dev] [PATCH] ip_pipeline: fix false cacheline sharing among threads X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 11 Jun 2016 15:12:00 -0000 In ip_pipeline app, the structure app_thread_data needs to be aligned to the cache line boundary as threads on different cpu cores are accessing fields of the app->thread_data and having this structure not aligned on cacheline boundary leads to false cacheline sharing. Fixes: 7f64b9c004aa ("examples/ip_pipeline: rework config file syntax") Signed-off-by: Jasvinder Singh Acked-by: Cristian Dumitrescu --- examples/ip_pipeline/app.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/examples/ip_pipeline/app.h b/examples/ip_pipeline/app.h index 848244a..c51fc7f 100644 --- a/examples/ip_pipeline/app.h +++ b/examples/ip_pipeline/app.h @@ -300,7 +300,7 @@ struct app_thread_data { uint64_t headroom_time; uint64_t headroom_cycles; double headroom_ratio; -}; +}__rte_cache_aligned; #ifndef APP_MAX_LINKS #define APP_MAX_LINKS 16 -- 2.5.5