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From: Jasvinder Singh <jasvinder.singh@intel.com>
To: dev@dpdk.org
Cc: cristian.dumitrescu@intel.com
Subject: [dpdk-dev] [PATCH v2] ip_pipeline: fix false cacheline sharing among threads
Date: Sun, 12 Jun 2016 13:42:47 +0100	[thread overview]
Message-ID: <1465735367-187704-1-git-send-email-jasvinder.singh@intel.com> (raw)
In-Reply-To: <1465658356-59012-1-git-send-email-jasvinder.singh@intel.com>

In ip_pipeline app, the structure app_thread_data needs to be aligned to
the cache line boundary as threads on different cpu cores are accessing
fields of the app->thread_data and having this structure not aligned on
cacheline boundary leads to false cacheline sharing.

Fixes: 7f64b9c004aa ("examples/ip_pipeline: rework config file syntax")

Signed-off-by: Jasvinder Singh <jasvinder.singh@intel.com>
Acked-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com>
---
v2
- fix checkpatch error

 examples/ip_pipeline/app.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/examples/ip_pipeline/app.h b/examples/ip_pipeline/app.h
index 848244a..7611341 100644
--- a/examples/ip_pipeline/app.h
+++ b/examples/ip_pipeline/app.h
@@ -300,7 +300,7 @@ struct app_thread_data {
 	uint64_t headroom_time;
 	uint64_t headroom_cycles;
 	double headroom_ratio;
-};
+} __rte_cache_aligned;
 
 #ifndef APP_MAX_LINKS
 #define APP_MAX_LINKS                            16
-- 
2.5.5

  reply	other threads:[~2016-06-12 12:35 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-06-11 15:19 [dpdk-dev] [PATCH] " Jasvinder Singh
2016-06-12 12:42 ` Jasvinder Singh [this message]
2016-06-14 19:13   ` [dpdk-dev] [PATCH v2] " Thomas Monjalon

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