From: Jerin Jacob <jerin.jacob@caviumnetworks.com>
To: <dev@dpdk.org>
Cc: <thomas.monjalon@6wind.com>, <bruce.richardson@intel.com>,
<jianbo.liu@linaro.org>, <helin.zhang@intel.com>,
<konstantin.ananyev@intel.com>,
Jerin Jacob <jerin.jacob@caviumnetworks.com>
Subject: [dpdk-dev] [PATCH] ixgbe: use rte_mbuf_prefetch_part2 for cacheline1 access
Date: Fri, 17 Jun 2016 19:36:44 +0530 [thread overview]
Message-ID: <1466172404-14120-1-git-send-email-jerin.jacob@caviumnetworks.com> (raw)
made second cache line access behavior same as IA
Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
---
drivers/net/ixgbe/ixgbe_rxtx_vec_neon.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/net/ixgbe/ixgbe_rxtx_vec_neon.c b/drivers/net/ixgbe/ixgbe_rxtx_vec_neon.c
index 9c1d124..64a329e 100644
--- a/drivers/net/ixgbe/ixgbe_rxtx_vec_neon.c
+++ b/drivers/net/ixgbe/ixgbe_rxtx_vec_neon.c
@@ -280,10 +280,10 @@ _recv_raw_pkts_vec(struct ixgbe_rx_queue *rxq, struct rte_mbuf **rx_pkts,
vst1q_u64((uint64_t *)&rx_pkts[pos + 2], mbp2);
if (split_packet) {
- rte_prefetch_non_temporal(&rx_pkts[pos]->cacheline1);
- rte_prefetch_non_temporal(&rx_pkts[pos + 1]->cacheline1);
- rte_prefetch_non_temporal(&rx_pkts[pos + 2]->cacheline1);
- rte_prefetch_non_temporal(&rx_pkts[pos + 3]->cacheline1);
+ rte_mbuf_prefetch_part2(rx_pkts[pos]);
+ rte_mbuf_prefetch_part2(rx_pkts[pos + 1]);
+ rte_mbuf_prefetch_part2(rx_pkts[pos + 2]);
+ rte_mbuf_prefetch_part2(rx_pkts[pos + 3]);
}
/* D.1 pkt 3,4 convert format from desc to pktmbuf */
--
2.5.5
next reply other threads:[~2016-06-17 14:07 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-06-17 14:06 Jerin Jacob [this message]
2016-06-20 3:19 ` Jianbo Liu
2016-06-24 11:04 ` Bruce Richardson
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