From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-lf0-f47.google.com (mail-lf0-f47.google.com [209.85.215.47]) by dpdk.org (Postfix) with ESMTP id 71663C33A for ; Wed, 22 Jun 2016 11:06:27 +0200 (CEST) Received: by mail-lf0-f47.google.com with SMTP id q132so67374353lfe.3 for ; Wed, 22 Jun 2016 02:06:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=6wind-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Uv6s2FZYnwAKmvYRNBqmNiW6YQ9XVDnLH8MUVl7Ho90=; b=SgOsNgko1mCQAshYvnKzeDOkU0MrJJlOEGr4CxJ2dnonwZqW6CAGJjtWYG2UDyDU5o C4aam2uxJis3WzyxOJEYCVRO4X6oV3J44JLYg2lTydr2kITFgBPYfOVgWvgmi3t0DvGC y5SZH3BVZY1NI1M1elHknGkxQnWblWUODg3N5ga3HuXALrdRnQNz7Z4tr2ceK43ycD09 SYYWb+F+pRsOSO9FdzKZcMYY4snlnB+v/3gW2HPY8wHqmSeTciIdPVroFwRVzjXMRFVM IDQgHnzHTvzwAHy2CeIyQbTcq5GUH1wYChSHgM4jDe4oyLaabWxGCPiDNKGxkyoaDRO1 hc/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Uv6s2FZYnwAKmvYRNBqmNiW6YQ9XVDnLH8MUVl7Ho90=; b=nObVaPwL7U3lOh0e6Zbg7/8Psosc2Ww0fTPW7a7+LoBI0X+lnTWpzCqvXAXf5Kvnbj HdllP0Ijx5YZ/KzSaOTbNtpGALHXll96qqZIKzjBxUri/2t2DbA69uWjWsl2xrTrSO4R wpVOU4AYFdLTmOIC7Il1sogtVV/lVGXN6n2SAU0MLNx3nMEOTuP1fl7sG6PKfQwxEs3Y JWhl97CcWfQBY+jwDjgDXY/wn7BguyFwWPBXbi5jZ3gI+l9LJjbOE2kp+URETqTuJXzo M0mOoMBG5ENMPZS3k2SZvkw2ukLL28vSH+6b7dLtJlcuWEfhwicGL6oh/rX+CkkHS00k HwVQ== X-Gm-Message-State: ALyK8tIOJpmMxPIntE3DuOfQIHeLvYk7DRwOsEraWN7BbGaVX2ukhJdMLjwjX9anax1BZsp3 X-Received: by 10.28.38.5 with SMTP id m5mr7239847wmm.82.1466586386960; Wed, 22 Jun 2016 02:06:26 -0700 (PDT) Received: from ping.vm.6wind.com (guy78-3-82-239-227-177.fbx.proxad.net. [82.239.227.177]) by smtp.gmail.com with ESMTPSA id z5sm7019178wme.5.2016.06.22.02.06.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 22 Jun 2016 02:06:26 -0700 (PDT) From: Nelio Laranjeiro To: dev@dpdk.org Cc: Ferruh Yigit , Adrien Mazarguil , Vasily Philipov Date: Wed, 22 Jun 2016 11:05:46 +0200 Message-Id: <1466586355-30777-17-git-send-email-nelio.laranjeiro@6wind.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1466586355-30777-1-git-send-email-nelio.laranjeiro@6wind.com> References: <1466493818-1877-1-git-send-email-nelio.laranjeiro@6wind.com> <1466586355-30777-1-git-send-email-nelio.laranjeiro@6wind.com> Subject: [dpdk-dev] [PATCH v4 16/25] mlx5: replace countdown with threshold for Tx completions X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 22 Jun 2016 09:06:27 -0000 From: Adrien Mazarguil Replacing the variable countdown (which depends on the number of descriptors) with a fixed relative threshold known at compile time improves performance by reducing the TX queue structure footprint and the amount of code to manage completions during a burst. Completions are now requested at most once per burst after threshold is reached. Signed-off-by: Adrien Mazarguil Signed-off-by: Nelio Laranjeiro Signed-off-by: Vasily Philipov --- drivers/net/mlx5/mlx5_defs.h | 7 +++++-- drivers/net/mlx5/mlx5_rxtx.c | 42 ++++++++++++++++++++++++------------------ drivers/net/mlx5/mlx5_rxtx.h | 5 ++--- drivers/net/mlx5/mlx5_txq.c | 19 ++++++++++++------- 4 files changed, 43 insertions(+), 30 deletions(-) diff --git a/drivers/net/mlx5/mlx5_defs.h b/drivers/net/mlx5/mlx5_defs.h index 8d2ec7a..cc2a6f3 100644 --- a/drivers/net/mlx5/mlx5_defs.h +++ b/drivers/net/mlx5/mlx5_defs.h @@ -48,8 +48,11 @@ /* Maximum number of special flows. */ #define MLX5_MAX_SPECIAL_FLOWS 4 -/* Request send completion once in every 64 sends, might be less. */ -#define MLX5_PMD_TX_PER_COMP_REQ 64 +/* + * Request TX completion every time descriptors reach this threshold since + * the previous request. Must be a power of two for performance reasons. + */ +#define MLX5_TX_COMP_THRESH 32 /* RSS Indirection table size. */ #define RSS_INDIRECTION_TABLE_SIZE 256 diff --git a/drivers/net/mlx5/mlx5_rxtx.c b/drivers/net/mlx5/mlx5_rxtx.c index 30d413c..d56c9e9 100644 --- a/drivers/net/mlx5/mlx5_rxtx.c +++ b/drivers/net/mlx5/mlx5_rxtx.c @@ -154,9 +154,6 @@ check_cqe64(volatile struct mlx5_cqe64 *cqe, * Manage TX completions. * * When sending a burst, mlx5_tx_burst() posts several WRs. - * To improve performance, a completion event is only required once every - * MLX5_PMD_TX_PER_COMP_REQ sends. Doing so discards completion information - * for other WRs, but this information would not be used anyway. * * @param txq * Pointer to TX queue structure. @@ -170,14 +167,16 @@ txq_complete(struct txq *txq) uint16_t elts_free = txq->elts_tail; uint16_t elts_tail; uint16_t cq_ci = txq->cq_ci; - unsigned int wqe_ci = (unsigned int)-1; + volatile struct mlx5_cqe64 *cqe = NULL; + volatile union mlx5_wqe *wqe; do { - unsigned int idx = cq_ci & cqe_cnt; - volatile struct mlx5_cqe64 *cqe = &(*txq->cqes)[idx].cqe64; + volatile struct mlx5_cqe64 *tmp; - if (check_cqe64(cqe, cqe_n, cq_ci) == 1) + tmp = &(*txq->cqes)[cq_ci & cqe_cnt].cqe64; + if (check_cqe64(tmp, cqe_n, cq_ci)) break; + cqe = tmp; #ifndef NDEBUG if (MLX5_CQE_FORMAT(cqe->op_own) == MLX5_COMPRESSED) { if (!check_cqe64_seen(cqe)) @@ -191,14 +190,15 @@ txq_complete(struct txq *txq) return; } #endif /* NDEBUG */ - wqe_ci = ntohs(cqe->wqe_counter); ++cq_ci; } while (1); - if (unlikely(wqe_ci == (unsigned int)-1)) + if (unlikely(cqe == NULL)) return; + wqe = &(*txq->wqes)[htons(cqe->wqe_counter) & (txq->wqe_n - 1)]; + elts_tail = wqe->wqe.ctrl.data[3]; + assert(elts_tail < txq->wqe_n); /* Free buffers. */ - elts_tail = (wqe_ci + 1) & (elts_n - 1); - do { + while (elts_free != elts_tail) { struct rte_mbuf *elt = (*txq->elts)[elts_free]; unsigned int elts_free_next = (elts_free + 1) & (elts_n - 1); @@ -214,7 +214,7 @@ txq_complete(struct txq *txq) /* Only one segment needs to be freed. */ rte_pktmbuf_free_seg(elt); elts_free = elts_free_next; - } while (elts_free != elts_tail); + } txq->cq_ci = cq_ci; txq->elts_tail = elts_tail; /* Update the consumer index. */ @@ -435,6 +435,7 @@ mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n) const unsigned int elts_n = txq->elts_n; unsigned int i; unsigned int max; + unsigned int comp; volatile union mlx5_wqe *wqe; struct rte_mbuf *buf; @@ -484,12 +485,7 @@ mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n) buf->vlan_tci); else mlx5_wqe_write(txq, wqe, addr, length, lkey); - /* Request completion if needed. */ - if (unlikely(--txq->elts_comp == 0)) { - wqe->wqe.ctrl.data[2] = htonl(8); - txq->elts_comp = txq->elts_comp_cd_init; - } else - wqe->wqe.ctrl.data[2] = 0; + wqe->wqe.ctrl.data[2] = 0; /* Should we enable HW CKSUM offload */ if (buf->ol_flags & (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) { @@ -508,6 +504,16 @@ mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n) /* Take a shortcut if nothing must be sent. */ if (unlikely(i == 0)) return 0; + /* Check whether completion threshold has been reached. */ + comp = txq->elts_comp + i; + if (comp >= MLX5_TX_COMP_THRESH) { + /* Request completion on last WQE. */ + wqe->wqe.ctrl.data[2] = htonl(8); + /* Save elts_head in unused "immediate" field of WQE. */ + wqe->wqe.ctrl.data[3] = elts_head; + txq->elts_comp = 0; + } else + txq->elts_comp = comp; #ifdef MLX5_PMD_SOFT_COUNTERS /* Increment sent packets counter. */ txq->stats.opackets += i; diff --git a/drivers/net/mlx5/mlx5_rxtx.h b/drivers/net/mlx5/mlx5_rxtx.h index 77b0fde..f900e65 100644 --- a/drivers/net/mlx5/mlx5_rxtx.h +++ b/drivers/net/mlx5/mlx5_rxtx.h @@ -238,8 +238,7 @@ struct hash_rxq { struct txq { uint16_t elts_head; /* Current index in (*elts)[]. */ uint16_t elts_tail; /* First element awaiting completion. */ - uint16_t elts_comp_cd_init; /* Initial value for countdown. */ - uint16_t elts_comp; /* Elements before asking a completion. */ + uint16_t elts_comp; /* Counter since last completion request. */ uint16_t elts_n; /* (*elts)[] length. */ uint16_t cq_ci; /* Consumer index for completion queue. */ uint16_t cqe_n; /* Number of CQ elements. */ @@ -247,6 +246,7 @@ struct txq { uint16_t wqe_n; /* Number of WQ elements. */ uint16_t bf_offset; /* Blueflame offset. */ uint16_t bf_buf_size; /* Blueflame size. */ + uint32_t qp_num_8s; /* QP number shifted by 8. */ volatile struct mlx5_cqe (*cqes)[]; /* Completion queue. */ volatile union mlx5_wqe (*wqes)[]; /* Work queue. */ volatile uint32_t *qp_db; /* Work queue doorbell. */ @@ -259,7 +259,6 @@ struct txq { } mp2mr[MLX5_PMD_TX_MP_CACHE]; /* MP to MR translation table. */ struct rte_mbuf *(*elts)[]; /* TX elements. */ struct mlx5_txq_stats stats; /* TX queue counters. */ - uint32_t qp_num_8s; /* QP number shifted by 8. */ } __rte_cache_aligned; /* TX queue control descriptor. */ diff --git a/drivers/net/mlx5/mlx5_txq.c b/drivers/net/mlx5/mlx5_txq.c index ddcd6b6..7b2dc7c 100644 --- a/drivers/net/mlx5/mlx5_txq.c +++ b/drivers/net/mlx5/mlx5_txq.c @@ -89,6 +89,7 @@ txq_alloc_elts(struct txq_ctrl *txq_ctrl, unsigned int elts_n) DEBUG("%p: allocated and configured %u WRs", (void *)txq_ctrl, elts_n); txq_ctrl->txq.elts_head = 0; txq_ctrl->txq.elts_tail = 0; + txq_ctrl->txq.elts_comp = 0; } /** @@ -108,6 +109,7 @@ txq_free_elts(struct txq_ctrl *txq_ctrl) DEBUG("%p: freeing WRs", (void *)txq_ctrl); txq_ctrl->txq.elts_head = 0; txq_ctrl->txq.elts_tail = 0; + txq_ctrl->txq.elts_comp = 0; while (elts_tail != elts_head) { struct rte_mbuf *elt = (*elts)[elts_tail]; @@ -274,13 +276,8 @@ txq_ctrl_setup(struct rte_eth_dev *dev, struct txq_ctrl *txq_ctrl, goto error; } (void)conf; /* Thresholds configuration (ignored). */ + assert(desc > MLX5_TX_COMP_THRESH); tmpl.txq.elts_n = desc; - /* Request send completion every MLX5_PMD_TX_PER_COMP_REQ packets or - * at least 4 times per ring. */ - tmpl.txq.elts_comp_cd_init = - ((MLX5_PMD_TX_PER_COMP_REQ < (desc / 4)) ? - MLX5_PMD_TX_PER_COMP_REQ : (desc / 4)); - tmpl.txq.elts_comp = tmpl.txq.elts_comp_cd_init; /* MRs will be registered in mp2mr[] later. */ attr.rd = (struct ibv_exp_res_domain_init_attr){ .comp_mask = (IBV_EXP_RES_DOMAIN_THREAD_MODEL | @@ -300,7 +297,8 @@ txq_ctrl_setup(struct rte_eth_dev *dev, struct txq_ctrl *txq_ctrl, .res_domain = tmpl.rd, }; tmpl.cq = ibv_exp_create_cq(priv->ctx, - (desc / tmpl.txq.elts_comp_cd_init) - 1, + (((desc / MLX5_TX_COMP_THRESH) - 1) ? + ((desc / MLX5_TX_COMP_THRESH) - 1) : 1), NULL, NULL, 0, &attr.cq); if (tmpl.cq == NULL) { ret = ENOMEM; @@ -452,6 +450,13 @@ mlx5_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, return -E_RTE_SECONDARY; priv_lock(priv); + if (desc <= MLX5_TX_COMP_THRESH) { + WARN("%p: number of descriptors requested for TX queue %u" + " must be higher than MLX5_TX_COMP_THRESH, using" + " %u instead of %u", + (void *)dev, idx, MLX5_TX_COMP_THRESH + 1, desc); + desc = MLX5_TX_COMP_THRESH + 1; + } if (!rte_is_power_of_2(desc)) { desc = 1 << log2above(desc); WARN("%p: increased number of descriptors in TX queue %u" -- 2.1.4