From: Chas Williams <3chas3@gmail.com>
To: dev@dpdk.org
Cc: harish.patil@qlogic.com, Chas Williams <3chas3@gmail.com>
Subject: [dpdk-dev] [PATCH 01/10] bnx2x: Set cache line based on build configuration
Date: Mon, 11 Jul 2016 17:11:22 -0400 [thread overview]
Message-ID: <1468271491-28510-1-git-send-email-3chas3@gmail.com> (raw)
Correctly hint the cache line size. Remove unused macros associated
with the cache line size.
Fixes: 540a211084a7 ("bnx2x: driver core")
Signed-off-by: Chas Williams <3chas3@gmail.com>
---
drivers/net/bnx2x/bnx2x.h | 5 +----
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/net/bnx2x/bnx2x.h b/drivers/net/bnx2x/bnx2x.h
index 135a6eb..852ec94 100644
--- a/drivers/net/bnx2x/bnx2x.h
+++ b/drivers/net/bnx2x/bnx2x.h
@@ -302,10 +302,7 @@ struct bnx2x_device_type {
/* TCP with Timestamp Option (32) + IPv6 (40) */
/* max supported alignment is 256 (8 shift) */
-#define BNX2X_RX_ALIGN_SHIFT 8
-/* FW uses 2 cache lines alignment for start packet and size */
-#define BNX2X_FW_RX_ALIGN_START (1 << BNX2X_RX_ALIGN_SHIFT)
-#define BNX2X_FW_RX_ALIGN_END (1 << BNX2X_RX_ALIGN_SHIFT)
+#define BNX2X_RX_ALIGN_SHIFT RTE_MAX(6, min(8, RTE_CACHE_LINE_SIZE_LOG2))
#define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5)
--
2.5.5
next reply other threads:[~2016-07-11 21:11 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-07-11 21:11 Chas Williams [this message]
2016-07-12 5:39 ` Harish Patil
2016-09-14 13:17 ` Ferruh Yigit
2016-09-30 14:36 ` Patil, Harish
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