From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by dpdk.org (Postfix) with ESMTP id BCBBF5AA3 for ; Thu, 18 Aug 2016 15:34:51 +0200 (CEST) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga102.fm.intel.com with ESMTP; 18 Aug 2016 06:34:36 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.28,539,1464678000"; d="scan'208";a="750440215" Received: from sie-lab-214-241.ir.intel.com (HELO silpixa00382162.ir.intel.com) ([10.237.214.241]) by FMSMGA003.fm.intel.com with ESMTP; 18 Aug 2016 06:34:35 -0700 From: Deepak Kumar Jain To: pablo.de.lara.guarch@intel.com, fiona.trahe@intel.com, john.griffin@intel.com Cc: dev@dpdk.org, Deepak Kumar Jain Date: Thu, 18 Aug 2016 14:34:31 +0100 Message-Id: <1471527272-81483-2-git-send-email-deepak.k.jain@intel.com> X-Mailer: git-send-email 2.5.5 In-Reply-To: <1471527272-81483-1-git-send-email-deepak.k.jain@intel.com> References: <1471527272-81483-1-git-send-email-deepak.k.jain@intel.com> Subject: [dpdk-dev] [PATCH 1/2] crypto/qat: add NULL capability to Intel QAT driver X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 18 Aug 2016 13:34:52 -0000 enabled NULL crypto for Intel(R) QuickAssist Technology Signed-off-by: Deepak Kumar Jain --- doc/guides/cryptodevs/qat.rst | 3 ++- drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 2 ++ drivers/crypto/qat/qat_crypto.c | 4 ++++ 3 files changed, 8 insertions(+), 1 deletion(-) diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst index 78a734f..bb62f22 100644 --- a/doc/guides/cryptodevs/qat.rst +++ b/doc/guides/cryptodevs/qat.rst @@ -49,6 +49,7 @@ Cipher algorithms: * ``RTE_CRYPTO_SYM_CIPHER_AES256_CTR`` * ``RTE_CRYPTO_SYM_CIPHER_SNOW3G_UEA2`` * ``RTE_CRYPTO_CIPHER_AES_GCM`` +* ``RTE_CRYPTO_CIPHER_NULL`` Hash algorithms: @@ -60,7 +61,7 @@ Hash algorithms: * ``RTE_CRYPTO_AUTH_AES_XCBC_MAC`` * ``RTE_CRYPTO_AUTH_SNOW3G_UIA2`` * ``RTE_CRYPTO_AUTH_MD5_HMAC`` - +* ``RTE_CRYPTO_AUTH_NULL`` Limitations ----------- diff --git a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c index af8c176..d9437bc 100644 --- a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c +++ b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c @@ -720,6 +720,8 @@ int qat_alg_aead_session_create_content_desc_auth(struct qat_session *cdesc, } state2_size = ICP_QAT_HW_MD5_STATE2_SZ; break; + case ICP_QAT_HW_AUTH_ALGO_NULL: + break; default: PMD_DRV_LOG(ERR, "Invalid HASH alg %u", cdesc->qat_hash_alg); return -EFAULT; diff --git a/drivers/crypto/qat/qat_crypto.c b/drivers/crypto/qat/qat_crypto.c index a474512..434ff81 100644 --- a/drivers/crypto/qat/qat_crypto.c +++ b/drivers/crypto/qat/qat_crypto.c @@ -427,6 +427,8 @@ qat_crypto_sym_configure_session_cipher(struct rte_cryptodev *dev, session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE; break; case RTE_CRYPTO_CIPHER_NULL: + session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE; + break; case RTE_CRYPTO_CIPHER_3DES_ECB: case RTE_CRYPTO_CIPHER_3DES_CBC: case RTE_CRYPTO_CIPHER_AES_ECB: @@ -558,6 +560,8 @@ qat_crypto_sym_configure_session_auth(struct rte_cryptodev *dev, session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_MD5; break; case RTE_CRYPTO_AUTH_NULL: + session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_NULL; + break; case RTE_CRYPTO_AUTH_SHA1: case RTE_CRYPTO_AUTH_SHA256: case RTE_CRYPTO_AUTH_SHA512: -- 2.5.5