From: Beilei Xing <beilei.xing@intel.com>
To: jingjing.wu@intel.com
Cc: dev@dpdk.org, Beilei Xing <beilei.xing@intel.com>
Subject: [dpdk-dev] [PATCH] net/i40e: fix parsing QinQ packets type issue
Date: Fri, 19 Aug 2016 11:20:05 +0800 [thread overview]
Message-ID: <1471576805-16857-1-git-send-email-beilei.xing@intel.com> (raw)
Previously, PTYPE filed in the RX descriptors is not set properly
for QinQ packets, wrong PTYPE is generated because outer Tag did
not have ORT/PIT configured.
Fix this issue by configuring ORT/PIT.
Fixes: 4861cde46116 ("i40e: new poll mode driver")
Signed-off-by: Beilei Xing <beilei.xing@intel.com>
---
drivers/net/i40e/i40e_ethdev.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c
index 55c4887..ba0eca0 100644
--- a/drivers/net/i40e/i40e_ethdev.c
+++ b/drivers/net/i40e/i40e_ethdev.c
@@ -747,8 +747,10 @@ static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
+ I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
/* GLQF_PIT Registers */
+ I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
}
--
2.5.0
next reply other threads:[~2016-08-19 3:20 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-08-19 3:20 Beilei Xing [this message]
2016-08-21 1:21 ` Wu, Jingjing
2016-08-23 9:44 ` [dpdk-dev] [PATCH v2] " Beilei Xing
2016-09-05 5:36 ` Wu, Jingjing
2016-09-12 9:41 ` [dpdk-dev] [PATCH v3] " Beilei Xing
2016-09-22 7:40 ` Wu, Jingjing
2016-09-23 11:00 ` Bruce Richardson
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