From: Beilei Xing <beilei.xing@intel.com>
To: jingjing.wu@intel.com
Cc: dev@dpdk.org, Beilei Xing <beilei.xing@intel.com>
Subject: [dpdk-dev] [PATCH v2] net/i40e: fix parsing QinQ packets type issue
Date: Tue, 23 Aug 2016 17:44:47 +0800 [thread overview]
Message-ID: <1471945487-15877-1-git-send-email-beilei.xing@intel.com> (raw)
In-Reply-To: <1471576805-16857-1-git-send-email-beilei.xing@intel.com>
Previously, PTYPE filed in the RX descriptors is not set properly
for QinQ packets, wrong PTYPE is generated because outer Tag did
not have ORT/PIT configured.
Fix this issue by configuring ORT/PIT.
Fixes: 4861cde46116 ("i40e: new poll mode driver")
Signed-off-by: Beilei Xing <beilei.xing@intel.com>
---
v2 changes:
Modify function name and add comments.
drivers/net/i40e/i40e_ethdev.c | 25 ++++++++++++++-----------
1 file changed, 14 insertions(+), 11 deletions(-)
diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c
index 55c4887..59ff6dc 100644
--- a/drivers/net/i40e/i40e_ethdev.c
+++ b/drivers/net/i40e/i40e_ethdev.c
@@ -724,10 +724,6 @@ static struct rte_driver rte_i40e_driver = {
PMD_REGISTER_DRIVER(rte_i40e_driver, i40e);
DRIVER_REGISTER_PCI_TABLE(i40e, pci_id_i40e_map);
-/*
- * Initialize registers for flexible payload, which should be set by NVM.
- * This should be removed from code once it is fixed in NVM.
- */
#ifndef I40E_GLQF_ORT
#define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
#endif
@@ -735,8 +731,12 @@ DRIVER_REGISTER_PCI_TABLE(i40e, pci_id_i40e_map);
#define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
#endif
-static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
+static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
{
+ /*
+ * Initialize registers for flexible payload, which should be set by NVM.
+ * This should be removed from code once it is fixed in NVM.
+ */
I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
@@ -747,10 +747,12 @@ static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
-
- /* GLQF_PIT Registers */
I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
+
+ /* Initialize registers for parsing packet type of QinQ */
+ I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
+ I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
}
#define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
@@ -1005,11 +1007,12 @@ eth_i40e_dev_init(struct rte_eth_dev *dev)
}
/*
- * To work around the NVM issue,initialize registers
- * for flexible payload by software.
- * It should be removed once issues are fixed in NVM.
+ * To work around the NVM issue, initialize registers
+ * for flexible payload and packet type of QinQ by
+ * software. It should be removed once issues are fixed
+ * in NVM.
*/
- i40e_flex_payload_reg_init(hw);
+ i40e_GLQF_reg_init(hw);
/* Initialize the input set for filters (hash and fd) to default value */
i40e_filter_input_set_init(pf);
--
2.5.0
next prev parent reply other threads:[~2016-08-23 9:44 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-08-19 3:20 [dpdk-dev] [PATCH] " Beilei Xing
2016-08-21 1:21 ` Wu, Jingjing
2016-08-23 9:44 ` Beilei Xing [this message]
2016-09-05 5:36 ` [dpdk-dev] [PATCH v2] " Wu, Jingjing
2016-09-12 9:41 ` [dpdk-dev] [PATCH v3] " Beilei Xing
2016-09-22 7:40 ` Wu, Jingjing
2016-09-23 11:00 ` Bruce Richardson
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