From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id 8E4F85681 for ; Thu, 25 Aug 2016 10:06:08 +0200 (CEST) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga101.fm.intel.com with ESMTP; 25 Aug 2016 01:06:09 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.28,574,1464678000"; d="scan'208";a="753271296" Received: from unknown (HELO localhost.localdomain.sh.intel.com) ([10.239.129.103]) by FMSMGA003.fm.intel.com with ESMTP; 25 Aug 2016 01:06:07 -0700 From: Zhang Qi To: jingjing.wu@intel.com, helin.zhang@intel.com Cc: dev@dpdk.org, Zhang Qi Date: Thu, 25 Aug 2016 16:05:11 -0400 Message-Id: <1472155518-853-6-git-send-email-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1472155518-853-1-git-send-email-qi.z.zhang@intel.com> References: <1472155518-853-1-git-send-email-qi.z.zhang@intel.com> Subject: [dpdk-dev] [PATCH 05/12] net/i40e/base: enable 25G get PHY abilities X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 25 Aug 2016 08:06:09 -0000 Add extended PHY types to get PHY abilities command response struct for 25G, then put PHY types for 25g into the proper PHY_Type_Ext field. Signed-off-by: Zhang Qi --- drivers/net/i40e/base/i40e_adminq_cmd.h | 15 +++++++++++++-- drivers/net/i40e/base/i40e_common.c | 4 +++- 2 files changed, 16 insertions(+), 3 deletions(-) diff --git a/drivers/net/i40e/base/i40e_adminq_cmd.h b/drivers/net/i40e/base/i40e_adminq_cmd.h index 2831593..4ae4315 100644 --- a/drivers/net/i40e/base/i40e_adminq_cmd.h +++ b/drivers/net/i40e/base/i40e_adminq_cmd.h @@ -1733,7 +1733,13 @@ struct i40e_aq_get_phy_abilities_resp { __le32 eeer_val; u8 d3_lpan; #define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01 - u8 reserved[3]; + u8 phy_type_ext; +#define I40E_AQ_PHY_TYPE_EXT_25G_KR 0X01 +#define I40E_AQ_PHY_TYPE_EXT_25G_CR 0X02 +#define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04 +#define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08 + u8 mod_type_ext; + u8 ext_comp_code; u8 phy_id[4]; u8 module_type[3]; u8 qualified_module_count; @@ -1755,7 +1761,12 @@ struct i40e_aq_set_phy_config { /* same bits as above in all */ __le16 eee_capability; __le32 eeer; u8 low_power_ctrl; - u8 reserved[3]; + u8 phy_type_ext; +#define I40E_AQ_PHY_TYPE_EXT_25G_KR 0X01 +#define I40E_AQ_PHY_TYPE_EXT_25G_CR 0X02 +#define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04 +#define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08 + u8 reserved[2]; }; I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config); diff --git a/drivers/net/i40e/base/i40e_common.c b/drivers/net/i40e/base/i40e_common.c index 1de0e39..ff64dca 100644 --- a/drivers/net/i40e/base/i40e_common.c +++ b/drivers/net/i40e/base/i40e_common.c @@ -1670,8 +1670,10 @@ enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw, if (hw->aq.asq_last_status == I40E_AQ_RC_EIO) status = I40E_ERR_UNKNOWN_PHY; - if (report_init) + if (report_init) { hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type); + hw->phy.phy_types |= ((u64)abilities->phy_type_ext << 32); + } return status; } -- 2.7.4