[dpdk-dev] [PATCH v4 0/2] net/i40e: enable 25G device

[dpdk-dev] [PATCH v4 0/2] net/i40e: enable 25G device

[Zhang Qi]

The patch enable devices that support 25G link speed.
It is based on previous 25G base driver update:
http://dpdk.org/ml/archives/dev/2016-August/045569.html

Zhang Qi (2):
  net/i40e: use PHY type to check PHY capability
  net/i40e: enable 25G device

 drivers/net/i40e/i40e_ethdev.c | 54 +++++++++++++++++++++++++++++++++++-------
 drivers/net/i40e/i40e_ethdev.h | 14 +++++++++++
 2 files changed, 59 insertions(+), 9 deletions(-)

-- 
2.7.4

[dpdk-dev] [PATCH v4 1/2] net/i40e: use PHY type to check PHY capability

[Zhang Qi]

In previous code, we use device ID to check PHY
capability which is not extensible since there is
always new device be added.
Now we use PHY type to detect PHY capability.
PHY type encoded all link speed the device support,
it is read out through aq command "get_phy_capability"
at init stage.

Signed-off-by: Zhang Qi <qi.z.zhang@intel.com>
---
 drivers/net/i40e/i40e_ethdev.c | 33 ++++++++++++++++++++++++++++-----
 drivers/net/i40e/i40e_ethdev.h |  8 ++++++++
 2 files changed, 36 insertions(+), 5 deletions(-)

diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c
index acc25a2..cbf98d9 100644
--- a/drivers/net/i40e/i40e_ethdev.c
+++ b/drivers/net/i40e/i40e_ethdev.c
@@ -411,6 +411,7 @@ static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 				void *arg);
 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 				  struct rte_eth_dcb_info *dcb_info);
+static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 static void i40e_configure_registers(struct i40e_hw *hw);
 static void i40e_hw_init(struct rte_eth_dev *dev);
 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
@@ -1028,7 +1029,11 @@ eth_i40e_dev_init(struct rte_eth_dev *dev)
 	config_floating_veb(dev);
 	/* Clear PXE mode */
 	i40e_clear_pxe_mode(hw);
-
+	ret = i40e_dev_sync_phy_type(hw);
+	if (ret) {
+		PMD_INIT_LOG(ERR, "Failed to sync phy type: %d", ret);
+		goto err_sync_phy_type;
+	}
 	/*
 	 * On X710, performance number is far from the expectation on recent
 	 * firmware versions. The fix for this issue may not be integrated in
@@ -1184,6 +1189,7 @@ err_msix_pool_init:
 err_qp_pool_init:
 err_parameter_init:
 err_get_capabilities:
+err_sync_phy_type:
 	(void)i40e_shutdown_adminq(hw);
 
 	return ret;
@@ -1650,7 +1656,7 @@ i40e_apply_link_speed(struct rte_eth_dev *dev)
 	abilities |= I40E_AQ_PHY_LINK_ENABLED;
 
 	/* Skip changing speed on 40G interfaces, FW does not support */
-	if (i40e_is_40G_device(hw->device_id)) {
+	if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
 		speed =  I40E_LINK_SPEED_UNKNOWN;
 		abilities |= I40E_AQ_PHY_AN_ENABLED;
 	}
@@ -2625,7 +2631,7 @@ i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
 		dev_info->max_tx_queues += dev_info->vmdq_queue_num;
 	}
 
-	if (i40e_is_40G_device(hw->device_id))
+	if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
 		/* For XL710 */
 		dev_info->speed_capa = ETH_LINK_SPEED_40G;
 	else
@@ -2873,7 +2879,7 @@ i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
 	if (err < 0)
 		return -ENOSYS;
 
-	if (i40e_is_40G_device(hw->device_id)) {
+	if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
 		/* Configure flow control refresh threshold,
 		 * the value for stat_tx_pause_refresh_timer[8]
 		 * is used for global pause operation.
@@ -8055,6 +8061,23 @@ i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
 
+static int
+i40e_dev_sync_phy_type(struct i40e_hw *hw)
+{
+	enum i40e_status_code status;
+	struct i40e_aq_get_phy_abilities_resp phy_ab;
+	int ret = -ENOTSUP;
+
+	status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
+					      NULL);
+
+	if (status)
+		return ret;
+
+	return 0;
+}
+
+
 static void
 i40e_configure_registers(struct i40e_hw *hw)
 {
@@ -8072,7 +8095,7 @@ i40e_configure_registers(struct i40e_hw *hw)
 
 	for (i = 0; i < RTE_DIM(reg_table); i++) {
 		if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
-			if (i40e_is_40G_device(hw->device_id)) /* For XL710 */
+			if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) /* For XL710 */
 				reg_table[i].val =
 					I40E_GL_SWR_PM_UP_THR_SF_VALUE;
 			else /* For X710 */
diff --git a/drivers/net/i40e/i40e_ethdev.h b/drivers/net/i40e/i40e_ethdev.h
index 92c8fad..9b6b03c 100644
--- a/drivers/net/i40e/i40e_ethdev.h
+++ b/drivers/net/i40e/i40e_ethdev.h
@@ -712,4 +712,12 @@ i40e_calc_itr_interval(int16_t interval)
 	(pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \
 	(pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD)
 
+#define I40E_PHY_TYPE_SUPPORT_40G(phy_type) \
+	(((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_KR4) || \
+	((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_CR4_CU) || \
+	((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_AOC) || \
+	((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_CR4) || \
+	((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_SR4) || \
+	((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_LR4))
+
 #endif /* _I40E_ETHDEV_H_ */
-- 
2.7.4

[dpdk-dev] [PATCH v4 2/2] net/i40e: enable 25G device

[Zhang Qi]

Add code branch for 25G link speed,
so 25G device will be functional.

Signed-off-by: Zhang Qi <qi.z.zhang@intel.com>
---
 drivers/net/i40e/i40e_ethdev.c | 23 ++++++++++++++++++-----
 drivers/net/i40e/i40e_ethdev.h |  6 ++++++
 2 files changed, 24 insertions(+), 5 deletions(-)

diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c
index cbf98d9..713c0c9 100644
--- a/drivers/net/i40e/i40e_ethdev.c
+++ b/drivers/net/i40e/i40e_ethdev.c
@@ -1573,6 +1573,8 @@ i40e_parse_link_speeds(uint16_t link_speeds)
 
 	if (link_speeds & ETH_LINK_SPEED_40G)
 		link_speed |= I40E_LINK_SPEED_40GB;
+	if (link_speeds & ETH_LINK_SPEED_25G)
+		link_speed |= I40E_LINK_SPEED_25GB;
 	if (link_speeds & ETH_LINK_SPEED_20G)
 		link_speed |= I40E_LINK_SPEED_20GB;
 	if (link_speeds & ETH_LINK_SPEED_10G)
@@ -1598,12 +1600,12 @@ i40e_phy_conf_link(struct i40e_hw *hw,
 			I40E_AQ_PHY_FLAG_PAUSE_RX |
 			I40E_AQ_PHY_FLAG_LOW_POWER;
 	const uint8_t advt = I40E_LINK_SPEED_40GB |
+			I40E_LINK_SPEED_25GB |
 			I40E_LINK_SPEED_10GB |
 			I40E_LINK_SPEED_1GB |
 			I40E_LINK_SPEED_100MB;
 	int ret = -ENOTSUP;
 
-
 	status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
 					      NULL);
 	if (status)
@@ -1650,7 +1652,8 @@ i40e_apply_link_speed(struct rte_eth_dev *dev)
 	struct rte_eth_conf *conf = &dev->data->dev_conf;
 
 	speed = i40e_parse_link_speeds(conf->link_speeds);
-	abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
+	if (!I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
+		abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
 	if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
 		abilities |= I40E_AQ_PHY_AN_ENABLED;
 	abilities |= I40E_AQ_PHY_LINK_ENABLED;
@@ -1752,7 +1755,8 @@ i40e_dev_start(struct rte_eth_dev *dev)
 	/* Apply link configure */
 	if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
 				ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
-				ETH_LINK_SPEED_20G | ETH_LINK_SPEED_40G)) {
+				ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
+				ETH_LINK_SPEED_40G)) {
 		PMD_DRV_LOG(ERR, "Invalid link setting");
 		goto err_up;
 	}
@@ -1972,9 +1976,11 @@ static int
 i40e_dev_set_link_down(struct rte_eth_dev *dev)
 {
 	uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
-	uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
+	uint8_t abilities = 0;
 	struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 
+	if (!I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
+		abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
 	return i40e_phy_conf_link(hw, abilities, speed);
 }
 
@@ -2032,6 +2038,9 @@ i40e_dev_link_update(struct rte_eth_dev *dev,
 	case I40E_LINK_SPEED_20GB:
 		link.link_speed = ETH_SPEED_NUM_20G;
 		break;
+	case I40E_LINK_SPEED_25GB:
+		link.link_speed = ETH_SPEED_NUM_25G;
+		break;
 	case I40E_LINK_SPEED_40GB:
 		link.link_speed = ETH_SPEED_NUM_40G;
 		break;
@@ -2634,6 +2643,9 @@ i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
 	if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
 		/* For XL710 */
 		dev_info->speed_capa = ETH_LINK_SPEED_40G;
+	if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
+		/* For XXL710 */
+		dev_info->speed_capa = ETH_LINK_SPEED_25G;
 	else
 		/* For X710 */
 		dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
@@ -8095,7 +8107,8 @@ i40e_configure_registers(struct i40e_hw *hw)
 
 	for (i = 0; i < RTE_DIM(reg_table); i++) {
 		if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
-			if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) /* For XL710 */
+			if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
+			    I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXL710 */
 				reg_table[i].val =
 					I40E_GL_SWR_PM_UP_THR_SF_VALUE;
 			else /* For X710 */
diff --git a/drivers/net/i40e/i40e_ethdev.h b/drivers/net/i40e/i40e_ethdev.h
index 9b6b03c..8d31fa3 100644
--- a/drivers/net/i40e/i40e_ethdev.h
+++ b/drivers/net/i40e/i40e_ethdev.h
@@ -720,4 +720,10 @@ i40e_calc_itr_interval(int16_t interval)
 	((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_SR4) || \
 	((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_LR4))
 
+#define I40E_PHY_TYPE_SUPPORT_25G(phy_type) \
+	(((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_KR) || \
+	((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_CR) || \
+	((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_SR) || \
+	((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_LR))
+
 #endif /* _I40E_ETHDEV_H_ */
-- 
2.7.4