[dpdk-dev] [PATCH 1/2] net/thunderx: disable l3 alignment pad feature

[Jerin Jacob <jerin.jacob@caviumnetworks.com>]

Based on the packet type(IPv4 or IPv6), the nicvf HW aligns
L3 data to the 64bit memory address.
The alignment creates a hole in mbuf(between the
end of headroom and packet data start).
The new revision of the HW provides an option to disable
the L3 alignment feature and make mbuf layout looks
more like other NICs. For better application compatibility,
disabling l3 alignment feature on the hardware revisions it supports.

Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
---
 drivers/net/thunderx/base/nicvf_hw.c      | 18 ++++++++++++++++++
 drivers/net/thunderx/base/nicvf_hw.h      |  4 ++++
 drivers/net/thunderx/base/nicvf_hw_defs.h |  2 ++
 drivers/net/thunderx/nicvf_ethdev.c       | 10 ++++++++++
 4 files changed, 34 insertions(+)

diff --git a/drivers/net/thunderx/base/nicvf_hw.c b/drivers/net/thunderx/base/nicvf_hw.c
index 1f08ef2..a69cd02 100644
--- a/drivers/net/thunderx/base/nicvf_hw.c
+++ b/drivers/net/thunderx/base/nicvf_hw.c
@@ -725,6 +725,24 @@ nicvf_vlan_hw_strip(struct nicvf *nic, bool enable)
 }
 
 void
+nicvf_apad_config(struct nicvf *nic, bool enable)
+{
+	uint64_t val;
+
+	/* APAD always enabled in this device */
+	if (!(nic->hwcap & NICVF_CAP_DISABLE_APAD))
+		return;
+
+	val = nicvf_reg_read(nic, NIC_VNIC_RQ_GEN_CFG);
+	if (enable)
+		val &= ~(1ULL << NICVF_QS_RQ_DIS_APAD_SHIFT);
+	else
+		val |= (1ULL << NICVF_QS_RQ_DIS_APAD_SHIFT);
+
+	nicvf_reg_write(nic, NIC_VNIC_RQ_GEN_CFG, val);
+}
+
+void
 nicvf_rss_set_key(struct nicvf *nic, uint8_t *key)
 {
 	int idx;
diff --git a/drivers/net/thunderx/base/nicvf_hw.h b/drivers/net/thunderx/base/nicvf_hw.h
index 2b8738b..cf68be9 100644
--- a/drivers/net/thunderx/base/nicvf_hw.h
+++ b/drivers/net/thunderx/base/nicvf_hw.h
@@ -54,6 +54,8 @@
 #define NICVF_CAP_TUNNEL_PARSING	(1ULL << 0)
 /* Additional word in Rx descriptor to hold optional tunneling extension info */
 #define NICVF_CAP_CQE_RX2		(1ULL << 1)
+/* The device capable of setting NIC_CQE_RX_S[APAD] == 0 */
+#define NICVF_CAP_DISABLE_APAD		(1ULL << 2)
 
 enum nicvf_tns_mode {
 	NIC_TNS_BYPASS_MODE,
@@ -217,6 +219,8 @@ uint32_t nicvf_qsize_sq_roundup(uint32_t val);
 
 void nicvf_vlan_hw_strip(struct nicvf *nic, bool enable);
 
+void nicvf_apad_config(struct nicvf *nic, bool enable);
+
 int nicvf_rss_config(struct nicvf *nic, uint32_t  qcnt, uint64_t cfg);
 int nicvf_rss_term(struct nicvf *nic);
 
diff --git a/drivers/net/thunderx/base/nicvf_hw_defs.h b/drivers/net/thunderx/base/nicvf_hw_defs.h
index e144d44..00dd2fe 100644
--- a/drivers/net/thunderx/base/nicvf_hw_defs.h
+++ b/drivers/net/thunderx/base/nicvf_hw_defs.h
@@ -105,6 +105,8 @@
 #define NICVF_INTR_MBOX_SHIFT           22
 #define NICVF_INTR_QS_ERR_SHIFT         23
 
+#define NICVF_QS_RQ_DIS_APAD_SHIFT      22
+
 #define NICVF_INTR_CQ_MASK              (0xFF << NICVF_INTR_CQ_SHIFT)
 #define NICVF_INTR_SQ_MASK              (0xFF << NICVF_INTR_SQ_SHIFT)
 #define NICVF_INTR_RBDR_MASK            (0x03 << NICVF_INTR_RBDR_SHIFT)
diff --git a/drivers/net/thunderx/nicvf_ethdev.c b/drivers/net/thunderx/nicvf_ethdev.c
index 094c5d5..501c8c2 100644
--- a/drivers/net/thunderx/nicvf_ethdev.c
+++ b/drivers/net/thunderx/nicvf_ethdev.c
@@ -1527,6 +1527,16 @@ nicvf_vf_start(struct rte_eth_dev *dev, struct nicvf *nic, uint32_t rbdrsz)
 	/* Configure VLAN Strip */
 	nicvf_vlan_hw_strip(nic, dev->data->dev_conf.rxmode.hw_vlan_strip);
 
+	/* Based on the packet type(IPv4 or IPv6), the nicvf HW aligns L3 data
+	 * to the 64bit memory address.
+	 * The alignment creates a hole in mbuf(between the end of headroom and
+	 * packet data start). The new revision of the HW provides an option to
+	 * disable the L3 alignment feature and make mbuf layout looks
+	 * more like other NICs. For better application compatibility, disabling
+	 * l3 alignment feature on the hardware revisions it supports
+	 */
+	nicvf_apad_config(nic, false);
+
 	/* Get queue ranges for this VF */
 	nicvf_tx_range(dev, nic, &tx_start, &tx_end);
 
-- 
2.5.5