From: Jingjing Wu <jingjing.wu@intel.com>
To: dev@dpdk.org
Cc: jingjing.wu@intel.com, helin.zhang@intel.com
Subject: [dpdk-dev] [PATCH v3 08/31] net/i40e/base: add clause22 and clause45 implementation
Date: Sat, 10 Dec 2016 19:24:30 +0800 [thread overview]
Message-ID: <1481369093-102492-9-git-send-email-jingjing.wu@intel.com> (raw)
In-Reply-To: <1481369093-102492-1-git-send-email-jingjing.wu@intel.com>
Some external PHYs require Clause22 and Clause45 method for
accessing registers. Mostly used for X722 support.
Signed-off-by: Jingjing Wu <jingjing.wu@intel.com>
---
drivers/net/i40e/base/i40e_common.c | 245 +++++++++++++++++++++++++++------
drivers/net/i40e/base/i40e_prototype.h | 16 ++-
drivers/net/i40e/base/i40e_type.h | 17 ++-
3 files changed, 226 insertions(+), 52 deletions(-)
diff --git a/drivers/net/i40e/base/i40e_common.c b/drivers/net/i40e/base/i40e_common.c
index 7eea189..85c1c11 100644
--- a/drivers/net/i40e/base/i40e_common.c
+++ b/drivers/net/i40e/base/i40e_common.c
@@ -6022,7 +6022,92 @@ enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
}
/**
- * i40e_read_phy_register
+ * i40e_read_phy_register_clause22
+ * @hw: pointer to the HW structure
+ * @reg: register address in the page
+ * @phy_adr: PHY address on MDIO interface
+ * @value: PHY register value
+ *
+ * Reads specified PHY register value
+ **/
+enum i40e_status_code i40e_read_phy_register_clause22(struct i40e_hw *hw,
+ u16 reg, u8 phy_addr, u16 *value)
+{
+ enum i40e_status_code status = I40E_ERR_TIMEOUT;
+ u8 port_num = (u8)hw->func_caps.mdio_port_num;
+ u32 command = 0;
+ u16 retry = 1000;
+
+ command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
+ (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
+ (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) |
+ (I40E_MDIO_CLAUSE22_STCODE_MASK) |
+ (I40E_GLGEN_MSCA_MDICMD_MASK);
+ wr32(hw, I40E_GLGEN_MSCA(port_num), command);
+ do {
+ command = rd32(hw, I40E_GLGEN_MSCA(port_num));
+ if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
+ status = I40E_SUCCESS;
+ break;
+ }
+ i40e_usec_delay(10);
+ retry--;
+ } while (retry);
+
+ if (status) {
+ i40e_debug(hw, I40E_DEBUG_PHY,
+ "PHY: Can't write command to external PHY.\n");
+ } else {
+ command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
+ *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
+ I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
+ }
+
+ return status;
+}
+
+/**
+ * i40e_write_phy_register_clause22
+ * @hw: pointer to the HW structure
+ * @reg: register address in the page
+ * @phy_adr: PHY address on MDIO interface
+ * @value: PHY register value
+ *
+ * Writes specified PHY register value
+ **/
+enum i40e_status_code i40e_write_phy_register_clause22(struct i40e_hw *hw,
+ u16 reg, u8 phy_addr, u16 value)
+{
+ enum i40e_status_code status = I40E_ERR_TIMEOUT;
+ u8 port_num = (u8)hw->func_caps.mdio_port_num;
+ u32 command = 0;
+ u16 retry = 1000;
+
+ command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
+ wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
+
+ command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
+ (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
+ (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) |
+ (I40E_MDIO_CLAUSE22_STCODE_MASK) |
+ (I40E_GLGEN_MSCA_MDICMD_MASK);
+
+ wr32(hw, I40E_GLGEN_MSCA(port_num), command);
+ do {
+ command = rd32(hw, I40E_GLGEN_MSCA(port_num));
+ if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
+ status = I40E_SUCCESS;
+ break;
+ }
+ i40e_usec_delay(10);
+ retry--;
+ } while (retry);
+
+ return status;
+}
+
+/**
+ * i40e_read_phy_register_clause45
* @hw: pointer to the HW structure
* @page: registers page number
* @reg: register address in the page
@@ -6031,9 +6116,8 @@ enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
*
* Reads specified PHY register value
**/
-enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw,
- u8 page, u16 reg, u8 phy_addr,
- u16 *value)
+enum i40e_status_code i40e_read_phy_register_clause45(struct i40e_hw *hw,
+ u8 page, u16 reg, u8 phy_addr, u16 *value)
{
enum i40e_status_code status = I40E_ERR_TIMEOUT;
u32 command = 0;
@@ -6043,8 +6127,8 @@ enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw,
command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
(page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
(phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
- (I40E_MDIO_OPCODE_ADDRESS) |
- (I40E_MDIO_STCODE) |
+ (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
+ (I40E_MDIO_CLAUSE45_STCODE_MASK) |
(I40E_GLGEN_MSCA_MDICMD_MASK) |
(I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
wr32(hw, I40E_GLGEN_MSCA(port_num), command);
@@ -6066,8 +6150,8 @@ enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw,
command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
(phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
- (I40E_MDIO_OPCODE_READ) |
- (I40E_MDIO_STCODE) |
+ (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) |
+ (I40E_MDIO_CLAUSE45_STCODE_MASK) |
(I40E_GLGEN_MSCA_MDICMD_MASK) |
(I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
status = I40E_ERR_TIMEOUT;
@@ -6097,7 +6181,7 @@ enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw,
}
/**
- * i40e_write_phy_register
+ * i40e_write_phy_register_clause45
* @hw: pointer to the HW structure
* @page: registers page number
* @reg: register address in the page
@@ -6106,9 +6190,8 @@ enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw,
*
* Writes value to specified PHY register
**/
-enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw,
- u8 page, u16 reg, u8 phy_addr,
- u16 value)
+enum i40e_status_code i40e_write_phy_register_clause45(struct i40e_hw *hw,
+ u8 page, u16 reg, u8 phy_addr, u16 value)
{
enum i40e_status_code status = I40E_ERR_TIMEOUT;
u32 command = 0;
@@ -6118,8 +6201,8 @@ enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw,
command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
(page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
(phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
- (I40E_MDIO_OPCODE_ADDRESS) |
- (I40E_MDIO_STCODE) |
+ (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
+ (I40E_MDIO_CLAUSE45_STCODE_MASK) |
(I40E_GLGEN_MSCA_MDICMD_MASK) |
(I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
wr32(hw, I40E_GLGEN_MSCA(port_num), command);
@@ -6143,8 +6226,8 @@ enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw,
command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
(phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
- (I40E_MDIO_OPCODE_WRITE) |
- (I40E_MDIO_STCODE) |
+ (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) |
+ (I40E_MDIO_CLAUSE45_STCODE_MASK) |
(I40E_GLGEN_MSCA_MDICMD_MASK) |
(I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
status = I40E_ERR_TIMEOUT;
@@ -6165,6 +6248,78 @@ enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw,
}
/**
+ * i40e_write_phy_register
+ * @hw: pointer to the HW structure
+ * @page: registers page number
+ * @reg: register address in the page
+ * @phy_adr: PHY address on MDIO interface
+ * @value: PHY register value
+ *
+ * Writes value to specified PHY register
+ **/
+enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw,
+ u8 page, u16 reg, u8 phy_addr, u16 value)
+{
+ enum i40e_status_code status;
+
+ switch (hw->device_id) {
+ case I40E_DEV_ID_1G_BASE_T_X722:
+ status = i40e_write_phy_register_clause22(hw,
+ reg, phy_addr, value);
+ break;
+ case I40E_DEV_ID_10G_BASE_T:
+ case I40E_DEV_ID_10G_BASE_T4:
+ case I40E_DEV_ID_10G_BASE_T_X722:
+ case I40E_DEV_ID_25G_B:
+ case I40E_DEV_ID_25G_SFP28:
+ status = i40e_write_phy_register_clause45(hw,
+ page, reg, phy_addr, value);
+ break;
+ default:
+ status = I40E_ERR_UNKNOWN_PHY;
+ break;
+ }
+
+ return status;
+}
+
+/**
+ * i40e_read_phy_register
+ * @hw: pointer to the HW structure
+ * @page: registers page number
+ * @reg: register address in the page
+ * @phy_adr: PHY address on MDIO interface
+ * @value: PHY register value
+ *
+ * Reads specified PHY register value
+ **/
+enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw,
+ u8 page, u16 reg, u8 phy_addr, u16 *value)
+{
+ enum i40e_status_code status;
+
+ switch (hw->device_id) {
+ case I40E_DEV_ID_1G_BASE_T_X722:
+ status = i40e_read_phy_register_clause22(hw, reg, phy_addr,
+ value);
+ break;
+ case I40E_DEV_ID_10G_BASE_T:
+ case I40E_DEV_ID_10G_BASE_T4:
+ case I40E_DEV_ID_10G_BASE_T_X722:
+ case I40E_DEV_ID_25G_B:
+ case I40E_DEV_ID_25G_SFP28:
+ status = i40e_read_phy_register_clause45(hw, page, reg,
+ phy_addr, value);
+ break;
+ default:
+ status = I40E_ERR_UNKNOWN_PHY;
+ break;
+ }
+
+ return status;
+}
+
+/**
* i40e_get_phy_address
* @hw: pointer to the HW structure
* @dev_num: PHY port num that address we want
@@ -6206,14 +6361,16 @@ enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw,
for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
led_addr++) {
- status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
- led_addr, phy_addr, &led_reg);
+ status = i40e_read_phy_register_clause45(hw,
+ I40E_PHY_COM_REG_PAGE,
+ led_addr, phy_addr,
+ &led_reg);
if (status)
goto phy_blinking_end;
led_ctl = led_reg;
if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
led_reg = 0;
- status = i40e_write_phy_register(hw,
+ status = i40e_write_phy_register_clause45(hw,
I40E_PHY_COM_REG_PAGE,
led_addr, phy_addr,
led_reg);
@@ -6225,20 +6382,18 @@ enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw,
if (time > 0 && interval > 0) {
for (i = 0; i < time * 1000; i += interval) {
- status = i40e_read_phy_register(hw,
- I40E_PHY_COM_REG_PAGE,
- led_addr, phy_addr,
- &led_reg);
+ status = i40e_read_phy_register_clause45(hw,
+ I40E_PHY_COM_REG_PAGE,
+ led_addr, phy_addr, &led_reg);
if (status)
goto restore_config;
if (led_reg & I40E_PHY_LED_MANUAL_ON)
led_reg = 0;
else
led_reg = I40E_PHY_LED_MANUAL_ON;
- status = i40e_write_phy_register(hw,
- I40E_PHY_COM_REG_PAGE,
- led_addr, phy_addr,
- led_reg);
+ status = i40e_write_phy_register_clause45(hw,
+ I40E_PHY_COM_REG_PAGE,
+ led_addr, phy_addr, led_reg);
if (status)
goto restore_config;
i40e_msec_delay(interval);
@@ -6246,8 +6401,9 @@ enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw,
}
restore_config:
- status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
- phy_addr, led_ctl);
+ status = i40e_write_phy_register_clause45(hw,
+ I40E_PHY_COM_REG_PAGE,
+ led_addr, phy_addr, led_ctl);
phy_blinking_end:
return status;
@@ -6278,8 +6434,10 @@ enum i40e_status_code i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
temp_addr++) {
- status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
- temp_addr, phy_addr, ®_val);
+ status = i40e_read_phy_register_clause45(hw,
+ I40E_PHY_COM_REG_PAGE,
+ temp_addr, phy_addr,
+ ®_val);
if (status)
return status;
*val = reg_val;
@@ -6312,41 +6470,42 @@ enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on,
i = rd32(hw, I40E_PFGEN_PORTNUM);
port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
phy_addr = i40e_get_phy_address(hw, port_num);
-
- status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
- phy_addr, &led_reg);
+ status = i40e_read_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
+ led_addr, phy_addr, &led_reg);
if (status)
return status;
led_ctl = led_reg;
if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
led_reg = 0;
- status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE,
- led_addr, phy_addr, led_reg);
+ status = i40e_write_phy_register_clause45(hw,
+ I40E_PHY_COM_REG_PAGE,
+ led_addr, phy_addr,
+ led_reg);
if (status)
return status;
}
- status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
- led_addr, phy_addr, &led_reg);
+ status = i40e_read_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
+ led_addr, phy_addr, &led_reg);
if (status)
goto restore_config;
if (on)
led_reg = I40E_PHY_LED_MANUAL_ON;
else
led_reg = 0;
- status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE,
- led_addr, phy_addr, led_reg);
+ status = i40e_write_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
+ led_addr, phy_addr, led_reg);
if (status)
goto restore_config;
if (mode & I40E_PHY_LED_MODE_ORIG) {
led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
- status = i40e_write_phy_register(hw,
+ status = i40e_write_phy_register_clause45(hw,
I40E_PHY_COM_REG_PAGE,
led_addr, phy_addr, led_ctl);
}
return status;
restore_config:
- status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
- phy_addr, led_ctl);
+ status = i40e_write_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
+ led_addr, phy_addr, led_ctl);
return status;
}
#endif /* PF_DRIVER */
diff --git a/drivers/net/i40e/base/i40e_prototype.h b/drivers/net/i40e/base/i40e_prototype.h
index 3aab5ca..9109cfc 100644
--- a/drivers/net/i40e/base/i40e_prototype.h
+++ b/drivers/net/i40e/base/i40e_prototype.h
@@ -538,10 +538,18 @@ enum i40e_status_code i40e_aq_get_wake_event_reason(struct i40e_hw *hw,
u16 *wake_reason,
struct i40e_asq_cmd_details *cmd_details);
#endif
-enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw, u8 page,
- u16 reg, u8 phy_addr, u16 *value);
-enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw, u8 page,
- u16 reg, u8 phy_addr, u16 value);
+enum i40e_status_code i40e_read_phy_register_clause22(struct i40e_hw *hw,
+ u16 reg, u8 phy_addr, u16 *value);
+enum i40e_status_code i40e_write_phy_register_clause22(struct i40e_hw *hw,
+ u16 reg, u8 phy_addr, u16 value);
+enum i40e_status_code i40e_read_phy_register_clause45(struct i40e_hw *hw,
+ u8 page, u16 reg, u8 phy_addr, u16 *value);
+enum i40e_status_code i40e_write_phy_register_clause45(struct i40e_hw *hw,
+ u8 page, u16 reg, u8 phy_addr, u16 value);
+enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw,
+ u8 page, u16 reg, u8 phy_addr, u16 *value);
+enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw,
+ u8 page, u16 reg, u8 phy_addr, u16 value);
u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num);
enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw,
u32 time, u32 interval);
diff --git a/drivers/net/i40e/base/i40e_type.h b/drivers/net/i40e/base/i40e_type.h
index b5f72c3..5a59ce2 100644
--- a/drivers/net/i40e/base/i40e_type.h
+++ b/drivers/net/i40e/base/i40e_type.h
@@ -157,15 +157,22 @@ enum i40e_debug_mask {
#define I40E_PCI_LINK_SPEED_5000 0x2
#define I40E_PCI_LINK_SPEED_8000 0x3
-#define I40E_MDIO_STCODE I40E_MASK(0, \
+#define I40E_MDIO_CLAUSE22_STCODE_MASK I40E_MASK(1, \
I40E_GLGEN_MSCA_STCODE_SHIFT)
-#define I40E_MDIO_OPCODE_ADDRESS I40E_MASK(0, \
+#define I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK I40E_MASK(1, \
I40E_GLGEN_MSCA_OPCODE_SHIFT)
-#define I40E_MDIO_OPCODE_WRITE I40E_MASK(1, \
+#define I40E_MDIO_CLAUSE22_OPCODE_READ_MASK I40E_MASK(2, \
I40E_GLGEN_MSCA_OPCODE_SHIFT)
-#define I40E_MDIO_OPCODE_READ_INC_ADDR I40E_MASK(2, \
+
+#define I40E_MDIO_CLAUSE45_STCODE_MASK I40E_MASK(0, \
+ I40E_GLGEN_MSCA_STCODE_SHIFT)
+#define I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK I40E_MASK(0, \
+ I40E_GLGEN_MSCA_OPCODE_SHIFT)
+#define I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK I40E_MASK(1, \
+ I40E_GLGEN_MSCA_OPCODE_SHIFT)
+#define I40E_MDIO_CLAUSE45_OPCODE_READ_INC_ADDR_MASK I40E_MASK(2, \
I40E_GLGEN_MSCA_OPCODE_SHIFT)
-#define I40E_MDIO_OPCODE_READ I40E_MASK(3, \
+#define I40E_MDIO_CLAUSE45_OPCODE_READ_MASK I40E_MASK(3, \
I40E_GLGEN_MSCA_OPCODE_SHIFT)
#define I40E_PHY_COM_REG_PAGE 0x1E
--
2.4.11
next prev parent reply other threads:[~2016-12-10 11:26 UTC|newest]
Thread overview: 108+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-12-03 1:18 [dpdk-dev] [PATCH 00/31] net/i40e: base code update Jingjing Wu
2016-12-03 1:18 ` [dpdk-dev] [PATCH 01/31] net/i40e/base: add encap csum VF offload flag Jingjing Wu
2016-12-03 1:18 ` [dpdk-dev] [PATCH 02/31] net/i40e/base: preserve extended PHY type field Jingjing Wu
2016-12-05 14:34 ` Ferruh Yigit
2016-12-03 1:18 ` [dpdk-dev] [PATCH 03/31] net/i40e/base: remove unnecessary code Jingjing Wu
2016-12-03 1:18 ` [dpdk-dev] [PATCH 04/31] net/i40e/base: fix bit test mask Jingjing Wu
2016-12-05 14:37 ` Ferruh Yigit
2016-12-03 1:18 ` [dpdk-dev] [PATCH 05/31] net/i40e/base: group base mode VF offload flags Jingjing Wu
2016-12-03 1:18 ` [dpdk-dev] [PATCH 06/31] net/i40e/base: fix long link down notification time Jingjing Wu
2016-12-03 1:18 ` [dpdk-dev] [PATCH 07/31] net/i40e/base: add media type detection for 25G link Jingjing Wu
2016-12-03 1:18 ` [dpdk-dev] [PATCH 08/31] net/i40e/base: add clause22 and clause45 implementation Jingjing Wu
2016-12-03 1:18 ` [dpdk-dev] [PATCH 09/31] net/i40e/base: add bus number info Jingjing Wu
2016-12-03 1:18 ` [dpdk-dev] [PATCH 10/31] net/i40e/base: add protocols when discover capabilities Jingjing Wu
2016-12-03 1:18 ` [dpdk-dev] [PATCH 11/31] net/i40e/base: pass unknown PHY type for unknown PHYs Jingjing Wu
2016-12-03 1:18 ` [dpdk-dev] [PATCH 12/31] net/i40e/base: replace memcpy Jingjing Wu
2016-12-03 1:18 ` [dpdk-dev] [PATCH 13/31] net/i40e/base: deprecating unused macro Jingjing Wu
2016-12-03 1:18 ` [dpdk-dev] [PATCH 14/31] net/i40e/base: remove FPK HyperV VF device ID Jingjing Wu
2016-12-03 1:18 ` [dpdk-dev] [PATCH 15/31] net/i40e/base: add FEC bits to PHY capabilities Jingjing Wu
2016-12-05 14:30 ` Ferruh Yigit
2016-12-03 1:18 ` [dpdk-dev] [PATCH 16/31] net/i40e/base: use BIT() macro instead of bit fields Jingjing Wu
2016-12-03 1:18 ` [dpdk-dev] [PATCH 17/31] net/i40e/base: adjust 25G PHY type values Jingjing Wu
2016-12-03 1:19 ` [dpdk-dev] [PATCH 18/31] net/i40e/base: implement clear all WoL filters Jingjing Wu
2016-12-03 1:19 ` [dpdk-dev] [PATCH 19/31] net/i40e/base: implement set VSI full promisc mode Jingjing Wu
2016-12-03 1:19 ` [dpdk-dev] [PATCH 20/31] net/i40e/base: add defines for new aq command Jingjing Wu
2016-12-03 1:19 ` [dpdk-dev] [PATCH 21/31] net/i40e/base: save link FEC info from link up event Jingjing Wu
2016-12-03 1:19 ` [dpdk-dev] [PATCH 22/31] net/i40e/base: acquire NVM lock before reads on all devices Jingjing Wu
2016-12-03 1:19 ` [dpdk-dev] [PATCH 23/31] net/i40e/base: change shift values to hex Jingjing Wu
2016-12-03 1:19 ` [dpdk-dev] [PATCH 24/31] net/i40e/base: comment that udp port must be in Host order Jingjing Wu
2016-12-03 1:19 ` [dpdk-dev] [PATCH 25/31] net/i40e/base: remove duplicate definitions Jingjing Wu
2016-12-05 14:52 ` Ferruh Yigit
2016-12-03 1:19 ` [dpdk-dev] [PATCH 26/31] net/i40e/base: add ERROR state for NVM update state machine Jingjing Wu
2016-12-03 1:19 ` [dpdk-dev] [PATCH 27/31] net/i40e/base: add broadcast promiscuous control per VLAN Jingjing Wu
2016-12-03 1:19 ` [dpdk-dev] [PATCH 28/31] net/i40e/base: avoid division by zero Jingjing Wu
2016-12-03 1:19 ` [dpdk-dev] [PATCH 29/31] net/i40e/base: fix byte order Jingjing Wu
2016-12-03 1:19 ` [dpdk-dev] [PATCH 30/31] net/i40e/base: remove unused marco Jingjing Wu
2016-12-05 14:55 ` Ferruh Yigit
2016-12-06 6:43 ` Wu, Jingjing
2016-12-03 1:19 ` [dpdk-dev] [PATCH 31/31] net/i40e: remove unused marco from PMD Jingjing Wu
2016-12-05 14:57 ` Ferruh Yigit
2016-12-09 14:38 ` [dpdk-dev] [PATCH v2 00/31] net/i40e: base code update Jingjing Wu
2016-12-09 14:38 ` [dpdk-dev] [PATCH v2 01/31] net/i40e/base: add encap csum VF offload flag Jingjing Wu
2016-12-09 14:38 ` [dpdk-dev] [PATCH v2 02/31] net/i40e/base: preserve extended PHY type field Jingjing Wu
2016-12-09 14:38 ` [dpdk-dev] [PATCH v2 03/31] net/i40e/base: remove unnecessary code Jingjing Wu
2016-12-09 14:38 ` [dpdk-dev] [PATCH v2 04/31] net/i40e/base: fix bit test mask Jingjing Wu
2016-12-09 14:38 ` [dpdk-dev] [PATCH v2 05/31] net/i40e/base: group base mode VF offload flags Jingjing Wu
2016-12-09 14:38 ` [dpdk-dev] [PATCH v2 06/31] net/i40e/base: fix long link down notification time Jingjing Wu
2016-12-09 14:39 ` [dpdk-dev] [PATCH v2 07/31] net/i40e/base: add media type detection for 25G link Jingjing Wu
2016-12-09 14:39 ` [dpdk-dev] [PATCH v2 08/31] net/i40e/base: add clause22 and clause45 implementation Jingjing Wu
2016-12-09 14:39 ` [dpdk-dev] [PATCH v2 09/31] net/i40e/base: add bus number info Jingjing Wu
2016-12-09 14:39 ` [dpdk-dev] [PATCH v2 10/31] net/i40e/base: add protocols when discover capabilities Jingjing Wu
2016-12-09 14:39 ` [dpdk-dev] [PATCH v2 11/31] net/i40e/base: pass unknown PHY type for unknown PHYs Jingjing Wu
2016-12-09 14:39 ` [dpdk-dev] [PATCH v2 12/31] net/i40e/base: replace memcpy Jingjing Wu
2016-12-09 14:39 ` [dpdk-dev] [PATCH v2 13/31] net/i40e/base: deprecating unused macro Jingjing Wu
2016-12-09 14:39 ` [dpdk-dev] [PATCH v2 14/31] net/i40e/base: remove FPK HyperV VF device ID Jingjing Wu
2016-12-09 14:39 ` [dpdk-dev] [PATCH v2 15/31] net/i40e/base: add FEC bits to PHY capabilities Jingjing Wu
2016-12-09 14:39 ` [dpdk-dev] [PATCH v2 16/31] net/i40e/base: use BIT() macro instead of bit fields Jingjing Wu
2016-12-09 14:39 ` [dpdk-dev] [PATCH v2 17/31] net/i40e/base: adjust 25G PHY type values Jingjing Wu
2016-12-09 14:39 ` [dpdk-dev] [PATCH v2 18/31] net/i40e/base: implement clear all WoL filters Jingjing Wu
2016-12-09 14:39 ` [dpdk-dev] [PATCH v2 19/31] net/i40e/base: implement set VSI full promisc mode Jingjing Wu
2016-12-09 14:39 ` [dpdk-dev] [PATCH v2 20/31] net/i40e/base: add defines for new aq command Jingjing Wu
2016-12-09 14:39 ` [dpdk-dev] [PATCH v2 21/31] net/i40e/base: save link FEC info from link up event Jingjing Wu
2016-12-09 14:39 ` [dpdk-dev] [PATCH v2 22/31] net/i40e/base: acquire NVM lock before reads on all devices Jingjing Wu
2016-12-09 14:39 ` [dpdk-dev] [PATCH v2 23/31] net/i40e/base: change shift values to hex Jingjing Wu
2016-12-09 14:39 ` [dpdk-dev] [PATCH v2 24/31] net/i40e/base: comment that udp port must be in Host order Jingjing Wu
2016-12-09 14:39 ` [dpdk-dev] [PATCH v2 25/31] net/i40e/base: remove duplicate definitions Jingjing Wu
2016-12-09 14:39 ` [dpdk-dev] [PATCH v2 26/31] net/i40e/base: add ERROR state for NVM update state machine Jingjing Wu
2016-12-09 14:39 ` [dpdk-dev] [PATCH v2 27/31] net/i40e/base: add broadcast promiscuous control per VLAN Jingjing Wu
2016-12-09 14:39 ` [dpdk-dev] [PATCH v2 28/31] net/i40e/base: avoid division by zero Jingjing Wu
2016-12-09 14:39 ` [dpdk-dev] [PATCH v2 29/31] net/i40e/base: fix byte order Jingjing Wu
2016-12-09 14:39 ` [dpdk-dev] [PATCH v2 30/31] net/i40e/base: remove unused macro Jingjing Wu
2016-12-09 14:39 ` [dpdk-dev] [PATCH v2 31/31] net/i40e: remove unused macro from PMD Jingjing Wu
2016-12-09 16:08 ` [dpdk-dev] [PATCH v2 00/31] net/i40e: base code update Ferruh Yigit
2016-12-10 11:24 ` [dpdk-dev] [PATCH v3 " Jingjing Wu
2016-12-10 11:24 ` [dpdk-dev] [PATCH v3 01/31] net/i40e/base: add encap csum VF offload flag Jingjing Wu
2016-12-10 11:24 ` [dpdk-dev] [PATCH v3 02/31] net/i40e/base: fix flow control set for 25G Jingjing Wu
2016-12-10 11:24 ` [dpdk-dev] [PATCH v3 03/31] net/i40e/base: remove unnecessary code Jingjing Wu
2016-12-10 11:24 ` [dpdk-dev] [PATCH v3 04/31] net/i40e/base: fix bit test mask Jingjing Wu
2016-12-10 11:24 ` [dpdk-dev] [PATCH v3 05/31] net/i40e/base: group base mode VF offload flags Jingjing Wu
2016-12-10 11:24 ` [dpdk-dev] [PATCH v3 06/31] net/i40e/base: fix long link down notification time Jingjing Wu
2016-12-10 11:24 ` [dpdk-dev] [PATCH v3 07/31] net/i40e/base: add media type detection for 25G link Jingjing Wu
2016-12-10 11:24 ` Jingjing Wu [this message]
2016-12-10 11:24 ` [dpdk-dev] [PATCH v3 09/31] net/i40e/base: add bus number info Jingjing Wu
2016-12-10 11:24 ` [dpdk-dev] [PATCH v3 10/31] net/i40e/base: add protocols when discover capabilities Jingjing Wu
2016-12-10 11:24 ` [dpdk-dev] [PATCH v3 11/31] net/i40e/base: fix unknown PHYs incorrect identification Jingjing Wu
2016-12-10 11:24 ` [dpdk-dev] [PATCH v3 12/31] net/i40e/base: replace memcpy Jingjing Wu
2016-12-10 11:24 ` [dpdk-dev] [PATCH v3 13/31] net/i40e/base: deprecating unused macro Jingjing Wu
2016-12-10 11:24 ` [dpdk-dev] [PATCH v3 14/31] net/i40e/base: remove FPK HyperV VF device ID Jingjing Wu
2016-12-10 11:24 ` [dpdk-dev] [PATCH v3 15/31] net/i40e/base: add FEC bits to PHY capabilities Jingjing Wu
2016-12-10 11:24 ` [dpdk-dev] [PATCH v3 16/31] net/i40e/base: use BIT() macro instead of bit fields Jingjing Wu
2016-12-10 11:24 ` [dpdk-dev] [PATCH v3 17/31] net/i40e/base: adjust 25G PHY type values Jingjing Wu
2016-12-10 11:24 ` [dpdk-dev] [PATCH v3 18/31] net/i40e/base: implement clear all WoL filters Jingjing Wu
2016-12-10 11:24 ` [dpdk-dev] [PATCH v3 19/31] net/i40e/base: implement set VSI full promisc mode Jingjing Wu
2016-12-10 11:24 ` [dpdk-dev] [PATCH v3 20/31] net/i40e/base: fix wol failure on PF reset Jingjing Wu
2016-12-10 11:24 ` [dpdk-dev] [PATCH v3 21/31] net/i40e/base: save link FEC info from link up event Jingjing Wu
2016-12-10 11:24 ` [dpdk-dev] [PATCH v3 22/31] net/i40e/base: fix NVM access intefering Jingjing Wu
2016-12-10 11:24 ` [dpdk-dev] [PATCH v3 23/31] net/i40e/base: change shift values to hex Jingjing Wu
2016-12-10 11:24 ` [dpdk-dev] [PATCH v3 24/31] net/i40e/base: comment that udp port must be in Host order Jingjing Wu
2016-12-10 11:24 ` [dpdk-dev] [PATCH v3 25/31] net/i40e/base: remove duplicate definitions Jingjing Wu
2016-12-10 11:24 ` [dpdk-dev] [PATCH v3 26/31] net/i40e/base: add ERROR state for NVM update state machine Jingjing Wu
2016-12-10 11:24 ` [dpdk-dev] [PATCH v3 27/31] net/i40e/base: add broadcast promiscuous control per VLAN Jingjing Wu
2016-12-10 11:24 ` [dpdk-dev] [PATCH v3 28/31] net/i40e/base: fix division by zero Jingjing Wu
2016-12-10 11:24 ` [dpdk-dev] [PATCH v3 29/31] net/i40e/base: fix byte order Jingjing Wu
2016-12-10 11:24 ` [dpdk-dev] [PATCH v3 30/31] net/i40e/base: remove unused macro Jingjing Wu
2016-12-10 11:24 ` [dpdk-dev] [PATCH v3 31/31] net/i40e: remove unused macro from PMD Jingjing Wu
2016-12-12 10:32 ` [dpdk-dev] [PATCH v3 00/31] net/i40e: base code update Ferruh Yigit
2016-12-20 15:40 ` Gregory Etelson
2016-12-20 16:21 ` Gregory Etelson
2017-01-12 11:48 ` Ferruh Yigit
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