From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0b-0016ce01.pphosted.com (mx0b-0016ce01.pphosted.com [67.231.156.153]) by dpdk.org (Postfix) with ESMTP id 09635F94F for ; Mon, 27 Feb 2017 08:58:43 +0100 (CET) Received: from pps.filterd (m0085408.ppops.net [127.0.0.1]) by mx0b-0016ce01.pphosted.com (8.16.0.20/8.16.0.20) with SMTP id v1R7vTnq010874; Sun, 26 Feb 2017 23:58:42 -0800 Received: from avcashub1.qlogic.com ([198.186.0.115]) by mx0b-0016ce01.pphosted.com with ESMTP id 28ut281v3d-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Sun, 26 Feb 2017 23:58:42 -0800 Received: from avluser05.qlc.com (10.1.113.115) by avcashub1.qlogic.org (10.1.4.190) with Microsoft SMTP Server (TLS) id 14.3.235.1; Sun, 26 Feb 2017 23:58:41 -0800 Received: (from rmody@localhost) by avluser05.qlc.com (8.14.4/8.14.4/Submit) id v1R7wfwt010489; Sun, 26 Feb 2017 23:58:41 -0800 X-Authentication-Warning: avluser05.qlc.com: rmody set sender to rasesh.mody@cavium.com using -f From: Rasesh Mody To: CC: Rasesh Mody , Date: Sun, 26 Feb 2017 23:57:14 -0800 Message-ID: <1488182237-10247-59-git-send-email-rasesh.mody@cavium.com> X-Mailer: git-send-email 1.7.10.3 In-Reply-To: <1488182237-10247-1-git-send-email-rasesh.mody@cavium.com> References: <1488182237-10247-1-git-send-email-rasesh.mody@cavium.com> MIME-Version: 1.0 Content-Type: text/plain disclaimer: bypass X-Proofpoint-Virus-Version: vendor=nai engine=5800 definitions=8451 signatures=669242 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1702020001 definitions=main-1702270081 Subject: [dpdk-dev] [PATCH 58/61] net/qede/base: semantic changes X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 27 Feb 2017 07:58:44 -0000 Make APIs static and other semantic changes. A step toward cleaning 'make C=1' with GCC 4.8.3. Signed-off-by: Rasesh Mody --- drivers/net/qede/base/ecore_cxt.c | 5 +- drivers/net/qede/base/ecore_cxt.h | 11 ---- drivers/net/qede/base/ecore_dcbx.c | 2 +- drivers/net/qede/base/ecore_dev.c | 111 ++++++++++++++++++------------------ drivers/net/qede/base/ecore_l2.c | 12 ++-- drivers/net/qede/base/ecore_vf.c | 2 +- 6 files changed, 68 insertions(+), 75 deletions(-) diff --git a/drivers/net/qede/base/ecore_cxt.c b/drivers/net/qede/base/ecore_cxt.c index b3d939a..d94db8b 100644 --- a/drivers/net/qede/base/ecore_cxt.c +++ b/drivers/net/qede/base/ecore_cxt.c @@ -327,7 +327,8 @@ static OSAL_INLINE void ecore_cxt_tm_iids(struct ecore_cxt_mngr *p_mngr, } } -void ecore_cxt_qm_iids(struct ecore_hwfn *p_hwfn, struct ecore_qm_iids *iids) +static void ecore_cxt_qm_iids(struct ecore_hwfn *p_hwfn, + struct ecore_qm_iids *iids) { struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; struct ecore_tid_seg *segs; @@ -1948,7 +1949,7 @@ enum _ecore_status_t ecore_cxt_get_cid_info(struct ecore_hwfn *p_hwfn, return ECORE_SUCCESS; } -void ecore_cxt_set_srq_count(struct ecore_hwfn *p_hwfn, u32 num_srqs) +static void ecore_cxt_set_srq_count(struct ecore_hwfn *p_hwfn, u32 num_srqs) { struct ecore_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr; diff --git a/drivers/net/qede/base/ecore_cxt.h b/drivers/net/qede/base/ecore_cxt.h index 1128051..e678118 100644 --- a/drivers/net/qede/base/ecore_cxt.h +++ b/drivers/net/qede/base/ecore_cxt.h @@ -35,17 +35,6 @@ u32 ecore_cxt_get_proto_cid_start(struct ecore_hwfn *p_hwfn, enum protocol_type type); u32 ecore_cxt_get_srq_count(struct ecore_hwfn *p_hwfn); -#ifndef LINUX_REMOVE -/** - * @brief ecore_cxt_qm_iids - fills the cid/tid counts for the QM configuration - * - * @param p_hwfn - * @param iids [out], a structure holding all the counters - */ -void ecore_cxt_qm_iids(struct ecore_hwfn *p_hwfn, - struct ecore_qm_iids *iids); -#endif - /** * @brief ecore_cxt_set_pf_params - Set the PF params for cxt init * diff --git a/drivers/net/qede/base/ecore_dcbx.c b/drivers/net/qede/base/ecore_dcbx.c index e31ce81..156eb0e 100644 --- a/drivers/net/qede/base/ecore_dcbx.c +++ b/drivers/net/qede/base/ecore_dcbx.c @@ -114,7 +114,7 @@ static bool ecore_dcbx_iwarp_tlv(struct ecore_hwfn *p_hwfn, u32 app_info_bitmap, } } -void +static void ecore_dcbx_set_params(struct ecore_dcbx_results *p_data, struct ecore_hwfn *p_hwfn, bool enable, u8 prio, u8 tc, diff --git a/drivers/net/qede/base/ecore_dev.c b/drivers/net/qede/base/ecore_dev.c index 66fd22b..10257f3 100644 --- a/drivers/net/qede/base/ecore_dev.c +++ b/drivers/net/qede/base/ecore_dev.c @@ -765,8 +765,8 @@ enum _ecore_status_t ecore_qm_reconf(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt) { struct ecore_qm_info *qm_info = &p_hwfn->qm_info; - enum _ecore_status_t rc; bool b_rc; + enum _ecore_status_t rc; /* initialize ecore's qm data structure */ ecore_init_qm_info(p_hwfn); @@ -1513,54 +1513,6 @@ static void ecore_link_init_bb(struct ecore_hwfn *p_hwfn, } #endif -static enum _ecore_status_t ecore_hw_init_port(struct ecore_hwfn *p_hwfn, - struct ecore_ptt *p_ptt, - int hw_mode) -{ - enum _ecore_status_t rc = ECORE_SUCCESS; - - rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id, - hw_mode); - if (rc != ECORE_SUCCESS) - return rc; -#ifndef ASIC_ONLY - if (CHIP_REV_IS_ASIC(p_hwfn->p_dev)) - return ECORE_SUCCESS; - - if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) { - if (ECORE_IS_AH(p_hwfn->p_dev)) - return ECORE_SUCCESS; - else if (ECORE_IS_BB(p_hwfn->p_dev)) - ecore_link_init_bb(p_hwfn, p_ptt, p_hwfn->port_id); - } else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) { - if (p_hwfn->p_dev->num_hwfns > 1) { - /* Activate OPTE in CMT */ - u32 val; - - val = ecore_rd(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV); - val |= 0x10; - ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV, val); - ecore_wr(p_hwfn, p_ptt, MISC_REG_CLK_100G_MODE, 1); - ecore_wr(p_hwfn, p_ptt, MISCS_REG_CLK_100G_MODE, 1); - ecore_wr(p_hwfn, p_ptt, MISC_REG_OPTE_MODE, 1); - ecore_wr(p_hwfn, p_ptt, - NIG_REG_LLH_ENG_CLS_TCP_4_TUPLE_SEARCH, 1); - ecore_wr(p_hwfn, p_ptt, - NIG_REG_LLH_ENG_CLS_ENG_ID_TBL, 0x55555555); - ecore_wr(p_hwfn, p_ptt, - NIG_REG_LLH_ENG_CLS_ENG_ID_TBL + 0x4, - 0x55555555); - } - - ecore_emul_link_init(p_hwfn, p_ptt); - } else { - DP_INFO(p_hwfn->p_dev, "link is not being configured\n"); - } -#endif - - return rc; -} - static enum _ecore_status_t ecore_hw_init_dpi_size(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus) @@ -1629,7 +1581,7 @@ enum ECORE_ROCE_EDPM_MODE { u32 db_bar_size, n_cpus; u32 roce_edpm_mode; u32 pf_dems_shift; - int rc = ECORE_SUCCESS; + enum _ecore_status_t rc = ECORE_SUCCESS; u8 cond; db_bar_size = ecore_hw_bar_size(p_hwfn, BAR_ID_1); @@ -1684,8 +1636,9 @@ enum ECORE_ROCE_EDPM_MODE { rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus); } - cond = ((rc) && (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE)) || - (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_DISABLE); + cond = ((rc != ECORE_SUCCESS) && + (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE)) || + (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_DISABLE); if (cond || p_hwfn->dcbx_no_edpm) { /* Either EDPM is disabled from user configuration, or it is * disabled via DCBx, or it is not mandatory and we failed to @@ -1709,7 +1662,7 @@ enum ECORE_ROCE_EDPM_MODE { "disabled" : "enabled"); /* Check return codes from above calls */ - if (rc) { + if (rc != ECORE_SUCCESS) { DP_ERR(p_hwfn, "Failed to allocate enough DPIs\n"); return ECORE_NORESOURCES; @@ -1727,6 +1680,56 @@ enum ECORE_ROCE_EDPM_MODE { return ECORE_SUCCESS; } +static enum _ecore_status_t ecore_hw_init_port(struct ecore_hwfn *p_hwfn, + struct ecore_ptt *p_ptt, + int hw_mode) +{ + enum _ecore_status_t rc = ECORE_SUCCESS; + + rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id, + hw_mode); + if (rc != ECORE_SUCCESS) + return rc; +#ifndef ASIC_ONLY + if (CHIP_REV_IS_ASIC(p_hwfn->p_dev)) + return ECORE_SUCCESS; + + if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) { + if (ECORE_IS_AH(p_hwfn->p_dev)) + return ECORE_SUCCESS; + else if (ECORE_IS_BB(p_hwfn->p_dev)) + ecore_link_init_bb(p_hwfn, p_ptt, p_hwfn->port_id); + else /* E5 */ + ECORE_E5_MISSING_CODE; + } else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) { + if (p_hwfn->p_dev->num_hwfns > 1) { + /* Activate OPTE in CMT */ + u32 val; + + val = ecore_rd(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV); + val |= 0x10; + ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV, val); + ecore_wr(p_hwfn, p_ptt, MISC_REG_CLK_100G_MODE, 1); + ecore_wr(p_hwfn, p_ptt, MISCS_REG_CLK_100G_MODE, 1); + ecore_wr(p_hwfn, p_ptt, MISC_REG_OPTE_MODE, 1); + ecore_wr(p_hwfn, p_ptt, + NIG_REG_LLH_ENG_CLS_TCP_4_TUPLE_SEARCH, 1); + ecore_wr(p_hwfn, p_ptt, + NIG_REG_LLH_ENG_CLS_ENG_ID_TBL, 0x55555555); + ecore_wr(p_hwfn, p_ptt, + NIG_REG_LLH_ENG_CLS_ENG_ID_TBL + 0x4, + 0x55555555); + } + + ecore_emul_link_init(p_hwfn, p_ptt); + } else { + DP_INFO(p_hwfn->p_dev, "link is not being configured\n"); + } +#endif + + return rc; +} + static enum _ecore_status_t ecore_hw_init_pf(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, @@ -1928,8 +1931,8 @@ enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev, { struct ecore_load_req_params load_req_params; u32 load_code, param, drv_mb_param; - struct ecore_hwfn *p_hwfn; bool b_default_mtu = true; + struct ecore_hwfn *p_hwfn; enum _ecore_status_t rc = ECORE_SUCCESS, mfw_rc; int i; diff --git a/drivers/net/qede/base/ecore_l2.c b/drivers/net/qede/base/ecore_l2.c index adb5e47..c4af895 100644 --- a/drivers/net/qede/base/ecore_l2.c +++ b/drivers/net/qede/base/ecore_l2.c @@ -946,17 +946,17 @@ enum _ecore_status_t dma_addr_t bd_chain_phys_addr, dma_addr_t cqe_pbl_addr, u16 cqe_pbl_size, - void OSAL_IOMEM * *pp_producer) + void OSAL_IOMEM * *pp_prod) { u32 init_prod_val = 0; - *pp_producer = (u8 OSAL_IOMEM *) - p_hwfn->regview + - GTT_BAR0_MAP_REG_MSDM_RAM + - MSTORM_ETH_PF_PRODS_OFFSET(p_cid->abs.queue_id); + *pp_prod = (u8 OSAL_IOMEM *) + p_hwfn->regview + + GTT_BAR0_MAP_REG_MSDM_RAM + + MSTORM_ETH_PF_PRODS_OFFSET(p_cid->abs.queue_id); /* Init the rcq, rx bd and rx sge (if valid) producers to 0 */ - __internal_ram_wr(p_hwfn, *pp_producer, sizeof(u32), + __internal_ram_wr(p_hwfn, *pp_prod, sizeof(u32), (u32 *)(&init_prod_val)); return ecore_eth_rxq_start_ramrod(p_hwfn, p_cid, diff --git a/drivers/net/qede/base/ecore_vf.c b/drivers/net/qede/base/ecore_vf.c index 53fc0cf..2aaf4c8 100644 --- a/drivers/net/qede/base/ecore_vf.c +++ b/drivers/net/qede/base/ecore_vf.c @@ -1285,8 +1285,8 @@ enum _ecore_status_t ecore_vf_pf_release(struct ecore_hwfn *p_hwfn) struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info; struct pfvf_def_resp_tlv *resp; struct vfpf_first_tlv *req; - enum _ecore_status_t rc; u32 size; + enum _ecore_status_t rc; /* clear mailbox and prep first tlv */ req = ecore_vf_pf_prep(p_hwfn, CHANNEL_TLV_RELEASE, sizeof(*req)); -- 1.7.10.3