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Fri, 3 Mar 2017 17:29:48 +0000 From: Jerin Jacob To: dev@dpdk.org Cc: thomas.monjalon@6wind.com, bruce.richardson@intel.com, harry.van.haaren@intel.com, hemant.agrawal@nxp.com, gage.eads@intel.com, nipun.gupta@nxp.com, santosh.shukla@caviumnetworks.com, Jerin Jacob Date: Fri, 3 Mar 2017 22:57:56 +0530 Message-Id: <1488562101-6658-15-git-send-email-jerin.jacob@caviumnetworks.com> X-Mailer: git-send-email 2.5.5 In-Reply-To: <1488562101-6658-1-git-send-email-jerin.jacob@caviumnetworks.com> References: <1488562101-6658-1-git-send-email-jerin.jacob@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [14.140.2.178] X-ClientProxiedBy: BMXPR01CA0021.INDPRD01.PROD.OUTLOOK.COM (10.174.214.159) To BN3PR0701MB1719.namprd07.prod.outlook.com (10.163.39.18) X-MS-Office365-Filtering-Correlation-Id: e722316e-4b7b-4e2b-ff61-08d4625ae6a1 X-Microsoft-Antispam: UriScan:; BCL:0; PCL:0; RULEID:(22001); SRVR:BN3PR0701MB1719; X-Microsoft-Exchange-Diagnostics: 1; BN3PR0701MB1719; 3:CLA0dyUVZCJ6aws2pWNjNnfvM8hx0CGuquOOktLD/I671k199XOBKJkhTmwJMWnGVqEZVtMuUpRt/jwETlvMYkekw/UUduvSN+O+uC8TfA5gBS4wnx2ttwoKG8z4CK5aE/oxBkMt4DXsoSH+kJ/ZzqYro1NGjcqFvRvImdD2z/In+GFd6IH6dRhz3OWOJWa+v6Ya+fgxZ87xUZfZ1kjU3kwjqpFqG4QcfSeTEL0hPP1+1DjLX3NESOmJ2ghSDAVBGXUZYFyz5HBqunU9Xwz++w==; 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return 0; } + +static int +ssovf_port_link(struct rte_eventdev *dev, void *port, const uint8_t queues[], + const uint8_t priorities[], uint16_t nb_links) +{ + uint16_t link; + uint64_t val; + struct ssows *ws = port; + + ssovf_func_trace("port=%d nb_links=%d", ws->port, nb_links); + RTE_SET_USED(dev); + RTE_SET_USED(priorities); + + for (link = 0; link < nb_links; link++) { + val = queues[link]; + val |= (1ULL << 24); /* Set membership */ + ssovf_write64(val, ws->base + SSOW_VHWS_GRPMSK_CHGX(0)); + } + return (int)nb_links; +} + +static int +ssovf_port_unlink(struct rte_eventdev *dev, void *port, uint8_t queues[], + uint16_t nb_unlinks) +{ + uint16_t unlink; + uint64_t val; + struct ssows *ws = port; + + ssovf_func_trace("port=%d nb_links=%d", ws->port, nb_unlinks); + RTE_SET_USED(dev); + + for (unlink = 0; unlink < nb_unlinks; unlink++) { + val = queues[unlink]; + val &= ~(1ULL << 24); /* Clear membership */ + ssovf_write64(val, ws->base + SSOW_VHWS_GRPMSK_CHGX(0)); + } + return (int)nb_unlinks; +} + /* Initialize and register event driver with DPDK Application */ static const struct rte_eventdev_ops ssovf_ops = { .dev_infos_get = ssovf_info_get, @@ -265,6 +305,8 @@ static const struct rte_eventdev_ops ssovf_ops = { .port_def_conf = ssovf_port_def_conf, .port_setup = ssovf_port_setup, .port_release = ssovf_port_release, + .port_link = ssovf_port_link, + .port_unlink = ssovf_port_unlink, }; static int diff --git a/drivers/event/octeontx/ssovf_evdev.h b/drivers/event/octeontx/ssovf_evdev.h index eda0e37..9a6bac5 100644 --- a/drivers/event/octeontx/ssovf_evdev.h +++ b/drivers/event/octeontx/ssovf_evdev.h @@ -120,6 +120,14 @@ #define SSO_GRP_GET_PRIORITY 0x7 #define SSO_GRP_SET_PRIORITY 0x8 +/* + * In Cavium OcteonTX SoC, all accesses to the device registers are + * implictly strongly ordered. So, The relaxed version of IO operation is + * safe to use with out any IO memory barriers. + */ +#define ssovf_read64 rte_read64_relaxed +#define ssovf_write64 rte_write64_relaxed + struct ssovf_evdev { uint8_t max_event_queues; uint8_t max_event_ports; -- 2.5.5