From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from NAM03-CO1-obe.outbound.protection.outlook.com (mail-co1nam03on0071.outbound.protection.outlook.com [104.47.40.71]) by dpdk.org (Postfix) with ESMTP id 6B51699AE for ; Thu, 25 May 2017 20:09:46 +0200 (CEST) Received: from CY1PR03CA0021.namprd03.prod.outlook.com (2603:10b6:600::31) by BL2PR03MB164.namprd03.prod.outlook.com (2a01:111:e400:c0d::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1124.9; Thu, 25 May 2017 18:09:44 +0000 Received: from BL2FFO11FD023.protection.gbl (2a01:111:f400:7c09::136) by CY1PR03CA0021.outlook.office365.com (2603:10b6:600::31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1124.9 via Frontend Transport; Thu, 25 May 2017 18:09:44 +0000 Authentication-Results: spf=fail (sender IP is 192.88.168.50) smtp.mailfrom=nxp.com; nxp.com; dkim=none (message not signed) header.d=none;nxp.com; dmarc=fail action=none header.from=nxp.com; Received-SPF: Fail (protection.outlook.com: domain of nxp.com does not designate 192.88.168.50 as permitted sender) receiver=protection.outlook.com; client-ip=192.88.168.50; helo=tx30smr01.am.freescale.net; Received: from tx30smr01.am.freescale.net (192.88.168.50) by BL2FFO11FD023.mail.protection.outlook.com (10.173.161.102) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1075.5 via Frontend Transport; Thu, 25 May 2017 18:09:43 +0000 Received: from b27504-OptiPlex-790.ap.freescale.net (b27504-OptiPlex-790.ap.freescale.net [10.232.132.60]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id v4PI84WN022340; Thu, 25 May 2017 11:09:40 -0700 From: Nipun Gupta To: CC: , , , , , , Nipun Gupta Date: Thu, 25 May 2017 23:37:43 +0530 Message-ID: <1495735671-4917-13-git-send-email-nipun.gupta@nxp.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1495735671-4917-1-git-send-email-nipun.gupta@nxp.com> References: <1495735671-4917-1-git-send-email-nipun.gupta@nxp.com> X-EOPAttributedMessage: 0 X-Matching-Connectors: 131402093838404469; (91ab9b29-cfa4-454e-5278-08d120cd25b8); () X-Forefront-Antispam-Report: CIP:192.88.168.50; IPV:NLI; CTRY:US; EFV:NLI; SFV:NSPM; SFS:(10009020)(6009001)(336005)(39380400002)(39400400002)(39860400002)(39850400002)(39840400002)(39410400002)(39450400003)(2980300002)(1109001)(1110001)(339900001)(199003)(189002)(9170700003)(86362001)(76176999)(50986999)(8676002)(106466001)(33646002)(104016004)(2906002)(305945005)(5660300001)(77096006)(110136004)(2351001)(38730400002)(5890100001)(189998001)(47776003)(50226002)(81166006)(54906002)(53936002)(8936002)(8656002)(85426001)(5003940100001)(4326008)(48376002)(36756003)(498600001)(356003)(50466002)(105606002)(6916009)(2950100002); DIR:OUT; SFP:1101; SCL:1; SRVR:BL2PR03MB164; H:tx30smr01.am.freescale.net; FPR:; SPF:Fail; MLV:ovrnspm; A:1; MX:1; PTR:InfoDomainNonexistent; LANG:en; X-Microsoft-Exchange-Diagnostics: 1; BL2FFO11FD023; 1:p3QREblU0JCTTHhyZO24Kd0qTk+kho0qKCpmgzBE82HUDWgvHrcp3KooZ9ed5DF9jf+tD7CpJ7WHWlCt1Z0gPRqD0IqeAeoB+3VQzdfE7Hk6HLBWvn0CFewevq7QnOja/K8rsXBS7DnCibo27NgYu+wqxdpm+1YZGr5SaWst44vRTQFnB6s/ugTAhvSK0UyjPNMeu+yWzi9hi4biU4BwhagR05mhAja0p59TaatQ0n0FBIc15FfRTPc0G8cQQD4JcKznubljzIZ5sLT7mNWmp4KaW6w009pTOdLF5D396vLHhsRRF1CdLsKc+mpPBBrpa7D5YDvU8x8TIFHoOk0ZZOd1UTDT3bIGzHRIM2rA9BW369gALCzM8js0jMi3sX/mLoUtnVISXnIHeTz3qZ11qB68AUzS9eHNCRX2xmwHRtCeR9sYauJJp31B0zmRBAfY4HfQcpw0v5nowVd3RU/Cf8CSWmzAsBo092Taj0a6bT39j4uK8Yb0+HKpY+ePgyIbAxxbbQ6N4KwISLTqsGsq2Sn633rZcBlIQm198MykwS0g2UztrTev2jidzFFSbQL+vYvixZMM914xmHEXFhiD/csuCiVBZVKoRNjMsVodiYZx4vE6YWbUSAfaXF0yst5t/TokI/2mxApuglzhlsSbbg+jMLL6k/PfAg8FubjNWWxBXIuPwtchvu3j9WU7uTPAtXhcDg5nPPfm920upkEJBWl4B7gZyoGFVD0pmWtxJhFKU92A2vCsQNRn9i9/6r95lyD+pQn7tO0flrx3fjWzKg== MIME-Version: 1.0 Content-Type: text/plain X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL2PR03MB164: X-MS-Office365-Filtering-Correlation-Id: aedfe57a-7162-4abf-aa14-08d4a399386f X-Microsoft-Antispam: UriScan:; BCL:0; PCL:0; RULEID:(22001)(201703131430075)(201703131517081); SRVR:BL2PR03MB164; X-Microsoft-Exchange-Diagnostics: 1; BL2PR03MB164; 3:5JskDKx9/m091gMReESvpx8XHanMq531XSh574wLEY8SZ0apm28bFbR1+a+P5rIpvyCgdhJ+Zi5PHrG6V8yDssdIDTF0AKF2dxzfWScxhkIZ+7RNKxQUPoTN+6LsnHySosje/aRGip7q0IsaF8LBixaC6SHVT2tJHiSnpd1kQCnAHOprF5iiZ3YS4huEEYiu+i3mFmIBaJ7L7IZvpc3eDMAltvd6i6mJFGPwbmUGvXaHvJSLtApqUfgM9I06OweFd9iwt+NYm3qcV3085HVFVNsZOCeGDQexVSk2+GVZKSnbsDRsQPFqaJXTzdaLKucF8B8XkcpB80On2u0F1IJmknXtUChc6BALCeYtKpJLU5rvM1qOG08ojmrwY6X0Jz9/2oM/ROB64UE5iSRUyqSQaXEmRjx3PViPjyWOc3Z0chROHAth5Q7Tqs2wpeNQU0Uh; 25:quRF2BxMrlxKgD9553N4QsXoRSX8PySEMF29r1nlH8Rbq9VNG2jqe74DRLBCpbh96mcS/nhm86Dastb3264k5RL027dpk96+y11TD2l0zbyT/ro6kR0Dm4XUv6ZsS38Bt7QVd7GknEax0fDVw4Id8ahWnmlrQATH5ghXbo3Qu3TxyDWiwqPBJQaZnKtTslTFQ20dS71f2pp6oYBZe929hg+sWbrREJ3WgDKlQwtRBqsGxxvdWupLuso+Wch+3UfCJbkQn5aEl2bNbJohF1S7/rBeV/ZAzEfbrcXZD0NS9388NoLWy+i+oZWdjRRNd5/Kayxhwgf6zRYjTuOeQ2jwH/QdQB9Whb0nFT+n+OVWhg4TBgQeQeXsuu5qdSCBZLznMConcr2YyLFdubHmDeor8Oc5ItjNm3sSvEi4fxUWUPQ20iKfdnAA8NO7Dwg6GTpubL3lkRaRVhrPyN1vJHjANV3EeAuluofLE28mbFTYGSw= X-Microsoft-Exchange-Diagnostics: 1; BL2PR03MB164; 31:XA3XQCAWoFwnFqQHXsE04SMm/EgpB8s1mZogXvS0KQa2CptjkHmSZ0x3KaHXu8cbyBReIP0d8Bg0XzYinLJSJbhEYhKY290fjT2aU/hm4ry1GVSwImDeYte7GyZ8TYatuZhDYNLad5cjvVCqVCfWAdhYdTbqQZEfkk5LzwKVn0nB6IpfoWkYwuIgW0N/FeMNTYOcsompTdRZlRTDRSlPzL1szJ4SLMkPvXZgJSEXewfckzHjMXI+QkiUteYBifxUiWJ3IaQ1EgNF/h2/GzFTxg== X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:(185117386973197); X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(6095135)(601004)(2401047)(13018025)(13023025)(13024025)(8121501046)(5005006)(13015025)(13017025)(10201501046)(3002001)(93006095)(93001095)(6055026)(6096035)(20161123565025)(201703131430075)(201703131433075)(201703131441075)(201703131448075)(201703161259150)(20161123559100)(20161123556025)(20161123561025)(20161123563025); SRVR:BL2PR03MB164; BCL:0; PCL:0; RULEID:(400006); SRVR:BL2PR03MB164; X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; BL2PR03MB164; 4:XEe/GdG+cmqN6H9c0I5Pc2aWTS8NwG4K/PFrjmG5KjR?= =?us-ascii?Q?jNMrfSx53QrdhH14Xdk+SeHYy0CsK1FPwmqPqhZhlskkaNeYge+cV9PjlFZo?= =?us-ascii?Q?rQsU0CWgZmK8tqtVO0izAfni/CbTMq9v1HoZFn0mKNTpSmWiht8+P05lXGpQ?= =?us-ascii?Q?b2KZSVVcFZGbeoRtCdgPLlEP3yMFGat9eL1wi84UOl5MRg0AHNrHH+Da8/+L?= =?us-ascii?Q?rlzyPw8zaPNiyMMOOccuQ98TSLG443WucmwMJbvK8s2XY6Y095Ssx9Cy52rJ?= =?us-ascii?Q?N/aPJyLgYfevQrFk3QhydG6mcVbphtqze6jd82rXaiymCURyLzBc1ka6q2oT?= =?us-ascii?Q?Tpar+YXN6SbutMNy33zYZl273fjazBxxeGZz/du24CbKi4X6Q5mDV+HmUODq?= =?us-ascii?Q?GOA+Pr4KvgkcseGK+zqkY5RuyK7U7VTstnyl1M7AY2csNhLwMb8x4ynzjA3p?= =?us-ascii?Q?GtFjBR4BZrc5leY8zsyJYU0I6Cns9u1G/3CGW77wSaWl/LkoXh2vyA6h3VZj?= =?us-ascii?Q?uAaJBKKSJsPDNraM37sKdQMWnbw2r978FOYzxk84YpuPiCGD5WeAOMXnDWRp?= =?us-ascii?Q?wkuiwgCHYFJtzcblAA3sRspWrODdd/2bXwLwLcQwq2Teg9Kf1OyQjvzkGf82?= =?us-ascii?Q?7b6A1iiiX7qmv12cbgcpUJ0h0q7n1fUGKdXZAPHh0/DvKR1IwtB+Ms6+SspU?= =?us-ascii?Q?JMRV4WkW0Gxvl8MpUba1ipEDNyCP02sdYbge9JntMPQp/Bk2nTMv6es7EzrP?= =?us-ascii?Q?7IacOwonciMaVLSy2oL5QO3aBG17v+LPEBGr39pD9otQd9she6WCd8qldGO/?= =?us-ascii?Q?TLW+bOFarFvGv8pgEMUS0v1X+aT6+7UgPGQXnAzovVJXPCRCxtA8l7Y5kvuL?= =?us-ascii?Q?GMEKm1pknJ7+UGdiLUF5vhJPWMmDiIOH8fujUvYej2HnbM5XqWqptRGqgLrp?= =?us-ascii?Q?GgMmcN+WkwvJm5bRjORQRLwAZAt976qmiF1gSIA=3D=3D?= X-Forefront-PRVS: 0318501FAE X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; BL2PR03MB164; 23:idE3Pdy9FfxaLTegen9dYyXWpJVMVw4uAqsZu/Nr3y?= =?us-ascii?Q?Yr2+rfOzi2bHCu62qHTXApub2PQFclLDLPjezz43HFTJhZ8Iu7MsRGHubRbj?= =?us-ascii?Q?IQRf4wwK2vV3IgZuehqGPr3ulQkFzV3KDa/5lYbfPDspEn3S84Ev4NZN+UOQ?= =?us-ascii?Q?m6NfHJFHsqeDQUXeVB/nFkFNmIC3T1eLkSiNZxNpyJR79EqFgtyr/+fzF757?= =?us-ascii?Q?LIkQuXiHZonkfAq0WalsGCyRcLScmJC3L9jy4MvInKchl3lGqaKKIoViQI7p?= =?us-ascii?Q?vmmaoGYNkqLuhEILGcG752ue6YCQvKdIkNzNwGiVfgEwAqAYZdoez/1+xsez?= =?us-ascii?Q?MakCRfi1IdCkz7q1ROKkHGQUmLE8UxjyCLVIP2bT/BobGROGWWCaJrTpdDC5?= =?us-ascii?Q?j6EGhOdXJTobeSoplCCZJhGJRYDwlWiwtuC56eKQlOzaMxLfAhmwgLPH7ESZ?= =?us-ascii?Q?UhvnT94fSRM0rpaZspFjKW3XZa/YSX7VprVEIcrfnQR20cYoBVtB+hY9Q7QC?= =?us-ascii?Q?7lLIWI/sCUcFSq3Lx5ci43UQ/g/OxPAX2k/hTYYXrox2fWho3jsbzalvHWy1?= =?us-ascii?Q?IWDF7AvArqJ+KbUEMiL2GNS9CC70L3CNvxiagcRTwJGjRplbUHR0EH2Kh/rC?= =?us-ascii?Q?o+jZFRu5cxBoyDe1oYG40JeQRKg8ViyzFycbv+BFHADMZR6dOqcMlxdgCH9/?= =?us-ascii?Q?/t9rGEBnJX0aApMzJvmvsEmnIoMmucleW+5+hqx51H3rzvrXWk4uFID9VVBo?= =?us-ascii?Q?60U7fh23zjEYCLYVcteacVtZImCDQoCSPS4pjoMbn9w+XgO+Io1Xr5OtYJ/s?= =?us-ascii?Q?+GKcYP6SQIDuS4QLnLUywpigg9ofXPtIweUiansbEEQ//rM8QzI9K3las8cH?= =?us-ascii?Q?6JBfDheE6H3yragP91RTGU/cx3x8CLQfFVe8i+bbEfz0tfKNrfwXEPA2MC7z?= =?us-ascii?Q?SX1VmM+RSAiBj9jgiulimf68rwayhG38CuvJACn+F+g0ltyt2IxEqYeU1OX/?= =?us-ascii?Q?F/CfTk4zwBByFxFd8FCbU5AfdJCZ/h6Zo3FmXm7hQ1sUfzL65BaOjdqv0oyB?= =?us-ascii?Q?/Wl/0VXfmcAa0/M+BE/rMH3fGh9/7XAJHX6wLe/GjWEO1anFvkfrYmWV/RJF?= =?us-ascii?Q?kpH0pLe9OCOfSd1ZllEDUiR9f5lyk9z8iyXeGzE/6mWNuzStCGZPwvGvhIcU?= =?us-ascii?Q?MMeZyuhY6C9lknZ4TWGEmrTWbGjAZENawX0scY7mkwy4l38rbz7kij+yZOl3?= =?us-ascii?Q?3kcdL8F5+4Cgrcg4I=3D?= X-Microsoft-Exchange-Diagnostics: 1; BL2PR03MB164; 6:7qdWIMudbK/CWl8lKbezwTYaybnOxfDIfHFcAKJaItckUxYJaYszZ6U6JegE74nw+58X5y131daY+C/9sSJo+GwcuYRUE0Y/bTK6uhCm4WLVPO6nnJES7wu6mr1UrhzrC1nV22mdfxNN1eAjuh4gfzXkRlJeINKplVuXrabThMxlCU2ZK4d6qc/RCmeOGHdrUBdPo1WHxBfgzosPhQdABEEi7Qsbb+LJqZTGzom8E8DwoHIuaA1pzm+xCkJ/phedGvyUegarYEzDutrEcQejha7IQChfWOAieG2Is+Dol0DgoATiewlOWH4P0H9Fu0LrTaZHq/QsH4uOGA2XhsuZW7v3vne5QFP1htUnnr3K4r1QQbLJYz41I0hZ5OTVncfwwFtNGm+652SPJvR5o86gYfz08aBtEQdl+uyjTAOW5tEuWYwXUoUz6oiCkB9hM3SBtLpFLXhosV+N7iTKwyZq4YgC5V1yHWRWnqrV9cD1NbCJYSIyHFTWa3tv0srIv5tVbfvioZUie8ogzzZ7eLHMFw==; 5:r8Datw4c1WiEx3vC60k6BHZl9FdDOR+GSP0Udz2uOOy8CR8dj1TemB0iJME0ObIHpEVh48NK06kc2bIVN5U61WTiDTaoDpEWteUL3IURrJ6SsdQG9rb7xQKb7hb2s2ZdQYMQs5TU9rptZHqdL81hTFZdw2K1ruA5bzVE5mfiJYzyVkiKiXn+sB5PmF+puHlQ; 24:J4GqD8SoOs5UN+otqNohHgyAnFouamP4LOABn8Qbgjy26LOEkHbp5EZJRcFLiBSL5CFa0KQeByP7tKO6TFIzUYcSS7sirY2xTCwjVxIS/m4= SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-Microsoft-Exchange-Diagnostics: 1; BL2PR03MB164; 7:U2U7iA6K/Ttn4sQi1spgH3u8x8zDsCMMOwIV1gH0euSZ03FO1qLrQQl6jcA66dpWgwgxTcgiN8tfP3/MKPyVocmwVgiDshoF62W8eb/xRX/VHH8WCMnTMUG7LiV0GnFsrImDbIxHflBS6y0arvvoyh33u4S6eymgfZwP2gJhmok8lxJ3h11Adet2mXTCtwwS0UHsIhMMFJj/Nt3VVxdB1ECZyHg02yAhSGcRy8KKjKqbU+HwmJgEDVufaoWfoshbrmPhLGvO3SJ+1RSARshWzjjiA4Ca+/McJwZGOG0o6ugN5m+0aWD4P47q4ngBXW//va8HTaHidKf3Vo0W5belWw== X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 May 2017 18:09:43.6688 (UTC) X-MS-Exchange-CrossTenant-Id: 5afe0b00-7697-4969-b663-5eab37d5f47e X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=5afe0b00-7697-4969-b663-5eab37d5f47e; Ip=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL2PR03MB164 Subject: [dpdk-dev] [PATCH 12/20] event/dpaa2: add configuration functions X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 25 May 2017 18:09:47 -0000 This patch adds all the configuration API's for DPAA2 eventdev including device config, start, stop & port and queue related API's Signed-off-by: Nipun Gupta --- drivers/event/dpaa2/dpaa2_eventdev.c | 283 ++++++++++++++++++++++++++++++++++- drivers/event/dpaa2/dpaa2_eventdev.h | 22 +++ 2 files changed, 304 insertions(+), 1 deletion(-) diff --git a/drivers/event/dpaa2/dpaa2_eventdev.c b/drivers/event/dpaa2/dpaa2_eventdev.c index 7fa17f2..cfb52bb 100644 --- a/drivers/event/dpaa2/dpaa2_eventdev.c +++ b/drivers/event/dpaa2/dpaa2_eventdev.c @@ -106,7 +106,288 @@ return dpaa2_eventdev_dequeue_burst(port, ev, 1, timeout_ticks); } -static const struct rte_eventdev_ops dpaa2_eventdev_ops; +static void +dpaa2_eventdev_info_get(struct rte_eventdev *dev, + struct rte_event_dev_info *dev_info) +{ + struct dpaa2_eventdev *priv = dev->data->dev_private; + + PMD_DRV_FUNC_TRACE(); + + RTE_SET_USED(dev); + + memset(dev_info, 0, sizeof(struct rte_event_dev_info)); + dev_info->min_dequeue_timeout_ns = + DPAA2_EVENT_MIN_DEQUEUE_TIMEOUT; + dev_info->max_dequeue_timeout_ns = + DPAA2_EVENT_MAX_DEQUEUE_TIMEOUT; + dev_info->dequeue_timeout_ns = + DPAA2_EVENT_MIN_DEQUEUE_TIMEOUT; + dev_info->max_event_queues = priv->max_event_queues; + dev_info->max_event_queue_flows = + DPAA2_EVENT_MAX_QUEUE_FLOWS; + dev_info->max_event_queue_priority_levels = + DPAA2_EVENT_MAX_QUEUE_PRIORITY_LEVELS; + dev_info->max_event_priority_levels = + DPAA2_EVENT_MAX_EVENT_PRIORITY_LEVELS; + dev_info->max_event_ports = RTE_MAX_LCORE; + dev_info->max_event_port_dequeue_depth = + DPAA2_EVENT_MAX_PORT_DEQUEUE_DEPTH; + dev_info->max_event_port_enqueue_depth = + DPAA2_EVENT_MAX_PORT_ENQUEUE_DEPTH; + dev_info->max_num_events = DPAA2_EVENT_MAX_NUM_EVENTS; + dev_info->event_dev_cap = RTE_EVENT_DEV_CAP_DISTRIBUTED_SCHED; +} + +static int +dpaa2_eventdev_configure(const struct rte_eventdev *dev) +{ + struct dpaa2_eventdev *priv = dev->data->dev_private; + struct rte_event_dev_config *conf = &dev->data->dev_conf; + + PMD_DRV_FUNC_TRACE(); + + priv->dequeue_timeout_ns = conf->dequeue_timeout_ns; + priv->nb_event_queues = conf->nb_event_queues; + priv->nb_event_ports = conf->nb_event_ports; + priv->nb_event_queue_flows = conf->nb_event_queue_flows; + priv->nb_event_port_dequeue_depth = conf->nb_event_port_dequeue_depth; + priv->nb_event_port_enqueue_depth = conf->nb_event_port_enqueue_depth; + priv->event_dev_cfg = conf->event_dev_cfg; + + PMD_DRV_LOG(DEBUG, "Configured eventdev devid=%d", dev->data->dev_id); + return 0; +} + +static int +dpaa2_eventdev_start(struct rte_eventdev *dev) +{ + PMD_DRV_FUNC_TRACE(); + + RTE_SET_USED(dev); + + return 0; +} + +static void +dpaa2_eventdev_stop(struct rte_eventdev *dev) +{ + PMD_DRV_FUNC_TRACE(); + + RTE_SET_USED(dev); +} + +static int +dpaa2_eventdev_close(struct rte_eventdev *dev) +{ + PMD_DRV_FUNC_TRACE(); + + RTE_SET_USED(dev); + + return 0; +} + +static void +dpaa2_eventdev_queue_def_conf(struct rte_eventdev *dev, uint8_t queue_id, + struct rte_event_queue_conf *queue_conf) +{ + PMD_DRV_FUNC_TRACE(); + + RTE_SET_USED(dev); + RTE_SET_USED(queue_id); + RTE_SET_USED(queue_conf); + + queue_conf->nb_atomic_flows = DPAA2_EVENT_QUEUE_ATOMIC_FLOWS; + queue_conf->nb_atomic_order_sequences = DPAA2_EVENT_QUEUE_ATOMIC_FLOWS; + queue_conf->event_queue_cfg = RTE_EVENT_QUEUE_CFG_ALL_TYPES; + queue_conf->priority = RTE_EVENT_DEV_PRIORITY_NORMAL; +} + +static void +dpaa2_eventdev_queue_release(struct rte_eventdev *dev, uint8_t queue_id) +{ + PMD_DRV_FUNC_TRACE(); + + RTE_SET_USED(dev); + RTE_SET_USED(queue_id); +} + +static int +dpaa2_eventdev_queue_setup(struct rte_eventdev *dev, uint8_t queue_id, + const struct rte_event_queue_conf *queue_conf) +{ + struct dpaa2_eventdev *priv = dev->data->dev_private; + struct evq_info_t *evq_info = + &priv->evq_info[queue_id]; + + PMD_DRV_FUNC_TRACE(); + + evq_info->event_queue_cfg = queue_conf->event_queue_cfg; + + return 0; +} + +static void +dpaa2_eventdev_port_def_conf(struct rte_eventdev *dev, uint8_t port_id, + struct rte_event_port_conf *port_conf) +{ + PMD_DRV_FUNC_TRACE(); + + RTE_SET_USED(dev); + RTE_SET_USED(port_id); + RTE_SET_USED(port_conf); + + port_conf->new_event_threshold = + DPAA2_EVENT_MAX_NUM_EVENTS; + port_conf->dequeue_depth = + DPAA2_EVENT_MAX_PORT_DEQUEUE_DEPTH; + port_conf->enqueue_depth = + DPAA2_EVENT_MAX_PORT_ENQUEUE_DEPTH; +} + +static void +dpaa2_eventdev_port_release(void *port) +{ + PMD_DRV_FUNC_TRACE(); + + RTE_SET_USED(port); +} + +static int +dpaa2_eventdev_port_setup(struct rte_eventdev *dev, uint8_t port_id, + const struct rte_event_port_conf *port_conf) +{ + PMD_DRV_FUNC_TRACE(); + + RTE_SET_USED(port_conf); + + if (!dpaa2_io_portal[port_id].dpio_dev) { + dpaa2_io_portal[port_id].dpio_dev = + dpaa2_get_qbman_swp(port_id); + rte_atomic16_inc(&dpaa2_io_portal[port_id].dpio_dev->ref_count); + if (!dpaa2_io_portal[port_id].dpio_dev) + return -1; + } + + dpaa2_io_portal[port_id].eventdev = dev; + dev->data->ports[port_id] = &dpaa2_io_portal[port_id]; + return 0; +} + +static int +dpaa2_eventdev_port_unlink(struct rte_eventdev *dev, void *port, + uint8_t queues[], uint16_t nb_unlinks) +{ + struct dpaa2_eventdev *priv = dev->data->dev_private; + struct dpaa2_io_portal_t *dpaa2_portal = port; + struct evq_info_t *evq_info; + int i; + + PMD_DRV_FUNC_TRACE(); + + for (i = 0; i < nb_unlinks; i++) { + evq_info = &priv->evq_info[queues[i]]; + qbman_swp_push_set(dpaa2_portal->dpio_dev->sw_portal, + evq_info->dpcon->channel_index, 0); + dpio_remove_static_dequeue_channel(dpaa2_portal->dpio_dev->dpio, + 0, dpaa2_portal->dpio_dev->token, + evq_info->dpcon->dpcon_id); + evq_info->link = 0; + } + + return (int)nb_unlinks; +} + +static int +dpaa2_eventdev_port_link(struct rte_eventdev *dev, void *port, + const uint8_t queues[], const uint8_t priorities[], + uint16_t nb_links) +{ + struct dpaa2_eventdev *priv = dev->data->dev_private; + struct dpaa2_io_portal_t *dpaa2_portal = port; + struct evq_info_t *evq_info; + uint8_t channel_index; + int ret, i, n; + + PMD_DRV_FUNC_TRACE(); + + for (i = 0; i < nb_links; i++) { + evq_info = &priv->evq_info[queues[i]]; + if (evq_info->link) + continue; + + ret = dpio_add_static_dequeue_channel( + dpaa2_portal->dpio_dev->dpio, + CMD_PRI_LOW, dpaa2_portal->dpio_dev->token, + evq_info->dpcon->dpcon_id, &channel_index); + if (ret < 0) { + PMD_DRV_ERR("Static dequeue cfg failed with ret: %d\n", + ret); + goto err; + } + + qbman_swp_push_set(dpaa2_portal->dpio_dev->sw_portal, + channel_index, 1); + evq_info->dpcon->channel_index = channel_index; + evq_info->link = 1; + } + + RTE_SET_USED(priorities); + + return (int)nb_links; +err: + for (n = 0; n < i; n++) { + evq_info = &priv->evq_info[queues[n]]; + qbman_swp_push_set(dpaa2_portal->dpio_dev->sw_portal, + evq_info->dpcon->channel_index, 0); + dpio_remove_static_dequeue_channel(dpaa2_portal->dpio_dev->dpio, + 0, dpaa2_portal->dpio_dev->token, + evq_info->dpcon->dpcon_id); + evq_info->link = 0; + } + return ret; +} + +static int +dpaa2_eventdev_timeout_ticks(struct rte_eventdev *dev, uint64_t ns, + uint64_t *timeout_ticks) +{ + uint32_t scale = 1; + + PMD_DRV_FUNC_TRACE(); + + RTE_SET_USED(dev); + *timeout_ticks = ns * scale; + + return 0; +} + +static void +dpaa2_eventdev_dump(struct rte_eventdev *dev, FILE *f) +{ + PMD_DRV_FUNC_TRACE(); + + RTE_SET_USED(dev); + RTE_SET_USED(f); +} + +static const struct rte_eventdev_ops dpaa2_eventdev_ops = { + .dev_infos_get = dpaa2_eventdev_info_get, + .dev_configure = dpaa2_eventdev_configure, + .dev_start = dpaa2_eventdev_start, + .dev_stop = dpaa2_eventdev_stop, + .dev_close = dpaa2_eventdev_close, + .queue_def_conf = dpaa2_eventdev_queue_def_conf, + .queue_setup = dpaa2_eventdev_queue_setup, + .queue_release = dpaa2_eventdev_queue_release, + .port_def_conf = dpaa2_eventdev_port_def_conf, + .port_setup = dpaa2_eventdev_port_setup, + .port_release = dpaa2_eventdev_port_release, + .port_link = dpaa2_eventdev_port_link, + .port_unlink = dpaa2_eventdev_port_unlink, + .timeout_ticks = dpaa2_eventdev_timeout_ticks, + .dump = dpaa2_eventdev_dump +}; static int dpaa2_eventdev_setup_dpci(struct dpaa2_dpci_dev *dpci_dev, diff --git a/drivers/event/dpaa2/dpaa2_eventdev.h b/drivers/event/dpaa2/dpaa2_eventdev.h index 01de73c..4027852 100644 --- a/drivers/event/dpaa2/dpaa2_eventdev.h +++ b/drivers/event/dpaa2/dpaa2_eventdev.h @@ -55,6 +55,17 @@ #define DPAA2_EVENT_DEFAULT_DPCI_PRIO 0 #define DPAA2_EVENT_MAX_QUEUES 16 +#define DPAA2_EVENT_MIN_DEQUEUE_TIMEOUT 1 +#define DPAA2_EVENT_MAX_DEQUEUE_TIMEOUT (UINT32_MAX - 1) +#define DPAA2_EVENT_MAX_QUEUE_FLOWS 2048 +#define DPAA2_EVENT_MAX_QUEUE_PRIORITY_LEVELS 8 +#define DPAA2_EVENT_MAX_EVENT_PRIORITY_LEVELS 0 +#define DPAA2_EVENT_MAX_PORT_DEQUEUE_DEPTH 8 +#define DPAA2_EVENT_MAX_PORT_ENQUEUE_DEPTH 8 +#define DPAA2_EVENT_MAX_NUM_EVENTS (INT32_MAX - 1) + +#define DPAA2_EVENT_QUEUE_ATOMIC_FLOWS 2048 +#define DPAA2_EVENT_QUEUE_ORDER_SEQUENCES 2048 enum { DPAA2_EVENT_DPCI_PARALLEL_QUEUE, @@ -78,11 +89,22 @@ struct evq_info_t { struct dpaa2_dpcon_dev *dpcon; /* Attached DPCI device */ struct dpaa2_dpci_dev *dpci; + /* Configuration provided by the user */ + uint32_t event_queue_cfg; + uint8_t link; }; struct dpaa2_eventdev { struct evq_info_t evq_info[DPAA2_EVENT_MAX_QUEUES]; + uint32_t dequeue_timeout_ns; uint8_t max_event_queues; + uint8_t nb_event_queues; + uint8_t nb_event_ports; + uint8_t resvd_1; + uint32_t nb_event_queue_flows; + uint32_t nb_event_port_dequeue_depth; + uint32_t nb_event_port_enqueue_depth; + uint32_t event_dev_cfg; }; struct dpaa2_dpcon_dev *rte_dpaa2_alloc_dpcon_dev(void); -- 1.9.1