From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by dpdk.org (Postfix) with ESMTP id 9617456A1 for ; Tue, 27 Jun 2017 15:34:54 +0200 (CEST) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 27 Jun 2017 06:34:54 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.39,399,1493708400"; d="scan'208";a="1145255233" Received: from dpdk2.sh.intel.com ([10.239.128.238]) by orsmga001.jf.intel.com with ESMTP; 27 Jun 2017 06:34:53 -0700 From: Jingjing Wu To: dev@dpdk.org Cc: jingjing.wu@intel.com, helin.zhang@intel.com Date: Tue, 27 Jun 2017 21:29:14 +0800 Message-Id: <1498570158-57201-14-git-send-email-jingjing.wu@intel.com> X-Mailer: git-send-email 2.4.11 In-Reply-To: <1498570158-57201-1-git-send-email-jingjing.wu@intel.com> References: <1498470539-26921-1-git-send-email-jingjing.wu@intel.com> <1498570158-57201-1-git-send-email-jingjing.wu@intel.com> Subject: [dpdk-dev] [PATCH v3 13/17] net/i40e/base: avoid reset timeout issue X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 27 Jun 2017 13:34:55 -0000 This patch allows detection of upcoming core reset in case NIC gets stuck while performing FLR reset. The i40e_pf_reset() function returns I40E_ERR_NOT_READY when global reset was detected. Signed-off-by: Jingjing Wu --- drivers/net/i40e/base/i40e_common.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/net/i40e/base/i40e_common.c b/drivers/net/i40e/base/i40e_common.c index 78ed2a8..ed2e01a 100644 --- a/drivers/net/i40e/base/i40e_common.c +++ b/drivers/net/i40e/base/i40e_common.c @@ -1382,6 +1382,8 @@ enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw) * we don't need to do the PF Reset */ if (!cnt) { + u32 reg2 = 0; + reg = rd32(hw, I40E_PFGEN_CTRL); wr32(hw, I40E_PFGEN_CTRL, (reg | I40E_PFGEN_CTRL_PFSWR_MASK)); @@ -1389,6 +1391,12 @@ enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw) reg = rd32(hw, I40E_PFGEN_CTRL); if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK)) break; + reg2 = rd32(hw, I40E_GLGEN_RSTAT); + if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) { + DEBUGOUT("Core reset upcoming.\n"); + DEBUGOUT1("I40E_GLGEN_RSTAT = 0x%x\n", reg2); + return I40E_ERR_NOT_READY; + } i40e_msec_delay(1); } if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) { -- 2.4.11