From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by dpdk.org (Postfix) with ESMTP id CF276378E for ; Tue, 27 Jun 2017 16:06:45 +0200 (CEST) Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 27 Jun 2017 07:06:30 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.39,399,1493708400"; d="scan'208";a="119771542" Received: from dpdk2.sh.intel.com ([10.239.128.238]) by fmsmga006.fm.intel.com with ESMTP; 27 Jun 2017 07:06:29 -0700 From: Jingjing Wu To: dev@dpdk.org Cc: jingjing.wu@intel.com, helin.zhang@intel.com Date: Tue, 27 Jun 2017 22:00:53 +0800 Message-Id: <1498572056-72971-15-git-send-email-jingjing.wu@intel.com> X-Mailer: git-send-email 2.4.11 In-Reply-To: <1498572056-72971-1-git-send-email-jingjing.wu@intel.com> References: <1498570158-57201-1-git-send-email-jingjing.wu@intel.com> <1498572056-72971-1-git-send-email-jingjing.wu@intel.com> Subject: [dpdk-dev] [PATCH v4 14/17] net/i40e/base: add EEPROM checksum verification X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 27 Jun 2017 14:06:46 -0000 This patch ensures PFs mutually exclusive access to NVM. Signed-off-by: Jingjing Wu --- drivers/net/i40e/base/i40e_nvm.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/net/i40e/base/i40e_nvm.c b/drivers/net/i40e/base/i40e_nvm.c index 90521fa..a1e7830 100644 --- a/drivers/net/i40e/base/i40e_nvm.c +++ b/drivers/net/i40e/base/i40e_nvm.c @@ -749,12 +749,18 @@ enum i40e_status_code i40e_validate_nvm_checksum(struct i40e_hw *hw, DEBUGFUNC("i40e_validate_nvm_checksum"); - if (hw->flags & I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE) - ret_code = i40e_acquire_nvm(hw, I40E_RESOURCE_READ); + /* acquire_nvm provides exclusive NVM lock to synchronize access across + * PFs. X710 uses i40e_read_nvm_word_srctl which polls for done bit + * twice (first time to be able to write address to I40E_GLNVM_SRCTL + * register, second to read data from I40E_GLNVM_SRDATA. One PF can see + * done bit and try to write address, while another one will interpret + * it as a good time to read data. It will cause invalid data to be + * read. + */ + ret_code = i40e_acquire_nvm(hw, I40E_RESOURCE_READ); if (!ret_code) { ret_code = i40e_calc_nvm_checksum(hw, &checksum_local); - if (hw->flags & I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE) - i40e_release_nvm(hw); + i40e_release_nvm(hw); if (ret_code != I40E_SUCCESS) goto i40e_validate_nvm_checksum_exit; } else { -- 2.4.11