* [dpdk-dev] [PATCH 1/5] app/testpmd: add new commands to manipulate with pctype mapping
2017-08-24 10:20 [dpdk-dev] [PATCH 0/5] net/i40e: implement dynamic mapping of flow types to pctypes Kirill Rybalchenko
@ 2017-08-24 10:20 ` Kirill Rybalchenko
2017-08-24 10:20 ` [dpdk-dev] [PATCH 2/5] net/i40e: add function to initialize pctype mapping table Kirill Rybalchenko
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Kirill Rybalchenko @ 2017-08-24 10:20 UTC (permalink / raw)
To: dev; +Cc: kirill.rybalchenko, andrey.chilikin, beilei.xing
Add new commands to manipulate with dynamic flow type to
pctype mapping table in i40e PMD.
Commands allow to print table, modify it and reset to default value.
Signed-off-by: Kirill Rybalchenko <kirill.rybalchenko@intel.com>
---
app/test-pmd/cmdline.c | 263 +++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 263 insertions(+)
diff --git a/app/test-pmd/cmdline.c b/app/test-pmd/cmdline.c
index cd8c358..6bf3a9d 100644
--- a/app/test-pmd/cmdline.c
+++ b/app/test-pmd/cmdline.c
@@ -13795,6 +13795,265 @@ cmdline_parse_inst_t cmd_clear_vf_stats = {
},
};
+/* pctype mapping reset */
+
+/* Common result structure for pctype mapping reset */
+struct cmd_pctype_mapping_reset_result {
+ cmdline_fixed_string_t pctype;
+ cmdline_fixed_string_t mapping;
+ cmdline_fixed_string_t reset;
+ uint8_t port_id;
+};
+
+/* Common CLI fields for ptype mapping reset*/
+cmdline_parse_token_string_t cmd_pctype_mapping_reset_pctype =
+ TOKEN_STRING_INITIALIZER
+ (struct cmd_pctype_mapping_reset_result,
+ pctype, "pctype");
+cmdline_parse_token_string_t cmd_pctype_mapping_reset_mapping =
+ TOKEN_STRING_INITIALIZER
+ (struct cmd_pctype_mapping_reset_result,
+ mapping, "mapping");
+cmdline_parse_token_string_t cmd_pctype_mapping_reset_reset =
+ TOKEN_STRING_INITIALIZER
+ (struct cmd_pctype_mapping_reset_result,
+ reset, "reset");
+cmdline_parse_token_num_t cmd_pctype_mapping_reset_port_id =
+ TOKEN_NUM_INITIALIZER
+ (struct cmd_pctype_mapping_reset_result,
+ port_id, UINT8);
+
+static void
+cmd_pctype_mapping_reset_parsed(
+ void *parsed_result,
+ __attribute__((unused)) struct cmdline *cl,
+ __attribute__((unused)) void *data)
+{
+ struct cmd_pctype_mapping_reset_result *res = parsed_result;
+ int ret = -ENOTSUP;
+
+ if (port_id_is_invalid(res->port_id, ENABLED_WARN))
+ return;
+
+#ifdef RTE_LIBRTE_I40E_PMD
+ ret = rte_pmd_i40e_flow_type_mapping_reset(res->port_id);
+#endif
+
+ switch (ret) {
+ case 0:
+ break;
+ case -ENODEV:
+ printf("invalid port_id %d\n", res->port_id);
+ break;
+ case -ENOTSUP:
+ printf("function not implemented\n");
+ break;
+ default:
+ printf("programming error: (%s)\n", strerror(-ret));
+ }
+}
+
+cmdline_parse_inst_t cmd_pctype_mapping_reset = {
+ .f = cmd_pctype_mapping_reset_parsed,
+ .data = NULL,
+ .help_str = "pctype mapping reset <port_id>",
+ .tokens = {
+ (void *)&cmd_pctype_mapping_reset_pctype,
+ (void *)&cmd_pctype_mapping_reset_mapping,
+ (void *)&cmd_pctype_mapping_reset_reset,
+ (void *)&cmd_pctype_mapping_reset_port_id,
+ NULL,
+ },
+};
+
+/* pctype mapping get */
+
+/* Common result structure for ptype mapping get */
+struct cmd_pctype_mapping_get_result {
+ cmdline_fixed_string_t pctype;
+ cmdline_fixed_string_t mapping;
+ cmdline_fixed_string_t get;
+ uint8_t port_id;
+ uint8_t valid_only;
+};
+
+/* Common CLI fields for ptype mapping get */
+cmdline_parse_token_string_t cmd_pctype_mapping_get_pctype =
+ TOKEN_STRING_INITIALIZER
+ (struct cmd_pctype_mapping_get_result,
+ pctype, "pctype");
+cmdline_parse_token_string_t cmd_pctype_mapping_get_mapping =
+ TOKEN_STRING_INITIALIZER
+ (struct cmd_pctype_mapping_get_result,
+ mapping, "mapping");
+cmdline_parse_token_string_t cmd_pctype_mapping_get_get =
+ TOKEN_STRING_INITIALIZER
+ (struct cmd_pctype_mapping_get_result,
+ get, "get");
+cmdline_parse_token_num_t cmd_pctype_mapping_get_port_id =
+ TOKEN_NUM_INITIALIZER
+ (struct cmd_pctype_mapping_get_result,
+ port_id, UINT8);
+cmdline_parse_token_num_t cmd_pctype_mapping_get_valid_only =
+ TOKEN_NUM_INITIALIZER
+ (struct cmd_pctype_mapping_get_result,
+ valid_only, UINT8);
+
+static void
+cmd_pctype_mapping_get_parsed(
+ void *parsed_result,
+ __attribute__((unused)) struct cmdline *cl,
+ __attribute__((unused)) void *data)
+{
+ struct cmd_pctype_mapping_get_result *res = parsed_result;
+ int ret = -ENOTSUP;
+#ifdef RTE_LIBRTE_I40E_PMD
+ int max_ptype_num = 64;
+ struct rte_pmd_i40e_flow_type_mapping mapping[max_ptype_num];
+ uint16_t count;
+ int i;
+#endif
+
+ if (port_id_is_invalid(res->port_id, ENABLED_WARN))
+ return;
+
+#ifdef RTE_LIBRTE_I40E_PMD
+ ret = rte_pmd_i40e_flow_type_mapping_get(res->port_id,
+ mapping,
+ max_ptype_num,
+ &count,
+ res->valid_only);
+#endif
+
+ switch (ret) {
+ case 0:
+ break;
+ case -ENODEV:
+ printf("invalid port_id %d\n", res->port_id);
+ break;
+ case -ENOTSUP:
+ printf("function not implemented\n");
+ break;
+ default:
+ printf("programming error: (%s)\n", strerror(-ret));
+ }
+
+#ifdef RTE_LIBRTE_I40E_PMD
+ if (!ret) {
+ for (i = 0; i < count; i++)
+ printf("%02d\t0x%016"PRIx64"\n",
+ mapping[i].flow_type, mapping[i].pctype);
+ }
+#endif
+}
+
+cmdline_parse_inst_t cmd_pctype_mapping_get = {
+ .f = cmd_pctype_mapping_get_parsed,
+ .data = NULL,
+ .help_str = "pctype mapping get <port_id> <valid_only>",
+ .tokens = {
+ (void *)&cmd_pctype_mapping_get_pctype,
+ (void *)&cmd_pctype_mapping_get_mapping,
+ (void *)&cmd_pctype_mapping_get_get,
+ (void *)&cmd_pctype_mapping_get_port_id,
+ (void *)&cmd_pctype_mapping_get_valid_only,
+ NULL,
+ },
+};
+
+/* pctype mapping update */
+
+/* Common result structure for pctype mapping update */
+struct cmd_pctype_mapping_update_result {
+ cmdline_fixed_string_t pctype;
+ cmdline_fixed_string_t mapping;
+ cmdline_fixed_string_t update;
+ uint8_t port_id;
+ uint16_t flow_type;
+ uint64_t pc_type;
+};
+
+/* Common CLI fields for ptype mapping update*/
+cmdline_parse_token_string_t cmd_pctype_mapping_update_pctype =
+ TOKEN_STRING_INITIALIZER
+ (struct cmd_pctype_mapping_update_result,
+ pctype, "pctype");
+cmdline_parse_token_string_t cmd_pctype_mapping_update_mapping =
+ TOKEN_STRING_INITIALIZER
+ (struct cmd_pctype_mapping_update_result,
+ mapping, "mapping");
+cmdline_parse_token_string_t cmd_pctype_mapping_update_update =
+ TOKEN_STRING_INITIALIZER
+ (struct cmd_pctype_mapping_update_result,
+ update, "update");
+cmdline_parse_token_num_t cmd_pctype_mapping_update_port_id =
+ TOKEN_NUM_INITIALIZER
+ (struct cmd_pctype_mapping_update_result,
+ port_id, UINT8);
+cmdline_parse_token_num_t cmd_pctype_mapping_update_flow_type =
+ TOKEN_NUM_INITIALIZER
+ (struct cmd_pctype_mapping_update_result,
+ flow_type, UINT16);
+cmdline_parse_token_num_t cmd_pctype_mapping_update_pc_type =
+ TOKEN_NUM_INITIALIZER
+ (struct cmd_pctype_mapping_update_result,
+ pc_type, UINT64);
+
+static void
+cmd_pctype_mapping_update_parsed(
+ void *parsed_result,
+ __attribute__((unused)) struct cmdline *cl,
+ __attribute__((unused)) void *data)
+{
+ struct cmd_pctype_mapping_update_result *res = parsed_result;
+ int ret = -ENOTSUP;
+#ifdef RTE_LIBRTE_I40E_PMD
+ struct rte_pmd_i40e_flow_type_mapping mapping;
+#endif
+ if (port_id_is_invalid(res->port_id, ENABLED_WARN))
+ return;
+
+#ifdef RTE_LIBRTE_I40E_PMD
+ mapping.flow_type = res->flow_type;
+ mapping.pctype = res->pc_type;
+ ret = rte_pmd_i40e_flow_type_mapping_update(res->port_id,
+ &mapping,
+ 1,
+ 0);
+#endif
+
+ switch (ret) {
+ case 0:
+ break;
+ case -EINVAL:
+ printf("invalid pctype 0x%016" PRIx64 "\n", res->pc_type);
+ break;
+ case -ENODEV:
+ printf("invalid port_id %d\n", res->port_id);
+ break;
+ case -ENOTSUP:
+ printf("function not implemented\n");
+ break;
+ default:
+ printf("programming error: (%s)\n", strerror(-ret));
+ }
+}
+
+cmdline_parse_inst_t cmd_pctype_mapping_update = {
+ .f = cmd_pctype_mapping_update_parsed,
+ .data = NULL,
+ .help_str = "pctype mapping update <port_id> <flow_ptype> <pctype>",
+ .tokens = {
+ (void *)&cmd_pctype_mapping_update_pctype,
+ (void *)&cmd_pctype_mapping_update_mapping,
+ (void *)&cmd_pctype_mapping_update_update,
+ (void *)&cmd_pctype_mapping_update_port_id,
+ (void *)&cmd_pctype_mapping_update_flow_type,
+ (void *)&cmd_pctype_mapping_update_pc_type,
+ NULL,
+ },
+};
+
/* ptype mapping get */
/* Common result structure for ptype mapping get */
@@ -14376,6 +14635,10 @@ cmdline_parse_ctx_t main_ctx[] = {
(cmdline_parse_inst_t *)&cmd_ptype_mapping_replace,
(cmdline_parse_inst_t *)&cmd_ptype_mapping_reset,
(cmdline_parse_inst_t *)&cmd_ptype_mapping_update,
+
+ (cmdline_parse_inst_t *)&cmd_pctype_mapping_get,
+ (cmdline_parse_inst_t *)&cmd_pctype_mapping_reset,
+ (cmdline_parse_inst_t *)&cmd_pctype_mapping_update,
NULL,
};
--
2.5.5
^ permalink raw reply [flat|nested] 6+ messages in thread* [dpdk-dev] [PATCH 5/5] net/i40e: implement dynamic mapping of sw flow types to hw pctypes
2017-08-24 10:20 [dpdk-dev] [PATCH 0/5] net/i40e: implement dynamic mapping of flow types to pctypes Kirill Rybalchenko
` (3 preceding siblings ...)
2017-08-24 10:20 ` [dpdk-dev] [PATCH 4/5] net/i40e: change list of parameters for functions mapping flow type to pctype and back Kirill Rybalchenko
@ 2017-08-24 10:20 ` Kirill Rybalchenko
4 siblings, 0 replies; 6+ messages in thread
From: Kirill Rybalchenko @ 2017-08-24 10:20 UTC (permalink / raw)
To: dev; +Cc: kirill.rybalchenko, andrey.chilikin, beilei.xing
Implement dynamic mapping of software flow types to hardware pctypes.
This allows to add new flow types and pctypes for DDP without changing
API of the driver. The mapping table is located in private
data area for particular network adapter and can be individually
modified with set of appropriate functions.
Signed-off-by: Kirill Rybalchenko <kirill.rybalchenko@intel.com>
---
drivers/net/i40e/i40e_ethdev.c | 313 +++++++++-----------------------------
drivers/net/i40e/i40e_ethdev.h | 16 +-
drivers/net/i40e/i40e_ethdev_vf.c | 36 ++---
3 files changed, 98 insertions(+), 267 deletions(-)
diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c
index 4a2e3f2..d80eca9 100644
--- a/drivers/net/i40e/i40e_ethdev.c
+++ b/drivers/net/i40e/i40e_ethdev.c
@@ -1062,6 +1062,7 @@ eth_i40e_dev_init(struct rte_eth_dev *dev)
return 0;
}
i40e_set_default_ptype_table(dev);
+ i40e_set_default_pctype_table(dev);
pci_dev = RTE_ETH_DEV_TO_PCI(dev);
intr_handle = &pci_dev->intr_handle;
@@ -2965,7 +2966,7 @@ i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
sizeof(uint32_t);
dev_info->reta_size = pf->hash_lut_size;
- dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
+ dev_info->flow_type_rss_offloads = pf->adapter->flow_types_msk;
dev_info->default_rxconf = (struct rte_eth_rxconf) {
.rx_thresh = {
@@ -6556,104 +6557,36 @@ i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
/* Configure hash enable flags for RSS */
uint64_t
-i40e_config_hena(uint64_t flags, enum i40e_mac_type type)
+i40e_config_hena(uint64_t flags, struct i40e_adapter *adapter)
{
uint64_t hena = 0;
+ int i;
if (!flags)
return hena;
- if (flags & ETH_RSS_FRAG_IPV4)
- hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
- if (flags & ETH_RSS_NONFRAG_IPV4_TCP) {
- if (type == I40E_MAC_X722) {
- hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
- (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
- } else
- hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
- }
- if (flags & ETH_RSS_NONFRAG_IPV4_UDP) {
- if (type == I40E_MAC_X722) {
- hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
- (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
- (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
- } else
- hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
- }
- if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
- hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
- if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
- hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
- if (flags & ETH_RSS_FRAG_IPV6)
- hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
- if (flags & ETH_RSS_NONFRAG_IPV6_TCP) {
- if (type == I40E_MAC_X722) {
- hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
- (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
- } else
- hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
- }
- if (flags & ETH_RSS_NONFRAG_IPV6_UDP) {
- if (type == I40E_MAC_X722) {
- hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
- (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
- (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
- } else
- hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
+ for (i = 0; i < I40E_FLOW_TYPE_MAX; i++) {
+ if (flags & (1ULL << i))
+ hena |= adapter->pcypes_tbl[i];
}
- if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
- hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
- if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
- hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
- if (flags & ETH_RSS_L2_PAYLOAD)
- hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
return hena;
}
/* Parse the hash enable flags */
uint64_t
-i40e_parse_hena(uint64_t flags)
+i40e_parse_hena(uint64_t flags, struct i40e_adapter *adapter)
{
uint64_t rss_hf = 0;
if (!flags)
return rss_hf;
- if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
- rss_hf |= ETH_RSS_FRAG_IPV4;
- if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
- rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
- if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK))
- rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
- if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
- rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
- if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP))
- rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
- if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP))
- rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
- if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
- rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
- if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
- rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
- if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
- rss_hf |= ETH_RSS_FRAG_IPV6;
- if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
- rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
- if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
- rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
- if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
- rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
- if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP))
- rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
- if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
- rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
- if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
- rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
- if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
- rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
- if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
- rss_hf |= ETH_RSS_L2_PAYLOAD;
+ int i;
+ for (i = 0; i < I40E_FLOW_TYPE_MAX; i++) {
+ if (flags & adapter->pcypes_tbl[i])
+ rss_hf |= (1ULL << i);
+ }
return rss_hf;
}
@@ -6662,16 +6595,9 @@ static void
i40e_pf_disable_rss(struct i40e_pf *pf)
{
struct i40e_hw *hw = I40E_PF_TO_HW(pf);
- uint64_t hena;
- hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
- hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
- if (hw->mac.type == I40E_MAC_X722)
- hena &= ~I40E_RSS_HENA_ALL_X722;
- else
- hena &= ~I40E_RSS_HENA_ALL;
- i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
- i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
+ i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
+ i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
I40E_WRITE_FLUSH(hw);
}
@@ -6743,23 +6669,14 @@ static int
i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
{
struct i40e_hw *hw = I40E_PF_TO_HW(pf);
- uint64_t rss_hf;
uint64_t hena;
int ret;
- ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
- rss_conf->rss_key_len);
+ ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key, rss_conf->rss_key_len);
if (ret)
return ret;
- rss_hf = rss_conf->rss_hf;
- hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
- hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
- if (hw->mac.type == I40E_MAC_X722)
- hena &= ~I40E_RSS_HENA_ALL_X722;
- else
- hena &= ~I40E_RSS_HENA_ALL;
- hena |= i40e_config_hena(rss_hf, hw->mac.type);
+ hena = i40e_config_hena(rss_conf->rss_hf, pf->adapter);
i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
I40E_WRITE_FLUSH(hw);
@@ -6773,14 +6690,13 @@ i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
{
struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
- uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
+ uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_msk;
uint64_t hena;
hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
- if (!(hena & ((hw->mac.type == I40E_MAC_X722)
- ? I40E_RSS_HENA_ALL_X722
- : I40E_RSS_HENA_ALL))) { /* RSS disabled */
+
+ if (!(hena & pf->adapter->pctypes_msk)) { /* RSS disabled */
if (rss_hf != 0) /* Enable RSS */
return -EINVAL;
return 0; /* Nothing to do */
@@ -6805,7 +6721,7 @@ i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
- rss_conf->rss_hf = i40e_parse_hena(hena);
+ rss_conf->rss_hf = i40e_parse_hena(hena, pf->adapter);
return 0;
}
@@ -7580,7 +7496,7 @@ i40e_pf_config_rss(struct i40e_pf *pf)
}
rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
- if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
+ if ((rss_conf.rss_hf & pf->adapter->flow_types_msk) == 0) {
i40e_pf_disable_rss(pf);
return 0;
}
@@ -7801,9 +7717,9 @@ static int
i40e_get_hash_filter_global_config(struct i40e_hw *hw,
struct rte_eth_hash_global_conf *g_cfg)
{
- uint32_t reg, mask = I40E_FLOW_TYPES;
- uint16_t i;
- enum i40e_filter_pctype pctype;
+ struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
+ uint32_t reg;
+ uint16_t i, j;
memset(g_cfg, 0, sizeof(*g_cfg));
reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
@@ -7814,29 +7730,31 @@ i40e_get_hash_filter_global_config(struct i40e_hw *hw,
PMD_DRV_LOG(DEBUG, "Hash function is %s",
(reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
- for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
- if (!(mask & (1UL << i)))
- continue;
- mask &= ~(1UL << i);
- /* Bit set indicats the coresponding flow type is supported */
- g_cfg->valid_bit_mask[0] |= (1UL << i);
- /* if flowtype is invalid, continue */
- if (!I40E_VALID_FLOW(i))
- continue;
- pctype = i40e_flowtype_to_pctype(i);
- reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
- if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
- g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
+ g_cfg->valid_bit_mask[0] = (uint32_t)adapter->flow_types_msk;
+
+ for (i = 0; i < UINT32_BIT; i++) {
+ if (adapter->pcypes_tbl[i]) {
+ for (j = 0; j < I40E_PCTYPE_MAX; j++) {
+ if (adapter->pcypes_tbl[i] & (1ULL << j)) {
+ reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
+ if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
+ g_cfg->sym_hash_enable_mask[0] |=
+ (1UL << i);
+ }
+ }
+ }
+ }
}
return 0;
}
static int
-i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
+i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg,
+ struct i40e_adapter *adapter)
{
uint32_t i;
- uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
+ uint32_t mask0, i40e_mask = adapter->flow_types_msk;
if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
@@ -7879,64 +7797,26 @@ static int
i40e_set_hash_filter_global_config(struct i40e_hw *hw,
struct rte_eth_hash_global_conf *g_cfg)
{
+ struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
int ret;
- uint16_t i;
+ uint16_t i, j;
uint32_t reg;
- uint32_t mask0 = g_cfg->valid_bit_mask[0];
- enum i40e_filter_pctype pctype;
+ uint32_t mask0 = g_cfg->valid_bit_mask[0] & (uint32_t)adapter->flow_types_msk;
/* Check the input parameters */
- ret = i40e_hash_global_config_check(g_cfg);
+ ret = i40e_hash_global_config_check(g_cfg, adapter);
if (ret < 0)
return ret;
- for (i = 0; mask0 && i < UINT32_BIT; i++) {
- if (!(mask0 & (1UL << i)))
- continue;
- mask0 &= ~(1UL << i);
- /* if flowtype is invalid, continue */
- if (!I40E_VALID_FLOW(i))
- continue;
- pctype = i40e_flowtype_to_pctype(i);
- reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
- I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
- if (hw->mac.type == I40E_MAC_X722) {
- if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_UDP) {
- i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
- I40E_FILTER_PCTYPE_NONF_IPV4_UDP), reg);
- i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
- I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP),
- reg);
- i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
- I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP),
- reg);
- } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_TCP) {
- i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
- I40E_FILTER_PCTYPE_NONF_IPV4_TCP), reg);
- i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
- I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK),
- reg);
- } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_UDP) {
- i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
- I40E_FILTER_PCTYPE_NONF_IPV6_UDP), reg);
- i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
- I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP),
- reg);
- i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
- I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP),
- reg);
- } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_TCP) {
- i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
- I40E_FILTER_PCTYPE_NONF_IPV6_TCP), reg);
- i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
- I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK),
- reg);
- } else {
- i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype),
- reg);
+ for (i = 0; i < UINT32_BIT; i++) {
+ if (mask0 & (1UL << i)) {
+ reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
+ I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
+
+ for (j = 0; j < I40E_PCTYPE_MAX; j++) {
+ if (adapter->pcypes_tbl[i] & (1ULL << j))
+ i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(j), reg);
}
- } else {
- i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
}
}
@@ -8639,9 +8519,9 @@ i40e_hash_filter_inset_select(struct i40e_hw *hw,
/* get translated pctype value in fd pctype register */
pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
I40E_GLQF_FD_PCTYPES((int)i40e_flowtype_to_pctype(
- conf->flow_type)));
+ conf->flow_type, pf->adapter)));
} else
- pctype = i40e_flowtype_to_pctype(conf->flow_type);
+ pctype = i40e_flowtype_to_pctype(conf->flow_type, pf->adapter);
ret = i40e_parse_input_set(&input_set, pctype, conf->field,
conf->inset_size);
@@ -8712,7 +8592,7 @@ i40e_fdir_filter_inset_select(struct i40e_pf *pf,
return -EINVAL;
}
- pctype = i40e_flowtype_to_pctype(conf->flow_type);
+ pctype = i40e_flowtype_to_pctype(conf->flow_type, pf->adapter);
ret = i40e_parse_input_set(&input_set, pctype, conf->field,
conf->inset_size);
@@ -9163,72 +9043,31 @@ i40e_hw_init(struct rte_eth_dev *dev)
i40e_set_symmetric_hash_enable_per_port(hw, 0);
}
-enum i40e_filter_pctype
-i40e_flowtype_to_pctype(uint16_t flow_type)
-{
- static const enum i40e_filter_pctype pctype_table[] = {
- [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
- [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
- I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
- [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
- I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
- [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
- I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
- [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
- I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
- [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
- [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
- I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
- [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
- I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
- [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
- I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
- [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
- I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
- [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
- };
+uint16_t
+i40e_flowtype_to_pctype(uint16_t flow_type, struct i40e_adapter *adapter)
+{
+ int i;
+ uint64_t pctype_mask = adapter->pcypes_tbl[flow_type];
- return pctype_table[flow_type];
+ for (i = I40E_PCTYPE_MAX - 1; i >= 0; i--) {
+ if (pctype_mask & (1ULL << i))
+ return (uint16_t)i;
+ }
+ return 0;
}
uint16_t
-i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
+i40e_pctype_to_flowtype(uint16_t pctype, struct i40e_adapter *adapter)
{
- static const uint16_t flowtype_table[] = {
- [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
- [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
- RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
- [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
- RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
- [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
- RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
- [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
- RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
- [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
- RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
- [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
- RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
- [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
- RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
- [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
- [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
- RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
- [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
- RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
- [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
- RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
- [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
- RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
- [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
- RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
- [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
- RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
- [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
- RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
- [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
- };
+ uint16_t flowtype = RTE_ETH_FLOW_UNKNOWN;
+ uint64_t pctype_mask = 1ULL << pctype;
+
+ for (; flowtype < I40E_FLOW_TYPE_MAX; flowtype++) {
+ if (adapter->pcypes_tbl[flowtype] & pctype_mask)
+ return flowtype;
+ }
- return flowtype_table[pctype];
+ return flowtype;
}
/*
diff --git a/drivers/net/i40e/i40e_ethdev.h b/drivers/net/i40e/i40e_ethdev.h
index 48abc05..9dc4617 100644
--- a/drivers/net/i40e/i40e_ethdev.h
+++ b/drivers/net/i40e/i40e_ethdev.h
@@ -852,7 +852,9 @@ struct i40e_vf {
uint64_t flags;
};
-#define I40E_MAX_PKT_TYPE 256
+#define I40E_MAX_PKT_TYPE 256
+#define I40E_FLOW_TYPE_MAX 64
+#define I40E_PCTYPE_MAX 64
/*
* Structure to store private data for each PF/VF instance.
@@ -881,6 +883,10 @@ struct i40e_adapter {
/* ptype mapping table */
uint32_t ptype_tbl[I40E_MAX_PKT_TYPE] __rte_cache_min_aligned;
+ /* flow type to pctype mapping table */
+ uint64_t pcypes_tbl[I40E_FLOW_TYPE_MAX] __rte_cache_min_aligned;
+ uint64_t flow_types_msk;
+ uint64_t pctypes_msk;
};
extern const struct rte_flow_ops i40e_flow_ops;
@@ -925,8 +931,8 @@ int i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
struct i40e_vsi_vlan_pvid_info *info);
int i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on);
int i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on);
-uint64_t i40e_config_hena(uint64_t flags, enum i40e_mac_type type);
-uint64_t i40e_parse_hena(uint64_t flags);
+uint64_t i40e_config_hena(uint64_t flags, struct i40e_adapter *adapter);
+uint64_t i40e_parse_hena(uint64_t flags, struct i40e_adapter *adapter);
enum i40e_status_code i40e_fdir_setup_tx_resources(struct i40e_pf *pf);
enum i40e_status_code i40e_fdir_setup_rx_resources(struct i40e_pf *pf);
int i40e_fdir_setup(struct i40e_pf *pf);
@@ -935,8 +941,8 @@ const struct rte_memzone *i40e_memzone_reserve(const char *name,
int socket_id);
int i40e_fdir_configure(struct rte_eth_dev *dev);
void i40e_fdir_teardown(struct i40e_pf *pf);
-enum i40e_filter_pctype i40e_flowtype_to_pctype(uint16_t flow_type);
-uint16_t i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype);
+uint16_t i40e_flowtype_to_pctype(uint16_t flow_type, struct i40e_adapter *adapter);
+uint16_t i40e_pctype_to_flowtype(uint16_t pctype, struct i40e_adapter *adapter);
int i40e_fdir_ctrl_func(struct rte_eth_dev *dev,
enum rte_filter_op filter_op,
void *arg);
diff --git a/drivers/net/i40e/i40e_ethdev_vf.c b/drivers/net/i40e/i40e_ethdev_vf.c
index f6d8293..4a0a06f 100644
--- a/drivers/net/i40e/i40e_ethdev_vf.c
+++ b/drivers/net/i40e/i40e_ethdev_vf.c
@@ -1503,6 +1503,7 @@ i40evf_dev_init(struct rte_eth_dev *eth_dev)
return 0;
}
i40e_set_default_ptype_table(eth_dev);
+ i40e_set_default_pctype_table(eth_dev);
rte_eth_copy_pci_info(eth_dev, pci_dev);
eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
@@ -2295,7 +2296,7 @@ i40evf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
dev_info->hash_key_size = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
dev_info->reta_size = ETH_RSS_RETA_SIZE_64;
- dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
+ dev_info->flow_type_rss_offloads = vf->adapter->flow_types_msk;
dev_info->max_mac_addrs = I40E_NUM_MACADDR_MAX;
dev_info->rx_offload_capa =
DEV_RX_OFFLOAD_VLAN_STRIP |
@@ -2580,7 +2581,7 @@ static int
i40evf_hw_rss_hash_set(struct i40e_vf *vf, struct rte_eth_rss_conf *rss_conf)
{
struct i40e_hw *hw = I40E_VF_TO_HW(vf);
- uint64_t rss_hf, hena;
+ uint64_t hena;
int ret;
ret = i40evf_set_rss_key(&vf->vsi, rss_conf->rss_key,
@@ -2588,14 +2589,7 @@ i40evf_hw_rss_hash_set(struct i40e_vf *vf, struct rte_eth_rss_conf *rss_conf)
if (ret)
return ret;
- rss_hf = rss_conf->rss_hf;
- hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
- hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
- if (hw->mac.type == I40E_MAC_X722)
- hena &= ~I40E_RSS_HENA_ALL_X722;
- else
- hena &= ~I40E_RSS_HENA_ALL;
- hena |= i40e_config_hena(rss_hf, hw->mac.type);
+ hena = i40e_config_hena(rss_conf->rss_hf, vf->adapter);
i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), (uint32_t)hena);
i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32));
I40EVF_WRITE_FLUSH(hw);
@@ -2607,16 +2601,9 @@ static void
i40evf_disable_rss(struct i40e_vf *vf)
{
struct i40e_hw *hw = I40E_VF_TO_HW(vf);
- uint64_t hena;
- hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
- hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
- if (hw->mac.type == I40E_MAC_X722)
- hena &= ~I40E_RSS_HENA_ALL_X722;
- else
- hena &= ~I40E_RSS_HENA_ALL;
- i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), (uint32_t)hena);
- i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32));
+ i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), 0);
+ i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), 0);
I40EVF_WRITE_FLUSH(hw);
}
@@ -2645,7 +2632,7 @@ i40evf_config_rss(struct i40e_vf *vf)
}
rss_conf = vf->dev_data->dev_conf.rx_adv_conf.rss_conf;
- if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
+ if ((rss_conf.rss_hf & vf->adapter->flow_types_msk) == 0) {
i40evf_disable_rss(vf);
PMD_DRV_LOG(DEBUG, "No hash flag is set");
return 0;
@@ -2670,14 +2657,13 @@ i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
{
struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
- uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
+ uint64_t rss_hf = rss_conf->rss_hf & vf->adapter->flow_types_msk;
uint64_t hena;
hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
- if (!(hena & ((hw->mac.type == I40E_MAC_X722)
- ? I40E_RSS_HENA_ALL_X722
- : I40E_RSS_HENA_ALL))) { /* RSS disabled */
+
+ if (!(hena & vf->adapter->pctypes_msk)) { /* RSS disabled */
if (rss_hf != 0) /* Enable RSS */
return -EINVAL;
return 0;
@@ -2703,7 +2689,7 @@ i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
- rss_conf->rss_hf = i40e_parse_hena(hena);
+ rss_conf->rss_hf = i40e_parse_hena(hena, vf->adapter);
return 0;
}
--
2.5.5
^ permalink raw reply [flat|nested] 6+ messages in thread