[dpdk-dev] [PATCH 1/7] net/i40e: support RSS for GTP-C and GTP-U

[Beilei Xing <beilei.xing@intel.com>]

GTP-C and GTP-U are supported by new profile.
Add new PCTYPE and enable RSS for GTP-C and GTP-U.

Signed-off-by: Beilei Xing <beilei.xing@intel.com>
---
 drivers/net/i40e/i40e_ethdev.c | 14 ++++++++++++++
 drivers/net/i40e/i40e_ethdev.h | 10 +++++++++-
 2 files changed, 23 insertions(+), 1 deletion(-)

diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c
index 4a2e3f2..7c9e5af 100644
--- a/drivers/net/i40e/i40e_ethdev.c
+++ b/drivers/net/i40e/i40e_ethdev.c
@@ -197,6 +197,8 @@
 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 /* UDP Tunneling ID, NVGRE/GRE key */
 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
+/* GTP TEID */
+#define I40E_REG_INSET_GTP_TEID                  0x0000000000020000ULL
 /* Last ether type */
 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 /* Tunneling outer destination IPv4 address */
@@ -6760,6 +6762,11 @@ i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
 	else
 		hena &= ~I40E_RSS_HENA_ALL;
 	hena |= i40e_config_hena(rss_hf, hw->mac.type);
+
+	/* Enable GTP-C/U by default */
+	hena |= 1ULL << I40E_FILTER_PCTYPE_GTPC;
+	hena |= 1ULL << I40E_FILTER_PCTYPE_GTPU;
+
 	i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
 	i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
 	I40E_WRITE_FLUSH(hw);
@@ -8123,6 +8130,12 @@ i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
 			I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
 			I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
 			I40E_INSET_FLEX_PAYLOAD,
+		[I40E_FILTER_PCTYPE_GTPC] =
+			I40E_INSET_GTP_TEID | I40E_INSET_IPV4_SRC |
+			I40E_INSET_IPV4_DST,
+		[I40E_FILTER_PCTYPE_GTPU] =
+			I40E_INSET_GTP_TEID | I40E_INSET_IPV4_SRC |
+			I40E_INSET_IPV4_DST,
 	};
 
 	/**
@@ -8449,6 +8462,7 @@ i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
 		{I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
 		{I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
 		{I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
+		{I40E_INSET_GTP_TEID, I40E_REG_INSET_GTP_TEID},
 	};
 
     /* some different registers map in x722*/
diff --git a/drivers/net/i40e/i40e_ethdev.h b/drivers/net/i40e/i40e_ethdev.h
index 48abc05..ab2a5cd 100644
--- a/drivers/net/i40e/i40e_ethdev.h
+++ b/drivers/net/i40e/i40e_ethdev.h
@@ -119,6 +119,10 @@ enum i40e_flxpld_layer_idx {
 #define I40E_FDIR_MAX_FLEX_LEN      16 /* len in bytes of flex payload */
 #define I40E_INSET_MASK_NUM_REG     2  /* number of input set mask registers */
 
+/* New PCTYE for GTP-C and GTP-U */
+#define I40E_FILTER_PCTYPE_GTPC		23
+#define I40E_FILTER_PCTYPE_GTPU		24
+
 /* i40e flags */
 #define I40E_FLAG_RSS                   (1ULL << 0)
 #define I40E_FLAG_DCB                   (1ULL << 1)
@@ -234,6 +238,8 @@ enum i40e_flxpld_layer_idx {
 #define I40E_INSET_TUNNEL_DST_PORT       0x0000001000000000ULL
 #define I40E_INSET_TUNNEL_ID             0x0000002000000000ULL
 
+#define I40E_INSET_GTP_TEID              0x0000004000000000ULL
+
 /* bit 48 ~ bit 55 */
 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
 
@@ -1131,7 +1137,9 @@ i40e_calc_itr_interval(int16_t interval)
 	(pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP || \
 	(pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP || \
 	(pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \
-	(pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD)
+	(pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD || \
+	(pctype) == I40E_FILTER_PCTYPE_GTPC || \
+	(pctype) == I40E_FILTER_PCTYPE_GTPU)
 
 #define I40E_PHY_TYPE_SUPPORT_40G(phy_type) \
 	(((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_KR4) || \
-- 
2.5.5