From: Rasesh Mody <rasesh.mody@cavium.com>
To: dev@dpdk.org, ferruh.yigit@intel.com
Cc: Rasesh Mody <rasesh.mody@cavium.com>, Dept-EngDPDKDev@cavium.com
Subject: [dpdk-dev] [PATCH 51/53] net/qede/base: add support for WoL writes
Date: Mon, 18 Sep 2017 18:51:41 -0700 [thread overview]
Message-ID: <1505785903-1741-22-git-send-email-rasesh.mody@cavium.com> (raw)
In-Reply-To: <1505785903-1741-1-git-send-email-rasesh.mody@cavium.com>
Add support programing of WoL Bitmap paterns via management FW mailbox.
Signed-off-by: Rasesh Mody <rasesh.mody@cavium.com>
---
drivers/net/qede/base/ecore_dev.c | 26 +++++++++++++-------------
drivers/net/qede/base/ecore_mcp.c | 26 ++++++++++++++++++++++++++
drivers/net/qede/base/ecore_mcp.h | 3 +++
drivers/net/qede/base/mcp_public.h | 18 ++++++++++++++----
4 files changed, 56 insertions(+), 17 deletions(-)
diff --git a/drivers/net/qede/base/ecore_dev.c b/drivers/net/qede/base/ecore_dev.c
index 9511110..e47d5c7 100644
--- a/drivers/net/qede/base/ecore_dev.c
+++ b/drivers/net/qede/base/ecore_dev.c
@@ -3318,8 +3318,8 @@ static enum _ecore_status_t ecore_hw_get_resc(struct ecore_hwfn *p_hwfn,
nvm_cfg1_offset = ecore_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
- OFFSETOF(struct nvm_cfg1, glob) + OFFSETOF(struct nvm_cfg1_glob,
- core_cfg);
+ OFFSETOF(struct nvm_cfg1, glob) +
+ OFFSETOF(struct nvm_cfg1_glob, core_cfg);
core_cfg = ecore_rd(p_hwfn, p_ptt, addr);
@@ -3399,8 +3399,8 @@ static enum _ecore_status_t ecore_hw_get_resc(struct ecore_hwfn *p_hwfn,
p_caps->speed_capabilities = link->speed.advertised_speeds;
link_temp = ecore_rd(p_hwfn, p_ptt,
- port_cfg_addr +
- OFFSETOF(struct nvm_cfg1_port, link_settings));
+ port_cfg_addr +
+ OFFSETOF(struct nvm_cfg1_port, link_settings));
switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
@@ -3480,8 +3480,8 @@ static enum _ecore_status_t ecore_hw_get_resc(struct ecore_hwfn *p_hwfn,
/* Read Multi-function information from shmem */
addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
- OFFSETOF(struct nvm_cfg1, glob) +
- OFFSETOF(struct nvm_cfg1_glob, generic_cont0);
+ OFFSETOF(struct nvm_cfg1, glob) +
+ OFFSETOF(struct nvm_cfg1_glob, generic_cont0);
generic_cont0 = ecore_rd(p_hwfn, p_ptt, addr);
@@ -3540,25 +3540,25 @@ static enum _ecore_status_t ecore_hw_get_resc(struct ecore_hwfn *p_hwfn,
/* Read Multi-function information from shmem */
addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
- OFFSETOF(struct nvm_cfg1, glob) +
- OFFSETOF(struct nvm_cfg1_glob, device_capabilities);
+ OFFSETOF(struct nvm_cfg1, glob) +
+ OFFSETOF(struct nvm_cfg1_glob, device_capabilities);
device_capabilities = ecore_rd(p_hwfn, p_ptt, addr);
if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
OSAL_SET_BIT(ECORE_DEV_CAP_ETH,
- &p_hwfn->hw_info.device_capabilities);
+ &p_hwfn->hw_info.device_capabilities);
if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE)
OSAL_SET_BIT(ECORE_DEV_CAP_FCOE,
- &p_hwfn->hw_info.device_capabilities);
+ &p_hwfn->hw_info.device_capabilities);
if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
OSAL_SET_BIT(ECORE_DEV_CAP_ISCSI,
- &p_hwfn->hw_info.device_capabilities);
+ &p_hwfn->hw_info.device_capabilities);
if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
OSAL_SET_BIT(ECORE_DEV_CAP_ROCE,
- &p_hwfn->hw_info.device_capabilities);
+ &p_hwfn->hw_info.device_capabilities);
if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_IWARP)
OSAL_SET_BIT(ECORE_DEV_CAP_IWARP,
- &p_hwfn->hw_info.device_capabilities);
+ &p_hwfn->hw_info.device_capabilities);
rc = ecore_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) {
diff --git a/drivers/net/qede/base/ecore_mcp.c b/drivers/net/qede/base/ecore_mcp.c
index 06e426a..3df8fce 100644
--- a/drivers/net/qede/base/ecore_mcp.c
+++ b/drivers/net/qede/base/ecore_mcp.c
@@ -3764,3 +3764,29 @@ enum _ecore_status_t
return ECORE_SUCCESS;
}
+
+void ecore_mcp_wol_wr(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
+ u32 offset, u32 val)
+{
+ struct ecore_mcp_mb_params mb_params = {0};
+ enum _ecore_status_t rc = ECORE_SUCCESS;
+ u32 dword = val;
+
+ mb_params.cmd = DRV_MSG_CODE_WRITE_WOL_REG;
+ mb_params.param = offset;
+ mb_params.p_data_src = &dword;
+ mb_params.data_src_size = sizeof(dword);
+
+ rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
+ if (rc != ECORE_SUCCESS) {
+ DP_NOTICE(p_hwfn, false,
+ "Failed to wol write request, rc = %d\n", rc);
+ }
+
+ if (mb_params.mcp_resp != FW_MSG_CODE_WOL_READ_WRITE_OK) {
+ DP_NOTICE(p_hwfn, false,
+ "Failed to write value 0x%x to offset 0x%x [mcp_resp 0x%x]\n",
+ val, offset, mb_params.mcp_resp);
+ rc = ECORE_UNKNOWN_ERROR;
+ }
+}
diff --git a/drivers/net/qede/base/ecore_mcp.h b/drivers/net/qede/base/ecore_mcp.h
index 875b205..6afaf7d 100644
--- a/drivers/net/qede/base/ecore_mcp.h
+++ b/drivers/net/qede/base/ecore_mcp.h
@@ -565,4 +565,7 @@ enum _ecore_status_t
void
ecore_mcp_read_ufp_config(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt);
+void ecore_mcp_wol_wr(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
+ u32 offset, u32 val);
+
#endif /* __ECORE_MCP_H__ */
diff --git a/drivers/net/qede/base/mcp_public.h b/drivers/net/qede/base/mcp_public.h
index d568179..799357a 100644
--- a/drivers/net/qede/base/mcp_public.h
+++ b/drivers/net/qede/base/mcp_public.h
@@ -1248,12 +1248,12 @@ struct public_drv_mb {
#define DRV_MSG_CODE_NVM_PUT_FILE_DATA 0x00020000
/* MFW will place the file offset and len in file_att struct */
#define DRV_MSG_CODE_NVM_GET_FILE_ATT 0x00030000
-/* Read 32bytes of nvram data. Param is [0:23] – Offset [24:31] –
- * Len in Bytes
+/* Read 32bytes of nvram data. Param is [0:23] ??? Offset [24:31] -
+ * ??? Len in Bytes
*/
#define DRV_MSG_CODE_NVM_READ_NVRAM 0x00050000
-/* Writes up to 32Bytes to nvram. Param is [0:23] – Offset [24:31] –
- * Len in Bytes. In case this address is in the range of secured file in
+/* Writes up to 32Bytes to nvram. Param is [0:23] ??? Offset [24:31]
+ * ??? Len in Bytes. In case this address is in the range of secured file in
* secured mode, the operation will fail
*/
#define DRV_MSG_CODE_NVM_WRITE_NVRAM 0x00060000
@@ -1431,10 +1431,14 @@ struct public_drv_mb {
#define DRV_MB_PARAM_PORT_MASK 0x00600000
#define DRV_MSG_CODE_EXT_PHY_FW_UPGRADE 0x002a0000
+#define DRV_MSG_CODE_GET_TLV_DONE 0x002f0000 /* Param: None */
/* Param: Set DRV_MB_PARAM_FEATURE_SUPPORT_* */
#define DRV_MSG_CODE_FEATURE_SUPPORT 0x00300000
/* return FW_MB_PARAM_FEATURE_SUPPORT_* */
#define DRV_MSG_CODE_GET_MFW_FEATURE_SUPPORT 0x00310000
+#define DRV_MSG_CODE_READ_WOL_REG 0X00320000
+#define DRV_MSG_CODE_WRITE_WOL_REG 0X00330000
+#define DRV_MSG_CODE_GET_WOL_BUFFER 0X00340000
/* Param: [0:23] Attribute key, [24:31] Attribute sub command */
#define DRV_MSG_CODE_ATTRIBUTE 0x00350000
@@ -1714,6 +1718,12 @@ struct public_drv_mb {
#define FW_MSG_CODE_DRV_CFG_PF_VFS_MSIX_DONE 0x00870000
#define FW_MSG_CODE_DRV_CFG_PF_VFS_MSIX_BAD_ASIC 0x00880000
+#define FW_MSG_CODE_WOL_READ_WRITE_OK 0x00820000
+#define FW_MSG_CODE_WOL_READ_WRITE_INVALID_VAL 0x00830000
+#define FW_MSG_CODE_WOL_READ_WRITE_INVALID_ADDR 0x00840000
+#define FW_MSG_CODE_WOL_READ_BUFFER_OK 0x00850000
+#define FW_MSG_CODE_WOL_READ_BUFFER_INVALID_VAL 0x00860000
+
#define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff
#define FW_MSG_CODE_ATTRIBUTE_INVALID_KEY 0x00020000
--
1.7.10.3
next prev parent reply other threads:[~2017-09-19 1:52 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-09-19 1:51 [dpdk-dev] [PATCH 30/53] net/qede/base: read per queue coalescing from HW Rasesh Mody
2017-09-19 1:51 ` [dpdk-dev] [PATCH 31/53] net/qede/base: refactor device's number of ports logic Rasesh Mody
2017-09-19 1:51 ` [dpdk-dev] [PATCH 32/53] net/qede/base: use proper units for rate limiting Rasesh Mody
2017-09-19 1:51 ` [dpdk-dev] [PATCH 33/53] net/qede/base: use available macro Rasesh Mody
2017-09-19 1:51 ` [dpdk-dev] [PATCH 34/53] net/qede/base: use function pointers for spq async callback Rasesh Mody
2017-09-19 1:51 ` [dpdk-dev] [PATCH 35/53] net/qede/base: fix API return types Rasesh Mody
2017-09-19 1:51 ` [dpdk-dev] [PATCH 36/53] net/qede/base: semantic changes Rasesh Mody
2017-09-19 1:51 ` [dpdk-dev] [PATCH 37/53] net/qede/base: handle the error condition properly Rasesh Mody
2017-09-19 1:51 ` [dpdk-dev] [PATCH 38/53] net/qede/base: add new macro for CMT mode Rasesh Mody
2017-09-19 1:51 ` [dpdk-dev] [PATCH 39/53] net/qede/base: change verbosity Rasesh Mody
2017-09-19 1:51 ` [dpdk-dev] [PATCH 40/53] net/qede/base: fix number of app table entries Rasesh Mody
2017-09-19 1:51 ` [dpdk-dev] [PATCH 41/53] net/qede/base: update firmware to 8.30.12.0 Rasesh Mody
2017-09-19 1:51 ` [dpdk-dev] [PATCH 42/53] net/qede/base: add UFP support Rasesh Mody
2017-09-19 1:51 ` [dpdk-dev] [PATCH 43/53] net/qede/base: add support for mapped doorbell Bars for VFs Rasesh Mody
2017-09-19 1:51 ` [dpdk-dev] [PATCH 44/53] net/qede/base: add support for driver attribute repository Rasesh Mody
2017-09-19 1:51 ` [dpdk-dev] [PATCH 45/53] net/qede/base: move define to header file Rasesh Mody
2017-09-19 1:51 ` [dpdk-dev] [PATCH 46/53] net/qede/base: dcbx dscp related extensions Rasesh Mody
2017-09-19 1:51 ` [dpdk-dev] [PATCH 47/53] net/qede/base: add feature support for per-PF virtual link Rasesh Mody
2017-09-19 1:51 ` [dpdk-dev] [PATCH 48/53] net/qede/base: catch an init command write failure Rasesh Mody
2017-09-19 1:51 ` [dpdk-dev] [PATCH 49/53] net/qede/base: retain dcbx config till actually applied Rasesh Mody
2017-09-19 1:51 ` [dpdk-dev] [PATCH 50/53] net/qede/base: disable aRFS for NPAR and 100G Rasesh Mody
2017-09-19 1:51 ` Rasesh Mody [this message]
2017-09-19 1:51 ` [dpdk-dev] [PATCH 52/53] net/qede/base: remove unused input parameter Rasesh Mody
2017-09-19 1:51 ` [dpdk-dev] [PATCH 53/53] net/qede/base: update PMD version to 2.6.0.1 Rasesh Mody
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