From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by dpdk.org (Postfix) with ESMTP id D43FC1AEF5 for ; Fri, 22 Sep 2017 11:42:58 +0200 (CEST) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 22 Sep 2017 02:42:58 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.42,427,1500966000"; d="scan'208";a="1174782469" Received: from unknown (HELO dpdk9.sh.intel.com) ([10.67.118.52]) by orsmga001.jf.intel.com with ESMTP; 22 Sep 2017 02:42:56 -0700 From: Beilei Xing To: jingjing.wu@intel.com Cc: andrey.chilikin@intel.com, dev@dpdk.org Date: Sat, 23 Sep 2017 06:35:09 +0800 Message-Id: <1506119714-53437-4-git-send-email-beilei.xing@intel.com> X-Mailer: git-send-email 2.5.5 In-Reply-To: <1506119714-53437-1-git-send-email-beilei.xing@intel.com> References: <1504783263-20575-1-git-send-email-beilei.xing@intel.com> <1506119714-53437-1-git-send-email-beilei.xing@intel.com> Subject: [dpdk-dev] [PATCH v3 3/8] net/i40e: support RSS for new pctype X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 22 Sep 2017 09:42:59 -0000 Enable RSS for new pctypes after downloading new profile. Signed-off-by: Beilei Xing --- drivers/net/i40e/i40e_ethdev.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c index dcff8cc..a15d994 100644 --- a/drivers/net/i40e/i40e_ethdev.c +++ b/drivers/net/i40e/i40e_ethdev.c @@ -1924,6 +1924,30 @@ i40e_apply_link_speed(struct rte_eth_dev *dev) return i40e_phy_conf_link(hw, abilities, speed, true); } +static void +i40e_new_pctype_hash_set(struct i40e_pf *pf, bool enable) +{ + struct i40e_hw *hw = I40E_PF_TO_HW(pf); + uint64_t hena; + int i; + + hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0)); + hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32; + + for (i = 0; i < I40E_PERSONALIZED_MAX; i++) { + if (pf->new_pctype[i].valid) { + if (enable) + hena |= 1ULL << pf->new_pctype[i].pctype; + else + hena &= ~(1ULL << pf->new_pctype[i].pctype); + } + } + + i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena); + i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32)); + I40E_WRITE_FLUSH(hw); +} + static int i40e_dev_start(struct rte_eth_dev *dev) { @@ -2071,6 +2095,8 @@ i40e_dev_start(struct rte_eth_dev *dev) "please call hierarchy_commit() " "before starting the port"); + i40e_new_pctype_hash_set(pf, true); + return I40E_SUCCESS; err_up: @@ -2151,6 +2177,8 @@ i40e_dev_close(struct rte_eth_dev *dev) uint32_t reg; int i; + i40e_new_pctype_hash_set(pf, false); + PMD_INIT_FUNC_TRACE(); i40e_dev_stop(dev); -- 2.5.5