From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by dpdk.org (Postfix) with ESMTP id 0B3961B19F for ; Wed, 27 Sep 2017 15:25:13 +0200 (CEST) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 27 Sep 2017 06:25:13 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.42,445,1500966000"; d="scan'208";a="904387311" Received: from unknown (HELO dpdk9.sh.intel.com) ([10.67.118.52]) by FMSMGA003.fm.intel.com with ESMTP; 27 Sep 2017 06:25:11 -0700 From: Beilei Xing To: jingjing.wu@intel.com Cc: andrey.chilikin@intel.com, dev@dpdk.org Date: Thu, 28 Sep 2017 10:17:29 +0800 Message-Id: <1506565054-67690-4-git-send-email-beilei.xing@intel.com> X-Mailer: git-send-email 2.5.5 In-Reply-To: <1506565054-67690-1-git-send-email-beilei.xing@intel.com> References: <1506119714-53437-2-git-send-email-beilei.xing@intel.com> <1506565054-67690-1-git-send-email-beilei.xing@intel.com> Subject: [dpdk-dev] [PATCH v4 3/8] net/i40e: support RSS for new pctype X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 27 Sep 2017 13:25:14 -0000 Enable RSS for new pctypes after downloading new profile. Signed-off-by: Beilei Xing --- drivers/net/i40e/i40e_ethdev.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c index d6b0d50..aba35a5 100644 --- a/drivers/net/i40e/i40e_ethdev.c +++ b/drivers/net/i40e/i40e_ethdev.c @@ -1928,6 +1928,31 @@ i40e_apply_link_speed(struct rte_eth_dev *dev) return i40e_phy_conf_link(hw, abilities, speed, true); } +static void +i40e_customized_pctype_hash_set(struct i40e_pf *pf, bool enable) +{ + struct i40e_hw *hw = I40E_PF_TO_HW(pf); + uint64_t hena; + int i; + + hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0)); + hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32; + + for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) { + if (pf->customized_pctype[i].valid) { + if (enable) + hena |= 1ULL << pf->customized_pctype[i].pctype; + else + hena &= ~(1ULL << + pf->customized_pctype[i].pctype); + } + } + + i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena); + i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32)); + I40E_WRITE_FLUSH(hw); +} + static int i40e_dev_start(struct rte_eth_dev *dev) { @@ -2075,6 +2100,8 @@ i40e_dev_start(struct rte_eth_dev *dev) "please call hierarchy_commit() " "before starting the port"); + i40e_customized_pctype_hash_set(pf, true); + return I40E_SUCCESS; err_up: @@ -2155,6 +2182,8 @@ i40e_dev_close(struct rte_eth_dev *dev) uint32_t reg; int i; + i40e_customized_pctype_hash_set(pf, false); + PMD_INIT_FUNC_TRACE(); i40e_dev_stop(dev); -- 2.5.5