From: Raslan Darawsheh <rasland@mellanox.com>
To: dev@dpdk.org
Cc: shahafs@mellanox.com, yskoh@mellanox.com, ferruh.yigit@intel.com
Subject: [dpdk-dev] [PATCH v8 3/3] net/mlx5: add Rx HW timestamp
Date: Tue, 10 Oct 2017 10:45:05 +0300 [thread overview]
Message-ID: <1507621505-10714-3-git-send-email-rasland@mellanox.com> (raw)
In-Reply-To: <1507621505-10714-1-git-send-email-rasland@mellanox.com>
Expose Rx HW timestamp to packet mbufs.
Signed-off-by: Raslan Darawsheh <rasland@mellanox.com>
---
Changes in V8:
- Rebasing the work on top of next-net
Changes in v7:
- Rebasing the work on top ot c814b93b ("net/mlx5: add vectorized Rx/Tx burst for ARM")
- Adding the timestamp code for ARM NEON
Changes in v6:
- Rebasing the work on top of 217b1421 ("net/mlx5: separate DPDK from Verbs Rx queue objects")
---
drivers/net/mlx5/mlx5_ethdev.c | 4 +++-
drivers/net/mlx5/mlx5_rxq.c | 6 +++++-
drivers/net/mlx5/mlx5_rxtx.c | 5 +++++
drivers/net/mlx5/mlx5_rxtx.h | 3 ++-
drivers/net/mlx5/mlx5_rxtx_vec_neon.h | 22 +++++++++++++++++++++-
drivers/net/mlx5/mlx5_rxtx_vec_sse.h | 13 ++++++++++++-
6 files changed, 48 insertions(+), 5 deletions(-)
diff --git a/drivers/net/mlx5/mlx5_ethdev.c b/drivers/net/mlx5/mlx5_ethdev.c
index 9f5b489..e06dce3 100644
--- a/drivers/net/mlx5/mlx5_ethdev.c
+++ b/drivers/net/mlx5/mlx5_ethdev.c
@@ -697,7 +697,9 @@ mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info)
DEV_RX_OFFLOAD_UDP_CKSUM |
DEV_RX_OFFLOAD_TCP_CKSUM) :
0) |
- (priv->hw_vlan_strip ? DEV_RX_OFFLOAD_VLAN_STRIP : 0);
+ (priv->hw_vlan_strip ? DEV_RX_OFFLOAD_VLAN_STRIP : 0) |
+ DEV_RX_OFFLOAD_TIMESTAMP;
+
if (!priv->mps)
info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT;
if (priv->hw_csum)
diff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c
index e1867cb..632d451 100644
--- a/drivers/net/mlx5/mlx5_rxq.c
+++ b/drivers/net/mlx5/mlx5_rxq.c
@@ -608,7 +608,7 @@ mlx5_priv_rxq_ibv_new(struct priv *priv, uint16_t idx)
attr.cq.mlx5 = (struct mlx5dv_cq_init_attr){
.comp_mask = 0,
};
- if (priv->cqe_comp) {
+ if (priv->cqe_comp && !rxq_data->hw_timestamp) {
attr.cq.mlx5.comp_mask |=
MLX5DV_CQ_INIT_ATTR_MASK_COMPRESSED_CQE;
attr.cq.mlx5.cqe_comp_res_format = MLX5DV_CQE_RES_FORMAT_HASH;
@@ -618,6 +618,8 @@ mlx5_priv_rxq_ibv_new(struct priv *priv, uint16_t idx)
*/
if (rxq_check_vec_support(rxq_data) < 0)
cqe_n *= 2;
+ } else if (priv->cqe_comp && rxq_data->hw_timestamp) {
+ DEBUG("Rx CQE compression is disabled for HW timestamp");
}
tmpl->cq = ibv_cq_ex_to_cq(mlx5dv_create_cq(priv->ctx, &attr.cq.ibv,
&attr.cq.mlx5));
@@ -939,6 +941,8 @@ mlx5_priv_rxq_new(struct priv *priv, uint16_t idx, uint16_t desc,
if (priv->hw_csum_l2tun)
tmpl->rxq.csum_l2tun =
!!dev->data->dev_conf.rxmode.hw_ip_checksum;
+ tmpl->rxq.hw_timestamp =
+ !!dev->data->dev_conf.rxmode.hw_timestamp;
/* Configure VLAN stripping. */
tmpl->rxq.vlan_strip = (priv->hw_vlan_strip &&
!!dev->data->dev_conf.rxmode.hw_vlan_strip);
diff --git a/drivers/net/mlx5/mlx5_rxtx.c b/drivers/net/mlx5/mlx5_rxtx.c
index 275cd6a..961967b 100644
--- a/drivers/net/mlx5/mlx5_rxtx.c
+++ b/drivers/net/mlx5/mlx5_rxtx.c
@@ -1887,6 +1887,11 @@ mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
pkt->vlan_tci =
rte_be_to_cpu_16(cqe->vlan_info);
}
+ if (rxq->hw_timestamp) {
+ pkt->timestamp =
+ rte_be_to_cpu_64(cqe->timestamp);
+ pkt->ol_flags |= PKT_RX_TIMESTAMP;
+ }
if (rxq->crc_present)
len -= ETHER_CRC_LEN;
PKT_LEN(pkt) = len;
diff --git a/drivers/net/mlx5/mlx5_rxtx.h b/drivers/net/mlx5/mlx5_rxtx.h
index 827cb3c..ea03742 100644
--- a/drivers/net/mlx5/mlx5_rxtx.h
+++ b/drivers/net/mlx5/mlx5_rxtx.h
@@ -106,6 +106,7 @@ struct rxq_zip {
struct mlx5_rxq_data {
unsigned int csum:1; /* Enable checksum offloading. */
unsigned int csum_l2tun:1; /* Same for L2 tunnels. */
+ unsigned int hw_timestamp:1; /* Enable HW timestamp. */
unsigned int vlan_strip:1; /* Enable VLAN stripping. */
unsigned int crc_present:1; /* CRC must be subtracted. */
unsigned int sges_n:2; /* Log 2 of SGEs (max buffers per packet). */
@@ -114,7 +115,7 @@ struct mlx5_rxq_data {
unsigned int rss_hash:1; /* RSS hash result is enabled. */
unsigned int mark:1; /* Marked flow available on the queue. */
unsigned int pending_err:1; /* CQE error needs to be handled. */
- unsigned int :15; /* Remaining bits. */
+ unsigned int :14; /* Remaining bits. */
volatile uint32_t *rq_db;
volatile uint32_t *cq_db;
uint16_t port_id;
diff --git a/drivers/net/mlx5/mlx5_rxtx_vec_neon.h b/drivers/net/mlx5/mlx5_rxtx_vec_neon.h
index 6dd18b6..ee8ecfa 100644
--- a/drivers/net/mlx5/mlx5_rxtx_vec_neon.h
+++ b/drivers/net/mlx5/mlx5_rxtx_vec_neon.h
@@ -573,7 +573,9 @@ rxq_cq_to_ptype_oflags_v(struct mlx5_rxq_data *rxq,
{
uint16x4_t ptype;
uint32x4_t pinfo, cv_flags;
- uint32x4_t ol_flags = vdupq_n_u32(rxq->rss_hash * PKT_RX_RSS_HASH);
+ uint32x4_t ol_flags =
+ vdupq_n_u32(rxq->rss_hash * PKT_RX_RSS_HASH |
+ rxq->hw_timestamp * PKT_RX_TIMESTAMP);
const uint32x4_t ptype_ol_mask = { 0x106, 0x106, 0x106, 0x106 };
const uint8x16_t cv_flag_sel = {
0,
@@ -982,6 +984,24 @@ rxq_burst_v(struct mlx5_rxq_data *rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
/* C.4 fill in mbuf - rearm_data and packet_type. */
rxq_cq_to_ptype_oflags_v(rxq, ptype_info, flow_tag,
opcode, &elts[pos]);
+ if (rxq->hw_timestamp) {
+ elts[pos]->timestamp =
+ rte_be_to_cpu_64(
+ container_of(p0, struct mlx5_cqe,
+ pkt_info)->timestamp);
+ elts[pos + 1]->timestamp =
+ rte_be_to_cpu_64(
+ container_of(p1, struct mlx5_cqe,
+ pkt_info)->timestamp);
+ elts[pos + 2]->timestamp =
+ rte_be_to_cpu_64(
+ container_of(p2, struct mlx5_cqe,
+ pkt_info)->timestamp);
+ elts[pos + 3]->timestamp =
+ rte_be_to_cpu_64(
+ container_of(p3, struct mlx5_cqe,
+ pkt_info)->timestamp);
+ }
#ifdef MLX5_PMD_SOFT_COUNTERS
/* Add up received bytes count. */
byte_cnt = vbic_u16(byte_cnt, invalid_mask);
diff --git a/drivers/net/mlx5/mlx5_rxtx_vec_sse.h b/drivers/net/mlx5/mlx5_rxtx_vec_sse.h
index 88c5d75..ab2d05b 100644
--- a/drivers/net/mlx5/mlx5_rxtx_vec_sse.h
+++ b/drivers/net/mlx5/mlx5_rxtx_vec_sse.h
@@ -552,7 +552,8 @@ rxq_cq_to_ptype_oflags_v(struct mlx5_rxq_data *rxq, __m128i cqes[4],
{
__m128i pinfo0, pinfo1;
__m128i pinfo, ptype;
- __m128i ol_flags = _mm_set1_epi32(rxq->rss_hash * PKT_RX_RSS_HASH);
+ __m128i ol_flags = _mm_set1_epi32(rxq->rss_hash * PKT_RX_RSS_HASH |
+ rxq->hw_timestamp * PKT_RX_TIMESTAMP);
__m128i cv_flags;
const __m128i zero = _mm_setzero_si128();
const __m128i ptype_mask =
@@ -947,6 +948,16 @@ rxq_burst_v(struct mlx5_rxq_data *rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
rxq->pending_err |= !!_mm_cvtsi128_si64(opcode);
/* D.5 fill in mbuf - rearm_data and packet_type. */
rxq_cq_to_ptype_oflags_v(rxq, cqes, opcode, &pkts[pos]);
+ if (rxq->hw_timestamp) {
+ pkts[pos]->timestamp =
+ rte_be_to_cpu_64(cq[pos].timestamp);
+ pkts[pos + 1]->timestamp =
+ rte_be_to_cpu_64(cq[pos + p1].timestamp);
+ pkts[pos + 2]->timestamp =
+ rte_be_to_cpu_64(cq[pos + p2].timestamp);
+ pkts[pos + 3]->timestamp =
+ rte_be_to_cpu_64(cq[pos + p3].timestamp);
+ }
#ifdef MLX5_PMD_SOFT_COUNTERS
/* Add up received bytes count. */
byte_cnt = _mm_shuffle_epi8(op_own, len_shuf_mask);
--
2.7.4
next prev parent reply other threads:[~2017-10-10 7:45 UTC|newest]
Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-08-22 13:46 [dpdk-dev] [PATCH 1/3] ethdev: expose Rx hardware timestamp Raslan Darawsheh
2017-08-22 13:46 ` [dpdk-dev] [PATCH 2/3] app/testpmd: add Rx timestamp in testpmd Raslan Darawsheh
2017-08-22 13:46 ` [dpdk-dev] [PATCH 3/3] net/mlx5: add hardware timestamp Raslan Darawsheh
2017-08-23 15:02 ` Nélio Laranjeiro
2017-08-24 7:46 ` [dpdk-dev] [PATCH v2 1/3] ethdev: expose Rx " Raslan Darawsheh
2017-08-24 7:46 ` [dpdk-dev] [PATCH v2 2/3] app/testpmd: add Rx timestamp in testpmd Raslan Darawsheh
2017-08-24 13:49 ` Nélio Laranjeiro
2017-08-24 7:46 ` [dpdk-dev] [PATCH v2 3/3] net/mlx5: add hardware timestamp Raslan Darawsheh
2017-08-24 14:01 ` Nélio Laranjeiro
2017-08-24 13:47 ` [dpdk-dev] [PATCH v2 1/3] ethdev: expose Rx " Nélio Laranjeiro
2017-09-28 16:48 ` [dpdk-dev] [PATCH v3 1/3] ethdev: add Rx HW timestamp capability Raslan Darawsheh
2017-09-28 16:48 ` [dpdk-dev] [PATCH v3 2/3] app/testpmd: add Rx HW timestamp Raslan Darawsheh
2017-09-28 16:48 ` [dpdk-dev] [PATCH v3 3/3] net/mlx5: " Raslan Darawsheh
2017-09-29 7:25 ` [dpdk-dev] [PATCH v3 1/3] ethdev: add Rx HW timestamp capability Andrew Rybchenko
2017-10-01 6:44 ` Shahaf Shuler
2017-10-02 14:50 ` [dpdk-dev] [PATCH " Raslan Darawsheh
2017-10-02 14:50 ` [dpdk-dev] [PATCH 2/3] app/testpmd: add Rx HW timestamp Raslan Darawsheh
2017-10-02 14:50 ` [dpdk-dev] [PATCH 3/3] net/mlx5: " Raslan Darawsheh
2017-10-02 18:48 ` [dpdk-dev] [PATCH 1/3] ethdev: add Rx HW timestamp capability Ferruh Yigit
2017-10-03 0:39 ` Yongseok Koh
2017-10-03 6:33 ` [dpdk-dev] [PATCH v5 " Raslan Darawsheh
2017-10-03 6:33 ` [dpdk-dev] [PATCH v5 2/3] app/testpmd: add Rx HW timestamp Raslan Darawsheh
2017-10-03 6:33 ` [dpdk-dev] [PATCH v5 3/3] net/mlx5: " Raslan Darawsheh
2017-10-03 6:40 ` [dpdk-dev] [PATCH v5 1/3] ethdev: add Rx HW timestamp capability Andrew Rybchenko
2017-10-03 6:53 ` Yongseok Koh
2017-10-03 7:24 ` Andrew Rybchenko
2017-10-03 11:00 ` [dpdk-dev] [PATCH v6 " Raslan Darawsheh
2017-10-03 11:00 ` [dpdk-dev] [PATCH v6 2/3] app/testpmd: add Rx HW timestamp Raslan Darawsheh
2017-10-05 23:11 ` Yongseok Koh
2017-10-03 11:00 ` [dpdk-dev] [PATCH v6 3/3] net/mlx5: " Raslan Darawsheh
2017-10-05 23:23 ` Yongseok Koh
2017-10-08 8:24 ` [dpdk-dev] [PATCH v7 1/3] ethdev: add Rx HW timestamp capability Raslan Darawsheh
2017-10-08 8:24 ` [dpdk-dev] [PATCH v7 2/3] app/testpmd: add Rx HW timestamp Raslan Darawsheh
2017-10-08 8:24 ` [dpdk-dev] [PATCH v7 3/3] net/mlx5: " Raslan Darawsheh
2017-10-09 19:17 ` Ferruh Yigit
2017-10-10 7:45 ` [dpdk-dev] [PATCH v8 1/3] ethdev: add Rx HW timestamp capability Raslan Darawsheh
2017-10-10 7:45 ` [dpdk-dev] [PATCH v8 2/3] app/testpmd: add Rx HW timestamp Raslan Darawsheh
2017-10-10 7:45 ` Raslan Darawsheh [this message]
2017-10-10 13:33 ` [dpdk-dev] [PATCH v8 1/3] ethdev: add Rx HW timestamp capability Yongseok Koh
2017-10-10 14:37 ` [dpdk-dev] [PATCH v9 " Raslan Darawsheh
2017-10-10 14:37 ` [dpdk-dev] [PATCH v9 2/3] app/testpmd: add Rx HW timestamp Raslan Darawsheh
2017-10-10 14:37 ` [dpdk-dev] [PATCH v9 3/3] net/mlx5: " Raslan Darawsheh
2017-10-10 14:40 ` Yongseok Koh
2017-10-11 1:14 ` [dpdk-dev] [PATCH v9 1/3] ethdev: add Rx HW timestamp capability Ferruh Yigit
2017-10-11 1:22 ` Yongseok Koh
2017-10-11 1:30 ` Ferruh Yigit
2017-10-04 5:57 ` [dpdk-dev] [PATCH v6 " Shahaf Shuler
2017-10-06 0:54 ` Ferruh Yigit
2017-10-02 14:01 ` [dpdk-dev] [PATCH " Raslan Darawsheh
2017-10-02 14:01 ` [dpdk-dev] [PATCH 2/3] app/testpmd: add Rx HW timestamp Raslan Darawsheh
2017-10-02 14:01 ` [dpdk-dev] [PATCH 3/3] net/mlx5: " Raslan Darawsheh
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