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HE1PR05MB1915; 6:oJmdrbYDnr/AYeRmgKThRU6ySM+rzvo2pzjMiBt0815C5VawcHsapooHdyB2wbKBhiXETI0ScWHDV/kXg3kOHxIm3knnTlctnE3VPs7Dglp+1muSea551xDFjr1vMTjB8OHBUtLe3ptv6hQxZOW4kkzZiWamm8J1DY3pyHkAHECJq6auqY6m2T9Sx88pT8aMdaYCb23LGBMCILbcbeLrfrTde5aHgXkTHqJ52P/L7np6L73uY7ntcB/Sa2bKcbMykccca9f15TokNsnpwU2m51draZ0sGuIuxj0vcqicd7lTxqfCazcfU2H1ITlhmwkSasHXMAFIkBW3+OQwJF0TAg==; 5:bpxlDrdgae20zvQyfJLUg5fAp7KZ2tFMy+9WpjIa+XpDYW/TFJKF1ZzNyHnz9iRRcaV6501Q8E7IZj4rmE5b+zr9M3KFGrSC9Dgbh4RYAhBExPDQJ1Wkr0ZImw9L4QQWEAI+Jg7YGRgslFGt7RdG0g==; 24:fVcdwbClOkfwUbVDL0rBEoKqOTEm2zGUwoS8Sdtn6kXuHMdFSCjqcUmDFs8GPt0X5zPMxpGw5gyu28QdfXRLvbLSrT1aBoQqhrIKwl1CE3U=; 7:cHCRwgOXCH1NrIyW/sytYslsP+W02JLex+VY6AkfrBOcp41BasejmAljaWN4mI9jRrOFYlwXyDKDOqU9Xfq0Qdid1ENM9r1zZfoOUVhxWh4+7owgRUqqv+TKCHjKShrd+2ZvBIUftECB0uOLlPFPdWQLFHtISIajPirFw9jhtkCy5h4OtxqxlcH3afcnMRic+e32RmoDM9H1yXOvULiGKtcUsuqJjbTKL8wLrb6ujtM= SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: Mellanox.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Oct 2017 13:12:28.2528 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 88a1b53e-fbcb-4af5-9149-08d51ae0e0dc X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: a652971c-7d2e-4d9b-a6a4-d149256f461b X-MS-Exchange-Transport-CrossTenantHeadersStamped: HE1PR05MB1915 Subject: [dpdk-dev] [PATCH v2] net/mlx4: fix no Rx interrupts X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 24 Oct 2017 13:12:31 -0000 This commit addresses the issue of rx interrupts support with the new Rx datapath introduced in DPDK version 17.11. In order to generate an Rx interrupt an event queue is armed with the consumer index of the Rx completion queue. Since version 17.11 this index is handled by the PMD so it is now the responsibility of the PMD to write this value when enabling Rx interrupts. Fixes: 6681b845034c ("net/mlx4: add Rx bypassing Verbs") Signed-off-by: Moti Haimovsky --- V2: * Rebased on top of ff3397e9 ("net/mlx4: relax Rx queue configuration order") --- drivers/net/mlx4/mlx4_intr.c | 38 +++++++++++++++++++++++++++++++++++++- drivers/net/mlx4/mlx4_prm.h | 9 +++++++++ drivers/net/mlx4/mlx4_rxq.c | 6 +++++- 3 files changed, 51 insertions(+), 2 deletions(-) diff --git a/drivers/net/mlx4/mlx4_intr.c b/drivers/net/mlx4/mlx4_intr.c index 3806322..217c591 100644 --- a/drivers/net/mlx4/mlx4_intr.c +++ b/drivers/net/mlx4/mlx4_intr.c @@ -53,6 +53,7 @@ #include #include #include +#include #include #include "mlx4.h" @@ -239,6 +240,40 @@ } /** + * MLX4 CQ notification . + * + * @param rxq + * Pointer to receive queue structure. + * @param solicited + * Is request solicited or not. + * + * @return + * Always 0. + */ +static int +mlx4_arm_cq(struct rxq *rxq, int solicited) +{ + struct mlx4_cq *cq = &rxq->mcq; + uint64_t doorbell; + uint32_t sn = cq->arm_sn & MLX4_CQ_DB_GEQ_N_MASK; + uint32_t ci = cq->cons_index & MLX4_CQ_DB_CI_MASK; + uint32_t cmd = solicited ? MLX4_CQ_DB_REQ_NOT_SOL : MLX4_CQ_DB_REQ_NOT; + void *cq_db_reg = (char *)cq->cq_uar + MLX4_CQ_DOORBELL; + + *cq->arm_db = rte_cpu_to_be_32(sn << 28 | cmd | ci); + /* + * Make sure that the doorbell record in host memory is + * written before ringing the doorbell via PCI MMIO. + */ + rte_wmb(); + doorbell = sn << 28 | cmd | cq->cqn; + doorbell <<= 32; + doorbell |= ci; + rte_write64(rte_cpu_to_be_64(doorbell), cq_db_reg); + return 0; +} + +/** * Uninstall interrupt handler. * * @param priv @@ -333,6 +368,7 @@ WARN("unable to disable interrupt on rx queue %d", idx); } else { + rxq->mcq.arm_sn++; ibv_ack_cq_events(rxq->cq, 1); } return -ret; @@ -358,7 +394,7 @@ if (!rxq || !rxq->channel) ret = EINVAL; else - ret = ibv_req_notify_cq(rxq->cq, 0); + ret = mlx4_arm_cq(rxq, 0); if (ret) { rte_errno = ret; WARN("unable to arm interrupt on rx queue %d", idx); diff --git a/drivers/net/mlx4/mlx4_prm.h b/drivers/net/mlx4/mlx4_prm.h index 3a77502..92f2fec 100644 --- a/drivers/net/mlx4/mlx4_prm.h +++ b/drivers/net/mlx4/mlx4_prm.h @@ -78,6 +78,11 @@ enum { MLX4_CQE_L2_TUNNEL_IPOK = (int)(1u << 31), }; +/* Completion queue events, numbers and masks. */ +#define MLX4_CQ_DB_GEQ_N_MASK 0x3 +#define MLX4_CQ_DB_CI_MASK 0xffffff +#define MLX4_CQ_DOORBELL 0x20 + /* Send queue information. */ struct mlx4_sq { uint8_t *buf; /**< SQ buffer. */ @@ -100,6 +105,10 @@ struct mlx4_cq { uint32_t cqe_64:1; /**< CQ entry size is 64 bytes. */ uint32_t cons_index; /**< Last queue entry that was handled. */ uint32_t *set_ci_db; /**< Pointer to the completion queue doorbell. */ + uint32_t *arm_db; /**< Pointer to doorbell for arming Rx events. */ + int arm_sn; /**< Rx event counter. */ + void *cq_uar; /**< CQ user access region. */ + uint32_t cqn; /**< CQ number. */ }; /** diff --git a/drivers/net/mlx4/mlx4_rxq.c b/drivers/net/mlx4/mlx4_rxq.c index 4c50077..24262cb 100644 --- a/drivers/net/mlx4/mlx4_rxq.c +++ b/drivers/net/mlx4/mlx4_rxq.c @@ -510,7 +510,7 @@ void mlx4_rss_detach(struct mlx4_rss *rss) struct rte_mbuf *(*elts)[elts_n] = rxq->elts; struct mlx4dv_obj mlxdv; struct mlx4dv_rwq dv_rwq; - struct mlx4dv_cq dv_cq; + struct mlx4dv_cq dv_cq = { .comp_mask = MLX4DV_CQ_MASK_UAR, }; const char *msg; struct ibv_cq *cq = NULL; struct ibv_wq *wq = NULL; @@ -604,6 +604,10 @@ void mlx4_rss_detach(struct mlx4_rss *rss) rxq->mcq.cqe_cnt = dv_cq.cqe_cnt; rxq->mcq.set_ci_db = dv_cq.set_ci_db; rxq->mcq.cqe_64 = (dv_cq.cqe_size & 64) ? 1 : 0; + rxq->mcq.arm_db = dv_cq.arm_db; + rxq->mcq.arm_sn = dv_cq.arm_sn; + rxq->mcq.cqn = dv_cq.cqn; + rxq->mcq.cq_uar = dv_cq.cq_uar; /* Update doorbell counter. */ rxq->rq_ci = elts_n / sges_n; rte_wmb(); -- 1.8.3.1