From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by dpdk.org (Postfix) with ESMTP id B31721B255 for ; Tue, 7 Nov 2017 01:14:44 +0100 (CET) Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga105.jf.intel.com with ESMTP; 06 Nov 2017 16:14:43 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.44,355,1505804400"; d="scan'208";a="172308781" Received: from ar11-dell-r730-21.jf.intel.com ([10.166.189.20]) by fmsmga005.fm.intel.com with ESMTP; 06 Nov 2017 16:14:43 -0800 From: Elza Mathew To: jasvinder.singh@intel.com Cc: dev@dpdk.org Date: Mon, 6 Nov 2017 10:05:43 -0800 Message-Id: <1509991543-26521-1-git-send-email-elza.mathew@intel.com> X-Mailer: git-send-email 1.9.1 Subject: [dpdk-dev] [PATCH 3/3] net: run-time function selection X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 07 Nov 2017 00:14:45 -0000 Compile-time function selection can potentially lead to lower performance on generic builds done by distros. Replaced compile time flag checks with run-time function selection. Signed-off-by: Elza Mathew --- lib/librte_net/rte_net_crc.c | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/lib/librte_net/rte_net_crc.c b/lib/librte_net/rte_net_crc.c index 661fe32..8f6a0e7 100644 --- a/lib/librte_net/rte_net_crc.c +++ b/lib/librte_net/rte_net_crc.c @@ -39,8 +39,8 @@ #include #include -#if defined(RTE_ARCH_X86_64) && defined(RTE_MACHINE_CPUFLAG_PCLMULQDQ) -#define X86_64_SSE42_PCLMULQDQ 1 +#ifdef RTE_ARCH_X86_64 +#include #elif defined(RTE_ARCH_ARM64) && defined(RTE_MACHINE_CPUFLAG_PMULL) #define ARM64_NEON_PMULL 1 #endif @@ -71,7 +71,7 @@ [RTE_NET_CRC32_ETH] = rte_crc32_eth_handler, }; -#ifdef X86_64_SSE42_PCLMULQDQ +#ifdef RTE_ARCH_X86_64 static rte_net_crc_handler handlers_sse42[] = { [RTE_NET_CRC16_CCITT] = rte_crc16_ccitt_sse42_handler, [RTE_NET_CRC32_ETH] = rte_crc32_eth_sse42_handler, @@ -169,10 +169,12 @@ rte_net_crc_set_alg(enum rte_net_crc_alg alg) { switch (alg) { -#ifdef X86_64_SSE42_PCLMULQDQ +#ifdef RTE_ARCH_X86_64 case RTE_NET_CRC_SSE42: - handlers = handlers_sse42; - break; + if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_PCLMULQDQ)) { + handlers = handlers_sse42; + break; + } #elif defined ARM64_NEON_PMULL /* fall-through */ case RTE_NET_CRC_NEON: @@ -212,9 +214,11 @@ static inline void __attribute__((constructor)) rte_net_crc_scalar_init(); -#ifdef X86_64_SSE42_PCLMULQDQ - alg = RTE_NET_CRC_SSE42; - rte_net_crc_sse42_init(); +#ifdef RTE_ARCH_X86_64 + if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_PCLMULQDQ)) { + alg = RTE_NET_CRC_SSE42; + rte_net_crc_sse42_init(); + } #elif defined ARM64_NEON_PMULL if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_PMULL)) { alg = RTE_NET_CRC_NEON; -- 1.9.1