From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dispatch1-us1.ppe-hosted.com (dispatch1-us1.ppe-hosted.com [67.231.154.164]) by dpdk.org (Postfix) with ESMTP id B72861B25A; Thu, 16 Nov 2017 09:05:01 +0100 (CET) Received: from pure.maildistiller.com (unknown [10.110.50.29]) by dispatch1-us1.ppe-hosted.com (Proofpoint Essentials ESMTP Server) with ESMTP id 56B822004D; Thu, 16 Nov 2017 08:05:01 +0000 (UTC) X-Virus-Scanned: Proofpoint Essentials engine Received: from mx1-us4.ppe-hosted.com (unknown [10.110.49.251]) by pure.maildistiller.com (Proofpoint Essentials ESMTP Server) with ESMTPS id D9B96220071; Thu, 16 Nov 2017 08:05:00 +0000 (UTC) Received: from webmail.solarflare.com (webmail.solarflare.com [12.187.104.26]) (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1-us4.ppe-hosted.com (Proofpoint Essentials ESMTP Server) with ESMTPS id D53F514005C; Thu, 16 Nov 2017 08:05:00 +0000 (UTC) Received: from ocex03.SolarFlarecom.com (10.20.40.36) by ocex03.SolarFlarecom.com (10.20.40.36) with Microsoft SMTP Server (TLS) id 15.0.1044.25; Thu, 16 Nov 2017 00:04:55 -0800 Received: from opal.uk.solarflarecom.com (10.17.10.1) by ocex03.SolarFlarecom.com (10.20.40.36) with Microsoft SMTP Server (TLS) id 15.0.1044.25 via Frontend Transport; Thu, 16 Nov 2017 00:04:55 -0800 Received: from uklogin.uk.solarflarecom.com (uklogin.uk.solarflarecom.com [10.17.10.10]) by opal.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id vAG84sEg016735; Thu, 16 Nov 2017 08:04:54 GMT Received: from uklogin.uk.solarflarecom.com (localhost.localdomain [127.0.0.1]) by uklogin.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id vAG84qu7006905; Thu, 16 Nov 2017 08:04:54 GMT From: Andrew Rybchenko To: CC: Vijay Srivastava , Date: Thu, 16 Nov 2017 08:04:22 +0000 Message-ID: <1510819481-6809-35-git-send-email-arybchenko@solarflare.com> X-Mailer: git-send-email 1.8.2.3 In-Reply-To: <1510819481-6809-1-git-send-email-arybchenko@solarflare.com> References: <1510819481-6809-1-git-send-email-arybchenko@solarflare.com> MIME-Version: 1.0 Content-Type: text/plain X-MDID: 1510819501-mI3Y2JVyehfr Subject: [dpdk-dev] [PATCH 34/53] net/sfc/base: fix build issue with PHY LED control enabled X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 16 Nov 2017 08:05:02 -0000 From: Vijay Srivastava Fixed build issue with the EFSYS_OPT_PHY_LED_CONTROL for Huntigton and Medford. Fixes: b1d06c75e32c ("net/sfc/base: import PHY LEDs control") Fixes: 0a7864349106 ("net/sfc/base: import PHY statistics") Cc: stable@dpdk.org Signed-off-by: Vijay Srivastava Signed-off-by: Andrew Rybchenko --- drivers/net/sfc/base/ef10_phy.c | 2 ++ drivers/net/sfc/base/efx_check.h | 4 ++-- drivers/net/sfc/base/siena_nic.c | 2 ++ drivers/net/sfc/base/siena_phy.c | 2 ++ 4 files changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/net/sfc/base/ef10_phy.c b/drivers/net/sfc/base/ef10_phy.c index 81309f2..ad40d51 100644 --- a/drivers/net/sfc/base/ef10_phy.c +++ b/drivers/net/sfc/base/ef10_phy.c @@ -280,7 +280,9 @@ ef10_phy_reconfigure( uint8_t payload[MAX(MC_CMD_SET_LINK_IN_LEN, MC_CMD_SET_LINK_OUT_LEN)]; uint32_t cap_mask; +#if EFSYS_OPT_PHY_LED_CONTROL unsigned int led_mode; +#endif unsigned int speed; boolean_t supported; efx_rc_t rc; diff --git a/drivers/net/sfc/base/efx_check.h b/drivers/net/sfc/base/efx_check.h index c8548c0..4ed7148 100644 --- a/drivers/net/sfc/base/efx_check.h +++ b/drivers/net/sfc/base/efx_check.h @@ -224,8 +224,8 @@ #if EFSYS_OPT_PHY_LED_CONTROL /* Support for PHY LED control */ -# if !EFSYS_OPT_SIENA -# error "PHY_LED_CONTROL requires SIENA" +# if !(EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) +# error "PHY_LED_CONTROL requires SIENA or HUNTINGTON or MEDFORD" # endif #endif /* EFSYS_OPT_PHY_LED_CONTROL */ diff --git a/drivers/net/sfc/base/siena_nic.c b/drivers/net/sfc/base/siena_nic.c index d574b24..5216cc6 100644 --- a/drivers/net/sfc/base/siena_nic.c +++ b/drivers/net/sfc/base/siena_nic.c @@ -190,7 +190,9 @@ static __checkReturn efx_rc_t siena_phy_cfg( __in efx_nic_t *enp) { +#if EFSYS_OPT_PHY_STATS efx_nic_cfg_t *encp = &(enp->en_nic_cfg); +#endif /* EFSYS_OPT_PHY_STATS */ efx_rc_t rc; /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */ diff --git a/drivers/net/sfc/base/siena_phy.c b/drivers/net/sfc/base/siena_phy.c index b90ccab..b1bd69f 100644 --- a/drivers/net/sfc/base/siena_phy.c +++ b/drivers/net/sfc/base/siena_phy.c @@ -273,7 +273,9 @@ siena_phy_reconfigure( MAX(MC_CMD_SET_LINK_IN_LEN, MC_CMD_SET_LINK_OUT_LEN))]; uint32_t cap_mask; +#if EFSYS_OPT_PHY_LED_CONTROL unsigned int led_mode; +#endif unsigned int speed; efx_rc_t rc; -- 2.7.4