From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by dpdk.org (Postfix) with ESMTP id 80A982BE1; Mon, 15 Jan 2018 11:08:20 +0100 (CET) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 15 Jan 2018 02:08:19 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.46,363,1511856000"; d="scan'208";a="195559230" Received: from dpdkx8602.sh.intel.com ([10.67.110.200]) by fmsmga006.fm.intel.com with ESMTP; 15 Jan 2018 02:08:18 -0800 From: Rosen Xu To: beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, stable@dpdk.org Date: Mon, 15 Jan 2018 18:05:55 +0800 Message-Id: <1516010755-136835-1-git-send-email-rosen.xu@intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1515740544-62985-1-git-send-email-rosen.xu@intel.com> References: <1515740544-62985-1-git-send-email-rosen.xu@intel.com> Subject: [dpdk-dev] [PATCH v2] net/i40e: fix issue of pctype doesn't take effect in X722 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 15 Jan 2018 10:08:21 -0000 Pctype should be setted after Port's MAC type setted, but in current code pctype is setted before Port's MAC type setted. Move pctype initialization after shared code initialization which initialize Port's MARC type. Fixes: a286ebeb0714 ("net/i40e: add dynamic mapping of SW flow types to HW pctypes") Cc: stable@dpdk.org Signed-off-by: Rosen Xu --- drivers/net/i40e/i40e_ethdev.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c index 7796e9e..9882701 100644 --- a/drivers/net/i40e/i40e_ethdev.c +++ b/drivers/net/i40e/i40e_ethdev.c @@ -1057,7 +1057,6 @@ static inline void i40e_GLQF_reg_init(struct i40e_hw *hw) return 0; } i40e_set_default_ptype_table(dev); - i40e_set_default_pctype_table(dev); pci_dev = RTE_ETH_DEV_TO_PCI(dev); intr_handle = &pci_dev->intr_handle; @@ -1103,6 +1102,8 @@ static inline void i40e_GLQF_reg_init(struct i40e_hw *hw) return ret; } + i40e_set_default_pctype_table(dev); + /* * To work around the NVM issue, initialize registers * for packet type of QinQ by software. -- 1.8.3.1