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* [dpdk-dev] [PATCH] net/i40e: add warning log during writing global register
@ 2018-01-17 15:08 Beilei Xing
  2018-01-29  9:53 ` [dpdk-dev] [PATCH v2 0/3] net/i40e: global configuration Beilei Xing
  0 siblings, 1 reply; 17+ messages in thread
From: Beilei Xing @ 2018-01-17 15:08 UTC (permalink / raw)
  To: qi.z.zhang, jingjing.wu; +Cc: dev

This patch adds warning log when writing global register,
and add limitation doc for impact during use of 700 series
NIC with both kernel driver and DPDK PMD.

Signed-off-by: Beilei Xing <beilei.xing@intel.com>
---
 doc/guides/nics/i40e.rst       | 12 ++++++++++++
 drivers/net/i40e/i40e_ethdev.c | 16 ++++++++++++++++
 drivers/net/i40e/i40e_ethdev.h | 39 +++++++++++++++++++++++++++++++++++++++
 drivers/net/i40e/i40e_fdir.c   |  1 +
 drivers/net/i40e/i40e_flow.c   |  1 +
 5 files changed, 69 insertions(+)

diff --git a/doc/guides/nics/i40e.rst b/doc/guides/nics/i40e.rst
index 50d5e36..61d144b 100644
--- a/doc/guides/nics/i40e.rst
+++ b/doc/guides/nics/i40e.rst
@@ -543,6 +543,18 @@ DCB function
 
 DCB works only when RSS is enabled.
 
+Global configuration warning
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+I40E PMD will set some global registers to enable some function or set some
+configure. Then when using different ports of the same NIC with Linux kernel
+and DPDK, the port with Linux kernel will be impacted by the port with DPDK.
+For example, register I40E_GL_SWT_L2TAGCTRL is used to control L2 tag, i40e
+PMD uses I40E_GL_SWT_L2TAGCTRL to set vlan TPID. If setting TPID in port A
+with DPDK, then the configuration will also impact port B in the NIC with
+kernel driver, which don't want to use the TPID.
+So PMD reports warning to clarify what is changed by writing global register.
+
 High Performance of Small Packets on 40G NIC
 --------------------------------------------
 
diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c
index 9626c6a..3907dfa 100644
--- a/drivers/net/i40e/i40e_ethdev.c
+++ b/drivers/net/i40e/i40e_ethdev.c
@@ -680,6 +680,7 @@ static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 	 */
 	I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 	I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
+	i40e_global_cfg_warning(I40E_WARNING_QINQ_PARSER);
 }
 
 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
@@ -1133,6 +1134,7 @@ eth_i40e_dev_init(struct rte_eth_dev *dev)
 				   0x00000028,	NULL);
 	if (ret)
 		PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d", ret);
+	i40e_global_cfg_warning(I40E_WARNING_QINQ_CLOUD_FILTER);
 
 	/* Need the special FW version to support floating VEB */
 	config_floating_veb(dev);
@@ -1413,6 +1415,7 @@ void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
 	I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
 	I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
 	I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
+	i40e_global_cfg_warning(I40E_WARNING_DIS_FLX_PLD);
 }
 
 static int
@@ -3260,6 +3263,7 @@ i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 		/* If NVM API < 1.7, keep the register setting */
 		ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
 						      tpid, qinq);
+	i40e_global_cfg_warning(I40E_WARNING_TPID);
 
 	return ret;
 }
@@ -3502,6 +3506,7 @@ i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
 	I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
 		       pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
 		       << I40E_KILOSHIFT);
+	i40e_global_cfg_warning(I40E_WARNING_FLOW_CTL);
 
 	I40E_WRITE_FLUSH(hw);
 
@@ -7981,6 +7986,7 @@ i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
 						   reg, NULL);
 		if (ret != 0)
 			return ret;
+		i40e_global_cfg_warning(I40E_WARNING_GRE_KEY_LEN);
 	} else {
 		ret = 0;
 	}
@@ -8239,6 +8245,8 @@ i40e_set_hash_filter_global_config(struct i40e_hw *hw,
 					i40e_write_rx_ctl(hw,
 							  I40E_GLQF_HSYM(j),
 							  reg);
+				i40e_global_cfg_warning(
+					I40E_WARNING_HSYM);
 			}
 		}
 	}
@@ -8265,6 +8273,7 @@ i40e_set_hash_filter_global_config(struct i40e_hw *hw,
 		goto out;
 
 	i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
+	i40e_global_cfg_warning(I40E_WARNING_QF_CTL);
 
 out:
 	I40E_WRITE_FLUSH(hw);
@@ -8909,6 +8918,10 @@ i40e_filter_input_set_init(struct i40e_pf *pf)
 		pf->hash_input_set[pctype] = input_set;
 		pf->fdir.input_set[pctype] = input_set;
 	}
+
+	i40e_global_cfg_warning(I40E_WARNING_HASH_INSET);
+	i40e_global_cfg_warning(I40E_WARNING_FD_MSK);
+	i40e_global_cfg_warning(I40E_WARNING_HASH_MSK);
 }
 
 int
@@ -8969,6 +8982,7 @@ i40e_hash_filter_inset_select(struct i40e_hw *hw,
 	i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
 			     (uint32_t)((inset_reg >>
 			     I40E_32_BIT_WIDTH) & UINT32_MAX));
+	i40e_global_cfg_warning(I40E_WARNING_HASH_INSET);
 
 	for (i = 0; i < num; i++)
 		i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
@@ -8977,6 +8991,7 @@ i40e_hash_filter_inset_select(struct i40e_hw *hw,
 	for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
 		i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
 				     0);
+	i40e_global_cfg_warning(I40E_WARNING_HASH_MSK);
 	I40E_WRITE_FLUSH(hw);
 
 	pf->hash_input_set[pctype] = input_set;
@@ -9050,6 +9065,7 @@ i40e_fdir_filter_inset_select(struct i40e_pf *pf,
 	for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
 		i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
 				     0);
+	i40e_global_cfg_warning(I40E_WARNING_FD_MSK);
 	I40E_WRITE_FLUSH(hw);
 
 	pf->fdir.input_set[pctype] = input_set;
diff --git a/drivers/net/i40e/i40e_ethdev.h b/drivers/net/i40e/i40e_ethdev.h
index 69ea6c1..98f5430 100644
--- a/drivers/net/i40e/i40e_ethdev.h
+++ b/drivers/net/i40e/i40e_ethdev.h
@@ -1069,6 +1069,21 @@ struct i40e_valid_pattern {
 	parse_filter_t parse_filter;
 };
 
+enum I40E_WARNING_IDX {
+	I40E_WARNING_DIS_FLX_PLD,
+	I40E_WARNING_ENA_FLX_PLD,
+	I40E_WARNING_QINQ_PARSER,
+	I40E_WARNING_QINQ_CLOUD_FILTER,
+	I40E_WARNING_TPID,
+	I40E_WARNING_FLOW_CTL,
+	I40E_WARNING_GRE_KEY_LEN,
+	I40E_WARNING_QF_CTL,
+	I40E_WARNING_HASH_INSET,
+	I40E_WARNING_HSYM,
+	I40E_WARNING_HASH_MSK,
+	I40E_WARNING_FD_MSK,
+};
+
 int i40e_dev_switch_queues(struct i40e_pf *pf, bool on);
 int i40e_vsi_release(struct i40e_vsi *vsi);
 struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf,
@@ -1277,6 +1292,30 @@ i40e_calc_itr_interval(int16_t interval, bool is_pf)
 	return interval / 2;
 }
 
+static inline void
+i40e_global_cfg_warning(enum I40E_WARNING_IDX idx)
+{
+	const char *warning;
+	static const char *const warning_list[] = {
+		[I40E_WARNING_DIS_FLX_PLD] = "disable FDIR flexible payload",
+		[I40E_WARNING_ENA_FLX_PLD] = "enable FDIR flexible payload",
+		[I40E_WARNING_QINQ_PARSER] = "support QinQ parser",
+		[I40E_WARNING_QINQ_CLOUD_FILTER] = "support QinQ cloud filter",
+		[I40E_WARNING_TPID] = "support TPID configuration",
+		[I40E_WARNING_FLOW_CTL] = "configure water marker",
+		[I40E_WARNING_GRE_KEY_LEN] = "support GRE key length setting",
+		[I40E_WARNING_QF_CTL] = "support hash function setting",
+		[I40E_WARNING_HASH_INSET] = "configure hash input set",
+		[I40E_WARNING_HSYM] = "set symmetric hash",
+		[I40E_WARNING_HASH_MSK] = "configure hash mask",
+		[I40E_WARNING_FD_MSK] = "configure fdir mask",
+	};
+
+	warning = warning_list[idx];
+
+	PMD_DRV_LOG(WARNING, "Global register is changed during %s", warning);
+}
+
 #define I40E_VALID_FLOW(flow_type) \
 	((flow_type) == RTE_ETH_FLOW_FRAG_IPV4 || \
 	(flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_TCP || \
diff --git a/drivers/net/i40e/i40e_fdir.c b/drivers/net/i40e/i40e_fdir.c
index 906c204..41c2382 100644
--- a/drivers/net/i40e/i40e_fdir.c
+++ b/drivers/net/i40e/i40e_fdir.c
@@ -527,6 +527,7 @@ i40e_set_flx_pld_cfg(struct i40e_pf *pf,
 			  (num << I40E_GLQF_ORT_FIELD_CNT_SHIFT) |
 			  (layer_idx * I40E_MAX_FLXPLD_FIED);
 		I40E_WRITE_REG(hw, I40E_GLQF_ORT(33 + layer_idx), flx_ort);
+		i40e_global_cfg_warning(I40E_WARNING_ENA_FLX_PLD);
 	}
 
 	for (i = 0; i < num; i++) {
diff --git a/drivers/net/i40e/i40e_flow.c b/drivers/net/i40e/i40e_flow.c
index cd9a9b6..2f2b6a9 100644
--- a/drivers/net/i40e/i40e_flow.c
+++ b/drivers/net/i40e/i40e_flow.c
@@ -2260,6 +2260,7 @@ i40e_flow_set_fdir_flex_pit(struct i40e_pf *pf,
 			  (raw_id << I40E_GLQF_ORT_FIELD_CNT_SHIFT) |
 			  (layer_idx * I40E_MAX_FLXPLD_FIED);
 		I40E_WRITE_REG(hw, I40E_GLQF_ORT(33 + layer_idx), flx_ort);
+		i40e_global_cfg_warning(I40E_WARNING_ENA_FLX_PLD);
 	}
 
 	/* Set flex pit */
-- 
2.5.5

^ permalink raw reply	[flat|nested] 17+ messages in thread

end of thread, other threads:[~2018-02-02 13:00 UTC | newest]

Thread overview: 17+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-01-17 15:08 [dpdk-dev] [PATCH] net/i40e: add warning log during writing global register Beilei Xing
2018-01-29  9:53 ` [dpdk-dev] [PATCH v2 0/3] net/i40e: global configuration Beilei Xing
2018-01-29  9:53   ` [dpdk-dev] [PATCH v2 1/3] net/i40e: add warning log for " Beilei Xing
2018-01-29  9:53   ` [dpdk-dev] [PATCH v2 2/3] net/i40e: add debug " Beilei Xing
2018-01-29  9:53   ` [dpdk-dev] [PATCH v2 3/3] net/i40e: add device args to disable " Beilei Xing
2018-01-30  2:23   ` [dpdk-dev] [PATCH v2 0/3] net/i40e: " Zhang, Helin
2018-02-01 11:49   ` [dpdk-dev] [PATCH v3 0/3] net/i40e: fix multiple driver support issue Beilei Xing
2018-02-01 11:49     ` [dpdk-dev] [PATCH v3 1/3] net/i40e: add warnings when writing global registers Beilei Xing
2018-02-01 11:49     ` [dpdk-dev] [PATCH v3 2/3] net/i40e: add debug logs " Beilei Xing
2018-02-01 11:49     ` [dpdk-dev] [PATCH v3 3/3] net/i40e: fix multiple driver support issue Beilei Xing
2018-02-02 12:05     ` [dpdk-dev] [PATCH v4 0/4] " Beilei Xing
2018-02-02 12:05       ` [dpdk-dev] [PATCH v4 1/4] net/i40e: add warnings when writing global registers Beilei Xing
2018-02-02 12:05       ` [dpdk-dev] [PATCH v4 2/4] net/i40e: add debug logs " Beilei Xing
2018-02-02 12:05       ` [dpdk-dev] [PATCH v4 3/4] net/i40e: fix multiple driver support issue Beilei Xing
2018-02-02 12:05       ` [dpdk-dev] [PATCH v4 4/4] net/i40e: fix interrupt conflict when using multi-driver Beilei Xing
2018-02-02 12:42       ` [dpdk-dev] [PATCH v4 0/4] net/i40e: fix multiple driver support issue Wu, Jingjing
2018-02-02 13:00         ` Zhang, Helin

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