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The changes consist of FW bug fixes and enhancements. Signed-off-by: Rasesh Mody --- drivers/net/qede/base/common_hsi.h | 8 +- drivers/net/qede/base/ecore_cxt.c | 10 +- drivers/net/qede/base/ecore_cxt.h | 4 +- drivers/net/qede/base/ecore_dev.c | 10 +- drivers/net/qede/base/ecore_hsi_common.h | 19 +- drivers/net/qede/base/ecore_hsi_debug_tools.h | 3 +- drivers/net/qede/base/ecore_hsi_eth.h | 23 +- drivers/net/qede/base/ecore_hsi_init_func.h | 3 + drivers/net/qede/base/ecore_init_fw_funcs.c | 210 +++++++-- drivers/net/qede/base/ecore_init_fw_funcs.h | 33 +- drivers/net/qede/base/ecore_iro_values.h | 64 +-- drivers/net/qede/base/ecore_l2.c | 2 +- drivers/net/qede/base/ecore_rt_defs.h | 588 +++++++++++++------------ drivers/net/qede/base/eth_common.h | 3 + drivers/net/qede/base/reg_addr.h | 2 + drivers/net/qede/qede_main.c | 2 +- 16 files changed, 585 insertions(+), 399 deletions(-) diff --git a/drivers/net/qede/base/common_hsi.h b/drivers/net/qede/base/common_hsi.h index 9a6059a..d37dc7c 100644 --- a/drivers/net/qede/base/common_hsi.h +++ b/drivers/net/qede/base/common_hsi.h @@ -96,10 +96,10 @@ /****************************************************************************/ -#define FW_MAJOR_VERSION 8 -#define FW_MINOR_VERSION 30 -#define FW_REVISION_VERSION 12 -#define FW_ENGINEERING_VERSION 0 +#define FW_MAJOR_VERSION 8 +#define FW_MINOR_VERSION 33 +#define FW_REVISION_VERSION 12 +#define FW_ENGINEERING_VERSION 0 /***********************/ /* COMMON HW CONSTANTS */ diff --git a/drivers/net/qede/base/ecore_cxt.c b/drivers/net/qede/base/ecore_cxt.c index 50bd66d..ca7c55f 100644 --- a/drivers/net/qede/base/ecore_cxt.c +++ b/drivers/net/qede/base/ecore_cxt.c @@ -1427,7 +1427,8 @@ static void ecore_cdu_init_pf(struct ecore_hwfn *p_hwfn) } } -void ecore_qm_init_pf(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt) +void ecore_qm_init_pf(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, + bool is_pf_loading) { struct ecore_qm_info *qm_info = &p_hwfn->qm_info; struct ecore_mcp_link_state *p_link; @@ -1438,8 +1439,9 @@ void ecore_qm_init_pf(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt) p_link = &ECORE_LEADING_HWFN(p_hwfn->p_dev)->mcp_info->link_output; - ecore_qm_pf_rt_init(p_hwfn, p_ptt, p_hwfn->port_id, - p_hwfn->rel_pf_id, qm_info->max_phys_tcs_per_port, + ecore_qm_pf_rt_init(p_hwfn, p_ptt, p_hwfn->rel_pf_id, + qm_info->max_phys_tcs_per_port, + is_pf_loading, iids.cids, iids.vf_cids, iids.tids, qm_info->start_pq, qm_info->num_pqs - qm_info->num_vf_pqs, @@ -1797,7 +1799,7 @@ void ecore_cxt_hw_init_common(struct ecore_hwfn *p_hwfn) void ecore_cxt_hw_init_pf(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt) { - ecore_qm_init_pf(p_hwfn, p_ptt); + ecore_qm_init_pf(p_hwfn, p_ptt, true); ecore_cm_init_pf(p_hwfn); ecore_dq_init_pf(p_hwfn); ecore_cdu_init_pf(p_hwfn); diff --git a/drivers/net/qede/base/ecore_cxt.h b/drivers/net/qede/base/ecore_cxt.h index 54761e4..1130a33 100644 --- a/drivers/net/qede/base/ecore_cxt.h +++ b/drivers/net/qede/base/ecore_cxt.h @@ -107,8 +107,10 @@ u32 ecore_cxt_get_proto_cid_start(struct ecore_hwfn *p_hwfn, * * @param p_hwfn * @param p_ptt + * @param is_pf_loading */ -void ecore_qm_init_pf(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt); +void ecore_qm_init_pf(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, + bool is_pf_loading); /** * @brief Reconfigures QM pf on the fly diff --git a/drivers/net/qede/base/ecore_dev.c b/drivers/net/qede/base/ecore_dev.c index 38492e6..a3269f4 100644 --- a/drivers/net/qede/base/ecore_dev.c +++ b/drivers/net/qede/base/ecore_dev.c @@ -721,6 +721,7 @@ static void ecore_init_qm_pq(struct ecore_hwfn *p_hwfn, "pq overflow! pq %d, max pq %d\n", pq_idx, max_pq); /* init pq params */ + qm_info->qm_pq_params[pq_idx].port_id = p_hwfn->port_id; qm_info->qm_pq_params[pq_idx].vport_id = qm_info->start_vport + qm_info->num_vports; qm_info->qm_pq_params[pq_idx].tc_id = tc; @@ -1025,10 +1026,9 @@ static void ecore_dp_init_qm_params(struct ecore_hwfn *p_hwfn) for (i = 0; i < qm_info->num_pqs; i++) { pq = &qm_info->qm_pq_params[i]; DP_VERBOSE(p_hwfn, ECORE_MSG_HW, - "pq idx %d, vport_id %d, tc %d, wrr_grp %d," - " rl_valid %d\n", - qm_info->start_pq + i, pq->vport_id, pq->tc_id, - pq->wrr_group, pq->rl_valid); + "pq idx %d, port %d, vport_id %d, tc %d, wrr_grp %d, rl_valid %d\n", + qm_info->start_pq + i, pq->port_id, pq->vport_id, + pq->tc_id, pq->wrr_group, pq->rl_valid); } } @@ -1083,7 +1083,7 @@ enum _ecore_status_t ecore_qm_reconf(struct ecore_hwfn *p_hwfn, ecore_init_clear_rt_data(p_hwfn); /* prepare QM portion of runtime array */ - ecore_qm_init_pf(p_hwfn, p_ptt); + ecore_qm_init_pf(p_hwfn, p_ptt, false); /* activate init tool on runtime array */ rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id, diff --git a/drivers/net/qede/base/ecore_hsi_common.h b/drivers/net/qede/base/ecore_hsi_common.h index d8abd60..38ac507 100644 --- a/drivers/net/qede/base/ecore_hsi_common.h +++ b/drivers/net/qede/base/ecore_hsi_common.h @@ -381,7 +381,7 @@ struct e4_xstorm_core_conn_ag_ctx { __le16 reserved16 /* physical_q2 */; __le16 tx_bd_cons /* word3 */; __le16 tx_bd_or_spq_prod /* word4 */; - __le16 word5 /* word5 */; + __le16 updated_qm_pq_id /* word5 */; __le16 conn_dpi /* conn_dpi */; u8 byte3 /* byte3 */; u8 byte4 /* byte4 */; @@ -904,8 +904,10 @@ struct core_rx_start_ramrod_data { /* if set, 802.1q tags will be removed and copied to CQE */ /* if set, 802.1q tags will be removed and copied to CQE */ u8 inner_vlan_stripping_en; -/* if set, outer tag wont be stripped, valid only in MF OVLAN. */ - u8 outer_vlan_stripping_dis; +/* if set and inner vlan does not exist, the outer vlan will copied to CQE as + * inner vlan. should be used in MF_OVLAN mode only. + */ + u8 report_outer_vlan; u8 queue_id /* Light L2 RX Queue ID */; u8 main_func_queue /* Is this the main queue for the PF */; /* Duplicate broadcast packets to LL2 main queue in mf_si mode. Valid if @@ -1294,7 +1296,10 @@ enum gft_profile_type { GFT_PROFILE_TYPE_4_TUPLE /* 4 tuple, IP type and L4 type match. */, /* L4 destination port, IP type and L4 type match. */ GFT_PROFILE_TYPE_L4_DST_PORT, - GFT_PROFILE_TYPE_IP_DST_PORT /* IP destination port and IP type. */, + GFT_PROFILE_TYPE_IP_DST_ADDR /* IP destination port and IP type. */, +/* tunnel type, inner IP source address and IP type match. */ + GFT_PROFILE_TYPE_IP_SRC_ADDR, + GFT_PROFILE_TYPE_TUNNEL_TYPE /* tunnel type and outer IP type match. */, MAX_GFT_PROFILE_TYPE }; @@ -1515,7 +1520,10 @@ struct protocol_dcb_data { u8 dcb_priority /* dcbPri flag value */; u8 dcb_tc /* dcb TC value */; u8 dscp_val /* dscp value to write if dscp_enable_flag is set */; - u8 reserved0; +/* When DCB is enabled - if this flag is set, dont add VLAN 0 tag to untagged + * frames + */ + u8 dcb_dont_add_vlan0; }; /* @@ -1739,6 +1747,7 @@ struct tstorm_per_port_stat { struct regpair eth_vxlan_tunn_filter_discard; /* GENEVE dropped packets */ struct regpair eth_geneve_tunn_filter_discard; + struct regpair eth_gft_drop_pkt /* GFT dropped packets */; }; diff --git a/drivers/net/qede/base/ecore_hsi_debug_tools.h b/drivers/net/qede/base/ecore_hsi_debug_tools.h index ebb6648..8a14451 100644 --- a/drivers/net/qede/base/ecore_hsi_debug_tools.h +++ b/drivers/net/qede/base/ecore_hsi_debug_tools.h @@ -960,7 +960,8 @@ enum dbg_grc_params { DBG_GRC_PARAM_DUMP_CAU /* dump CAU memories (0/1) */, DBG_GRC_PARAM_DUMP_QM /* dump QM memories (0/1) */, DBG_GRC_PARAM_DUMP_MCP /* dump MCP memories (0/1) */, - DBG_GRC_PARAM_RESERVED /* reserved */, +/* MCP Trace meta data size in bytes */ + DBG_GRC_PARAM_MCP_TRACE_META_SIZE, DBG_GRC_PARAM_DUMP_CFC /* dump CFC memories (0/1) */, DBG_GRC_PARAM_DUMP_IGU /* dump IGU memories (0/1) */, DBG_GRC_PARAM_DUMP_BRB /* dump BRB memories (0/1) */, diff --git a/drivers/net/qede/base/ecore_hsi_eth.h b/drivers/net/qede/base/ecore_hsi_eth.h index ffbf5c7..5d5a521 100644 --- a/drivers/net/qede/base/ecore_hsi_eth.h +++ b/drivers/net/qede/base/ecore_hsi_eth.h @@ -346,7 +346,7 @@ struct e4_xstorm_eth_conn_ag_ctx { __le16 edpm_num_bds /* physical_q2 */; __le16 tx_bd_cons /* word3 */; __le16 tx_bd_prod /* word4 */; - __le16 tx_class /* word5 */; + __le16 updated_qm_pq_id /* word5 */; __le16 conn_dpi /* conn_dpi */; u8 byte3 /* byte3 */; u8 byte4 /* byte4 */; @@ -1034,7 +1034,6 @@ struct eth_vport_rx_mode { #define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_SHIFT 5 #define ETH_VPORT_RX_MODE_RESERVED1_MASK 0x3FF #define ETH_VPORT_RX_MODE_RESERVED1_SHIFT 6 - __le16 reserved2[3]; }; @@ -1089,7 +1088,6 @@ struct eth_vport_tx_mode { #define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_SHIFT 4 #define ETH_VPORT_TX_MODE_RESERVED1_MASK 0x7FF #define ETH_VPORT_TX_MODE_RESERVED1_SHIFT 5 - __le16 reserved2[3]; }; @@ -1216,7 +1214,9 @@ struct rx_queue_update_ramrod_data { u8 complete_cqe_flg /* post completion to the CQE ring if set */; u8 complete_event_flg /* post completion to the event ring if set */; u8 vport_id /* ID of virtual port */; - u8 reserved[4]; +/* If set, update default rss queue to this RX queue. */ + u8 set_default_rss_queue; + u8 reserved[3]; u8 reserved1 /* FW reserved. */; u8 reserved2 /* FW reserved. */; u8 reserved3 /* FW reserved. */; @@ -1257,7 +1257,8 @@ struct rx_update_gft_filter_data { __le16 action_icid; __le16 rx_qid /* RX queue ID. Valid if rx_qid_valid set. */; __le16 flow_id /* RX flow ID. Valid if flow_id_valid set. */; - u8 vport_id /* RX vport Id. */; +/* RX vport Id. For drop flow, set to ETH_GFT_TRASHCAN_VPORT. */ + __le16 vport_id; /* If set, action_icid will used for GFT filter update. */ u8 action_icid_valid; /* If set, rx_qid will used for traffic steering, in additional to vport_id. @@ -1273,7 +1274,10 @@ struct rx_update_gft_filter_data { * case of error. */ u8 assert_on_error; - u8 reserved[2]; +/* If set, inner VLAN will be removed regardless to VPORT configuration. + * Supported by E4 only. + */ + u8 inner_vlan_removal_en; }; @@ -1403,7 +1407,7 @@ struct vport_start_ramrod_data { u8 ctl_frame_mac_check_en; /* If set, control frames will be filtered according to ethtype check. */ u8 ctl_frame_ethtype_check_en; - u8 reserved[5]; + u8 reserved[1]; }; @@ -1486,6 +1490,7 @@ struct vport_update_ramrod_data { struct vport_update_ramrod_data_cmn common; struct eth_vport_rx_mode rx_mode /* vport rx mode bitmap */; struct eth_vport_tx_mode tx_mode /* vport tx mode bitmap */; + __le32 reserved[3]; /* TPA configuration parameters */ struct eth_vport_tpa_param tpa_param; struct vport_update_ramrod_mcast approx_mcast; @@ -1809,7 +1814,7 @@ struct E4XstormEthConnAgCtxDqExtLdPart { __le16 edpm_num_bds /* physical_q2 */; __le16 tx_bd_cons /* word3 */; __le16 tx_bd_prod /* word4 */; - __le16 tx_class /* word5 */; + __le16 updated_qm_pq_id /* word5 */; __le16 conn_dpi /* conn_dpi */; u8 byte3 /* byte3 */; u8 byte4 /* byte4 */; @@ -2153,7 +2158,7 @@ struct e4_xstorm_eth_hw_conn_ag_ctx { __le16 edpm_num_bds /* physical_q2 */; __le16 tx_bd_cons /* word3 */; __le16 tx_bd_prod /* word4 */; - __le16 tx_class /* word5 */; + __le16 updated_qm_pq_id /* word5 */; __le16 conn_dpi /* conn_dpi */; }; diff --git a/drivers/net/qede/base/ecore_hsi_init_func.h b/drivers/net/qede/base/ecore_hsi_init_func.h index 48b0048..8421d16 100644 --- a/drivers/net/qede/base/ecore_hsi_init_func.h +++ b/drivers/net/qede/base/ecore_hsi_init_func.h @@ -114,6 +114,9 @@ struct init_qm_pq_params { u8 wrr_group /* WRR group */; /* Indicates if a rate limiter should be allocated for the PQ (0/1) */ u8 rl_valid; + u8 port_id /* Port ID */; + u8 reserved0; + u16 reserved1; }; diff --git a/drivers/net/qede/base/ecore_init_fw_funcs.c b/drivers/net/qede/base/ecore_init_fw_funcs.c index 1da80a6..8d73a5e 100644 --- a/drivers/net/qede/base/ecore_init_fw_funcs.c +++ b/drivers/net/qede/base/ecore_init_fw_funcs.c @@ -76,12 +76,12 @@ #define QM_RL_PERIOD_CLK_25M (25 * QM_RL_PERIOD) /* RL increment value - rate is specified in mbps. the factor of 1.01 was -* added after seeing only 99% factor reached in a 25Gbps port with DPDK RFC -* 2544 test. In this scenario the PF RL was reducing the line rate to 99% -* although the credit increment value was the correct one and FW calculated -* correct packet sizes. The reason for the inaccuracy of the RL is unknown at -* this point. -*/ + * added after seeing only 99% factor reached in a 25Gbps port with DPDK RFC + * 2544 test. In this scenario the PF RL was reducing the line rate to 99% + * although the credit increment value was the correct one and FW calculated + * correct packet sizes. The reason for the inaccuracy of the RL is unknown at + * this point. + */ #define QM_RL_INC_VAL(rate) \ OSAL_MAX_T(u32, (u32)(((rate ? rate : 100000) * QM_RL_PERIOD * 101) / \ (8 * 100)), 1) @@ -182,7 +182,7 @@ (((vp) << 0) | ((pf) << 12) | ((tc) << 16) | \ ((port) << 20) | ((rl_valid) << 22) | ((rl) << 24)) #define PQ_INFO_RAM_GRC_ADDRESS(pq_id) \ - (XSEM_REG_FAST_MEMORY + SEM_FAST_REG_INT_RAM + 21768 + (pq_id) * 4) + (XSEM_REG_FAST_MEMORY + SEM_FAST_REG_INT_RAM + 21776 + (pq_id) * 4) /******************** INTERNAL IMPLEMENTATION *********************/ @@ -421,9 +421,9 @@ static void ecore_btb_blocks_rt_init(struct ecore_hwfn *p_hwfn, /* Prepare Tx PQ mapping runtime init values for the specified PF */ static void ecore_tx_pq_map_rt_init(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, - u8 port_id, u8 pf_id, u8 max_phys_tcs_per_port, + bool is_pf_loading, u32 num_pf_cids, u32 num_vf_cids, u16 start_pq, @@ -437,7 +437,7 @@ static void ecore_tx_pq_map_rt_init(struct ecore_hwfn *p_hwfn, /* A bit per Tx PQ indicating if the PQ is associated with a VF */ u32 tx_pq_vf_mask[MAX_QM_TX_QUEUES / QM_PF_QUEUE_GROUP_SIZE] = { 0 }; u32 num_tx_pq_vf_masks = MAX_QM_TX_QUEUES / QM_PF_QUEUE_GROUP_SIZE; - u16 num_pqs, first_pq_group, last_pq_group, i, pq_id, pq_group; + u16 num_pqs, first_pq_group, last_pq_group, i, j, pq_id, pq_group; u32 pq_mem_4kb, vport_pq_mem_4kb, mem_addr_4kb; num_pqs = num_pf_pqs + num_vf_pqs; @@ -467,11 +467,11 @@ static void ecore_tx_pq_map_rt_init(struct ecore_hwfn *p_hwfn, bool is_vf_pq, rl_valid; u16 first_tx_pq_id; - ext_voq = ecore_get_ext_voq(p_hwfn, port_id, pq_params[i].tc_id, + ext_voq = ecore_get_ext_voq(p_hwfn, pq_params[i].port_id, + pq_params[i].tc_id, max_phys_tcs_per_port); is_vf_pq = (i >= num_pf_pqs); - rl_valid = pq_params[i].rl_valid && pq_params[i].vport_id < - max_qm_global_rls; + rl_valid = pq_params[i].rl_valid > 0; /* Update first Tx PQ of VPORT/TC */ vport_id_in_pf = pq_params[i].vport_id - start_vport; @@ -492,28 +492,38 @@ static void ecore_tx_pq_map_rt_init(struct ecore_hwfn *p_hwfn, } /* Check RL ID */ - if (pq_params[i].rl_valid && pq_params[i].vport_id >= - max_qm_global_rls) + if (rl_valid && pq_params[i].vport_id >= max_qm_global_rls) { DP_NOTICE(p_hwfn, true, "Invalid VPORT ID for rate limiter config\n"); + rl_valid = false; + } /* Prepare PQ map entry */ struct qm_rf_pq_map_e4 tx_pq_map; + QM_INIT_TX_PQ_MAP(p_hwfn, tx_pq_map, E4, pq_id, rl_valid ? 1 : 0, first_tx_pq_id, rl_valid ? pq_params[i].vport_id : 0, ext_voq, pq_params[i].wrr_group); - /* Set base address */ + /* Set PQ base address */ STORE_RT_REG(p_hwfn, QM_REG_BASEADDRTXPQ_RT_OFFSET + pq_id, mem_addr_4kb); + /* Clear PQ pointer table entry (64 bit) */ + if (is_pf_loading) + for (j = 0; j < 2; j++) + STORE_RT_REG(p_hwfn, QM_REG_PTRTBLTX_RT_OFFSET + + (pq_id * 2) + j, 0); + /* Write PQ info to RAM */ if (WRITE_PQ_INFO_TO_RAM != 0) { u32 pq_info = 0; + pq_info = PQ_INFO_ELEMENT(first_tx_pq_id, pf_id, - pq_params[i].tc_id, port_id, + pq_params[i].tc_id, + pq_params[i].port_id, rl_valid ? 1 : 0, rl_valid ? pq_params[i].vport_id : 0); ecore_wr(p_hwfn, p_ptt, PQ_INFO_RAM_GRC_ADDRESS(pq_id), @@ -540,12 +550,13 @@ static void ecore_tx_pq_map_rt_init(struct ecore_hwfn *p_hwfn, /* Prepare Other PQ mapping runtime init values for the specified PF */ static void ecore_other_pq_map_rt_init(struct ecore_hwfn *p_hwfn, u8 pf_id, + bool is_pf_loading, u32 num_pf_cids, u32 num_tids, u32 base_mem_addr_4kb) { u32 pq_size, pq_mem_4kb, mem_addr_4kb; - u16 i, pq_id, pq_group; + u16 i, j, pq_id, pq_group; /* A single other PQ group is used in each PF, where PQ group i is used * in PF i. @@ -563,11 +574,19 @@ static void ecore_other_pq_map_rt_init(struct ecore_hwfn *p_hwfn, STORE_RT_REG(p_hwfn, QM_REG_MAXPQSIZE_2_RT_OFFSET, QM_PQ_SIZE_256B(pq_size)); - /* Set base address */ for (i = 0, pq_id = pf_id * QM_PF_QUEUE_GROUP_SIZE; i < QM_OTHER_PQS_PER_PF; i++, pq_id++) { + /* Set PQ base address */ STORE_RT_REG(p_hwfn, QM_REG_BASEADDROTHERPQ_RT_OFFSET + pq_id, mem_addr_4kb); + + /* Clear PQ pointer table entry */ + if (is_pf_loading) + for (j = 0; j < 2; j++) + STORE_RT_REG(p_hwfn, + QM_REG_PTRTBLOTHER_RT_OFFSET + + (pq_id * 2) + j, 0); + mem_addr_4kb += pq_mem_4kb; } } @@ -576,7 +595,6 @@ static void ecore_other_pq_map_rt_init(struct ecore_hwfn *p_hwfn, * Return -1 on error. */ static int ecore_pf_wfq_rt_init(struct ecore_hwfn *p_hwfn, - u8 port_id, u8 pf_id, u16 pf_wfq, u8 max_phys_tcs_per_port, @@ -595,7 +613,8 @@ static int ecore_pf_wfq_rt_init(struct ecore_hwfn *p_hwfn, } for (i = 0; i < num_tx_pqs; i++) { - ext_voq = ecore_get_ext_voq(p_hwfn, port_id, pq_params[i].tc_id, + ext_voq = ecore_get_ext_voq(p_hwfn, pq_params[i].port_id, + pq_params[i].tc_id, max_phys_tcs_per_port); crd_reg_offset = (pf_id < MAX_NUM_PFS_BB ? QM_REG_WFQPFCRD_RT_OFFSET : @@ -604,12 +623,12 @@ static int ecore_pf_wfq_rt_init(struct ecore_hwfn *p_hwfn, (pf_id % MAX_NUM_PFS_BB); OVERWRITE_RT_REG(p_hwfn, crd_reg_offset, (u32)QM_WFQ_CRD_REG_SIGN_BIT); - STORE_RT_REG(p_hwfn, QM_REG_WFQPFUPPERBOUND_RT_OFFSET + pf_id, - QM_WFQ_UPPER_BOUND | (u32)QM_WFQ_CRD_REG_SIGN_BIT); - STORE_RT_REG(p_hwfn, QM_REG_WFQPFWEIGHT_RT_OFFSET + pf_id, - inc_val); } + STORE_RT_REG(p_hwfn, QM_REG_WFQPFUPPERBOUND_RT_OFFSET + + pf_id, QM_WFQ_UPPER_BOUND | (u32)QM_WFQ_CRD_REG_SIGN_BIT); + STORE_RT_REG(p_hwfn, QM_REG_WFQPFWEIGHT_RT_OFFSET + pf_id, inc_val); + return 0; } @@ -820,9 +839,9 @@ int ecore_qm_common_rt_init(struct ecore_hwfn *p_hwfn, int ecore_qm_pf_rt_init(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, - u8 port_id, u8 pf_id, u8 max_phys_tcs_per_port, + bool is_pf_loading, u32 num_pf_cids, u32 num_vf_cids, u32 num_tids, @@ -850,20 +869,21 @@ int ecore_qm_pf_rt_init(struct ecore_hwfn *p_hwfn, /* Map Other PQs (if any) */ #if QM_OTHER_PQS_PER_PF > 0 - ecore_other_pq_map_rt_init(p_hwfn, pf_id, num_pf_cids, num_tids, 0); + ecore_other_pq_map_rt_init(p_hwfn, pf_id, is_pf_loading, num_pf_cids, + num_tids, 0); #endif /* Map Tx PQs */ - ecore_tx_pq_map_rt_init(p_hwfn, p_ptt, port_id, pf_id, - max_phys_tcs_per_port, num_pf_cids, num_vf_cids, + ecore_tx_pq_map_rt_init(p_hwfn, p_ptt, pf_id, max_phys_tcs_per_port, + is_pf_loading, num_pf_cids, num_vf_cids, start_pq, num_pf_pqs, num_vf_pqs, start_vport, other_mem_size_4kb, pq_params, vport_params); /* Init PF WFQ */ if (pf_wfq) - if (ecore_pf_wfq_rt_init - (p_hwfn, port_id, pf_id, pf_wfq, max_phys_tcs_per_port, - num_pf_pqs + num_vf_pqs, pq_params)) + if (ecore_pf_wfq_rt_init(p_hwfn, pf_id, pf_wfq, + max_phys_tcs_per_port, + num_pf_pqs + num_vf_pqs, pq_params)) return -1; /* Init PF RL */ @@ -1419,7 +1439,9 @@ void ecore_set_port_mf_ovlan_eth_type(struct ecore_hwfn *p_hwfn, u32 ethType) #define SET_TUNNEL_TYPE_ENABLE_BIT(var, offset, enable) \ (var = ((var) & ~(1 << (offset))) | ((enable) ? (1 << (offset)) : 0)) -#define PRS_ETH_TUNN_FIC_FORMAT -188897008 +#define PRS_ETH_TUNN_OUTPUT_FORMAT -188897008 +#define PRS_ETH_OUTPUT_FORMAT -46832 + void ecore_set_vxlan_dest_port(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, u16 dest_port) { @@ -1444,9 +1466,14 @@ void ecore_set_vxlan_enable(struct ecore_hwfn *p_hwfn, PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_SHIFT, vxlan_enable); ecore_wr(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN, reg_val); - if (reg_val) { - ecore_wr(p_hwfn, p_ptt, PRS_REG_OUTPUT_FORMAT_4_0_BB_K2, - (u32)PRS_ETH_TUNN_FIC_FORMAT); + if (reg_val) { /* TODO: handle E5 init */ + reg_val = ecore_rd(p_hwfn, p_ptt, + PRS_REG_OUTPUT_FORMAT_4_0_BB_K2); + + /* Update output only if tunnel blocks not included. */ + if (reg_val == (u32)PRS_ETH_OUTPUT_FORMAT) + ecore_wr(p_hwfn, p_ptt, PRS_REG_OUTPUT_FORMAT_4_0_BB_K2, + (u32)PRS_ETH_TUNN_OUTPUT_FORMAT); } /* Update NIG register */ @@ -1476,9 +1503,14 @@ void ecore_set_gre_enable(struct ecore_hwfn *p_hwfn, PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_SHIFT, ip_gre_enable); ecore_wr(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN, reg_val); - if (reg_val) { - ecore_wr(p_hwfn, p_ptt, PRS_REG_OUTPUT_FORMAT_4_0_BB_K2, - (u32)PRS_ETH_TUNN_FIC_FORMAT); + if (reg_val) { /* TODO: handle E5 init */ + reg_val = ecore_rd(p_hwfn, p_ptt, + PRS_REG_OUTPUT_FORMAT_4_0_BB_K2); + + /* Update output only if tunnel blocks not included. */ + if (reg_val == (u32)PRS_ETH_OUTPUT_FORMAT) + ecore_wr(p_hwfn, p_ptt, PRS_REG_OUTPUT_FORMAT_4_0_BB_K2, + (u32)PRS_ETH_TUNN_OUTPUT_FORMAT); } /* Update NIG register */ @@ -1526,9 +1558,14 @@ void ecore_set_geneve_enable(struct ecore_hwfn *p_hwfn, PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_SHIFT, ip_geneve_enable); ecore_wr(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN, reg_val); - if (reg_val) { - ecore_wr(p_hwfn, p_ptt, PRS_REG_OUTPUT_FORMAT_4_0_BB_K2, - (u32)PRS_ETH_TUNN_FIC_FORMAT); + if (reg_val) { /* TODO: handle E5 init */ + reg_val = ecore_rd(p_hwfn, p_ptt, + PRS_REG_OUTPUT_FORMAT_4_0_BB_K2); + + /* Update output only if tunnel blocks not included. */ + if (reg_val == (u32)PRS_ETH_OUTPUT_FORMAT) + ecore_wr(p_hwfn, p_ptt, PRS_REG_OUTPUT_FORMAT_4_0_BB_K2, + (u32)PRS_ETH_TUNN_OUTPUT_FORMAT); } /* Update NIG register */ @@ -1548,6 +1585,36 @@ void ecore_set_geneve_enable(struct ecore_hwfn *p_hwfn, ip_geneve_enable ? 1 : 0); } +#define PRS_ETH_VXLAN_NO_L2_ENABLE_OFFSET 4 +#define PRS_ETH_VXLAN_NO_L2_OUTPUT_FORMAT -927094512 + +void ecore_set_vxlan_no_l2_enable(struct ecore_hwfn *p_hwfn, + struct ecore_ptt *p_ptt, + bool enable) +{ + u32 reg_val, cfg_mask; + + /* read PRS config register */ + reg_val = ecore_rd(p_hwfn, p_ptt, PRS_REG_MSG_INFO); + + /* set VXLAN_NO_L2_ENABLE mask */ + cfg_mask = (1 << PRS_ETH_VXLAN_NO_L2_ENABLE_OFFSET); + + if (enable) { + /* set VXLAN_NO_L2_ENABLE flag */ + reg_val |= cfg_mask; + + /* update PRS FIC register */ + ecore_wr(p_hwfn, p_ptt, PRS_REG_OUTPUT_FORMAT_4_0_BB_K2, + (u32)PRS_ETH_VXLAN_NO_L2_OUTPUT_FORMAT); + } else { + /* clear VXLAN_NO_L2_ENABLE flag */ + reg_val &= ~cfg_mask; + } + + /* write PRS config register */ + ecore_wr(p_hwfn, p_ptt, PRS_REG_MSG_INFO, reg_val); +} #define T_ETH_PACKET_ACTION_GFT_EVENTID 23 #define PARSER_ETH_CONN_GFT_ACTION_CM_HDR 272 @@ -1664,6 +1731,10 @@ void ecore_gft_config(struct ecore_hwfn *p_hwfn, ram_line_lo = 0; ram_line_hi = 0; + /* Tunnel type */ + SET_FIELD(ram_line_lo, GFT_RAM_LINE_TUNNEL_DST_PORT, 1); + SET_FIELD(ram_line_lo, GFT_RAM_LINE_TUNNEL_OVER_IP_PROTOCOL, 1); + if (profile_type == GFT_PROFILE_TYPE_4_TUPLE) { SET_FIELD(ram_line_hi, GFT_RAM_LINE_DST_IP, 1); SET_FIELD(ram_line_hi, GFT_RAM_LINE_SRC_IP, 1); @@ -1675,9 +1746,14 @@ void ecore_gft_config(struct ecore_hwfn *p_hwfn, SET_FIELD(ram_line_hi, GFT_RAM_LINE_OVER_IP_PROTOCOL, 1); SET_FIELD(ram_line_lo, GFT_RAM_LINE_ETHERTYPE, 1); SET_FIELD(ram_line_lo, GFT_RAM_LINE_DST_PORT, 1); - } else if (profile_type == GFT_PROFILE_TYPE_IP_DST_PORT) { + } else if (profile_type == GFT_PROFILE_TYPE_IP_DST_ADDR) { SET_FIELD(ram_line_hi, GFT_RAM_LINE_DST_IP, 1); SET_FIELD(ram_line_lo, GFT_RAM_LINE_ETHERTYPE, 1); + } else if (profile_type == GFT_PROFILE_TYPE_IP_SRC_ADDR) { + SET_FIELD(ram_line_hi, GFT_RAM_LINE_SRC_IP, 1); + SET_FIELD(ram_line_lo, GFT_RAM_LINE_ETHERTYPE, 1); + } else if (profile_type == GFT_PROFILE_TYPE_TUNNEL_TYPE) { + SET_FIELD(ram_line_lo, GFT_RAM_LINE_TUNNEL_ETHERTYPE, 1); } ecore_wr(p_hwfn, p_ptt, @@ -1921,3 +1997,53 @@ void ecore_enable_context_validation(struct ecore_hwfn *p_hwfn, ctx_validation = CDU_VALIDATION_DEFAULT_CFG << 8; ecore_wr(p_hwfn, p_ptt, CDU_REG_TCFC_CTX_VALID0, ctx_validation); } + +#define RSS_IND_TABLE_BASE_ADDR 4112 +#define RSS_IND_TABLE_VPORT_SIZE 16 +#define RSS_IND_TABLE_ENTRY_PER_LINE 8 + +/* Update RSS indirection table entry. */ +void ecore_update_eth_rss_ind_table_entry(struct ecore_hwfn *p_hwfn, + struct ecore_ptt *p_ptt, + u8 rss_id, + u8 ind_table_index, + u16 ind_table_value) +{ + u32 cnt, rss_addr; + u32 *reg_val; + u16 rss_ind_entry[RSS_IND_TABLE_ENTRY_PER_LINE]; + u16 rss_ind_mask[RSS_IND_TABLE_ENTRY_PER_LINE]; + + /* get entry address */ + rss_addr = RSS_IND_TABLE_BASE_ADDR + + RSS_IND_TABLE_VPORT_SIZE * rss_id + + ind_table_index / RSS_IND_TABLE_ENTRY_PER_LINE; + + /* prepare update command */ + ind_table_index %= RSS_IND_TABLE_ENTRY_PER_LINE; + + for (cnt = 0; cnt < RSS_IND_TABLE_ENTRY_PER_LINE; cnt++) { + if (cnt == ind_table_index) { + rss_ind_entry[cnt] = ind_table_value; + rss_ind_mask[cnt] = 0xFFFF; + } else { + rss_ind_entry[cnt] = 0; + rss_ind_mask[cnt] = 0; + } + } + + /* Update entry in HW*/ + ecore_wr(p_hwfn, p_ptt, RSS_REG_RSS_RAM_ADDR, rss_addr); + + reg_val = (u32 *)rss_ind_mask; + ecore_wr(p_hwfn, p_ptt, RSS_REG_RSS_RAM_MASK, reg_val[0]); + ecore_wr(p_hwfn, p_ptt, RSS_REG_RSS_RAM_MASK + 4, reg_val[1]); + ecore_wr(p_hwfn, p_ptt, RSS_REG_RSS_RAM_MASK + 8, reg_val[2]); + ecore_wr(p_hwfn, p_ptt, RSS_REG_RSS_RAM_MASK + 12, reg_val[3]); + + reg_val = (u32 *)rss_ind_entry; + ecore_wr(p_hwfn, p_ptt, RSS_REG_RSS_RAM_DATA, reg_val[0]); + ecore_wr(p_hwfn, p_ptt, RSS_REG_RSS_RAM_DATA + 4, reg_val[1]); + ecore_wr(p_hwfn, p_ptt, RSS_REG_RSS_RAM_DATA + 8, reg_val[2]); + ecore_wr(p_hwfn, p_ptt, RSS_REG_RSS_RAM_DATA + 12, reg_val[3]); +} diff --git a/drivers/net/qede/base/ecore_init_fw_funcs.h b/drivers/net/qede/base/ecore_init_fw_funcs.h index ab560e5..7c55609 100644 --- a/drivers/net/qede/base/ecore_init_fw_funcs.h +++ b/drivers/net/qede/base/ecore_init_fw_funcs.h @@ -61,9 +61,10 @@ int ecore_qm_common_rt_init(struct ecore_hwfn *p_hwfn, * * @param p_hwfn * @param p_ptt - ptt window used for writing the registers - * @param port_id - port ID * @param pf_id - PF ID * @param max_phys_tcs_per_port - max number of physical TCs per port in HW + * @param is_pf_loading - indicates if the PF is currently loading, + * i.e. it has no allocated QM resources. * @param num_pf_cids - number of connections used by this PF * @param num_vf_cids - number of connections used by VFs of this PF * @param num_tids - number of tasks used by this PF @@ -87,9 +88,9 @@ int ecore_qm_common_rt_init(struct ecore_hwfn *p_hwfn, */ int ecore_qm_pf_rt_init(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, - u8 port_id, u8 pf_id, u8 max_phys_tcs_per_port, + bool is_pf_loading, u32 num_pf_cids, u32 num_vf_cids, u32 num_tids, @@ -259,6 +260,16 @@ void ecore_init_brb_ram(struct ecore_hwfn *p_hwfn, struct init_brb_ram_req *req); #endif /* UNUSED_HSI_FUNC */ +/** + * @brief ecore_set_vxlan_no_l2_enable - enable or disable VXLAN no L2 parsing + * + * @param p_ptt - ptt window used for writing the registers. + * @param enable - VXLAN no L2 enable flag. + */ +void ecore_set_vxlan_no_l2_enable(struct ecore_hwfn *p_hwfn, + struct ecore_ptt *p_ptt, + bool enable); + #ifndef UNUSED_HSI_FUNC /** * @brief ecore_set_port_mf_ovlan_eth_type - initializes DORQ ethType Regs to @@ -462,4 +473,22 @@ void ecore_memset_session_ctx(void *p_ctx_mem, void ecore_memset_task_ctx(void *p_ctx_mem, u32 ctx_size, u8 ctx_type); + +/** + * @brief ecore_update_eth_rss_ind_table_entry - Update RSS indirection table + * entry. + * The function must run in exclusive mode to prevent wrong RSS configuration. + * + * @param p_hwfn - HW device data + * @param p_ptt - ptt window used for writing the registers. + * @param rss_id - RSS engine ID. + * @param ind_table_index - RSS indirect table index. + * @param ind_table_value - RSS indirect table new value. + */ +void ecore_update_eth_rss_ind_table_entry(struct ecore_hwfn *p_hwfn, + struct ecore_ptt *p_ptt, + u8 rss_id, + u8 ind_table_index, + u16 ind_table_value); + #endif diff --git a/drivers/net/qede/base/ecore_iro_values.h b/drivers/net/qede/base/ecore_iro_values.h index 41532ee..5c9cb47 100644 --- a/drivers/net/qede/base/ecore_iro_values.h +++ b/drivers/net/qede/base/ecore_iro_values.h @@ -13,9 +13,9 @@ /* YSTORM_FLOW_CONTROL_MODE_OFFSET */ { 0x0, 0x0, 0x0, 0x0, 0x8}, /* TSTORM_PORT_STAT_OFFSET(port_id) */ - { 0x4cb0, 0x80, 0x0, 0x0, 0x80}, + { 0x4cb8, 0x88, 0x0, 0x0, 0x88}, /* TSTORM_LL2_PORT_STAT_OFFSET(port_id) */ - { 0x6508, 0x20, 0x0, 0x0, 0x20}, + { 0x6530, 0x20, 0x0, 0x0, 0x20}, /* USTORM_VF_PF_CHANNEL_READY_OFFSET(vf_id) */ { 0xb00, 0x8, 0x0, 0x0, 0x4}, /* USTORM_FLR_FINAL_ACK_OFFSET(pf_id) */ @@ -27,49 +27,49 @@ /* USTORM_COMMON_QUEUE_CONS_OFFSET(queue_zone_id) */ { 0x84, 0x8, 0x0, 0x0, 0x2}, /* XSTORM_INTEG_TEST_DATA_OFFSET */ - { 0x4c40, 0x0, 0x0, 0x0, 0x78}, + { 0x4c48, 0x0, 0x0, 0x0, 0x78}, /* YSTORM_INTEG_TEST_DATA_OFFSET */ - { 0x3e10, 0x0, 0x0, 0x0, 0x78}, + { 0x3e38, 0x0, 0x0, 0x0, 0x78}, /* PSTORM_INTEG_TEST_DATA_OFFSET */ - { 0x2b50, 0x0, 0x0, 0x0, 0x78}, + { 0x2b78, 0x0, 0x0, 0x0, 0x78}, /* TSTORM_INTEG_TEST_DATA_OFFSET */ - { 0x4c38, 0x0, 0x0, 0x0, 0x78}, + { 0x4c40, 0x0, 0x0, 0x0, 0x78}, /* MSTORM_INTEG_TEST_DATA_OFFSET */ - { 0x4990, 0x0, 0x0, 0x0, 0x78}, + { 0x4998, 0x0, 0x0, 0x0, 0x78}, /* USTORM_INTEG_TEST_DATA_OFFSET */ - { 0x7f48, 0x0, 0x0, 0x0, 0x78}, + { 0x7f50, 0x0, 0x0, 0x0, 0x78}, /* TSTORM_LL2_RX_PRODS_OFFSET(core_rx_queue_id) */ { 0xa28, 0x8, 0x0, 0x0, 0x8}, /* CORE_LL2_TSTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) */ - { 0x61e8, 0x10, 0x0, 0x0, 0x10}, + { 0x6210, 0x10, 0x0, 0x0, 0x10}, /* CORE_LL2_USTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) */ { 0xb820, 0x30, 0x0, 0x0, 0x30}, /* CORE_LL2_PSTORM_PER_QUEUE_STAT_OFFSET(core_tx_stats_id) */ - { 0x96b8, 0x30, 0x0, 0x0, 0x30}, + { 0x96c0, 0x30, 0x0, 0x0, 0x30}, /* MSTORM_QUEUE_STAT_OFFSET(stat_counter_id) */ - { 0x4b60, 0x80, 0x0, 0x0, 0x40}, + { 0x4b68, 0x80, 0x0, 0x0, 0x40}, /* MSTORM_ETH_PF_PRODS_OFFSET(queue_id) */ { 0x1f8, 0x4, 0x0, 0x0, 0x4}, /* MSTORM_ETH_VF_PRODS_OFFSET(vf_id,vf_queue_id) */ - { 0x53a0, 0x80, 0x4, 0x0, 0x4}, + { 0x53a8, 0x80, 0x4, 0x0, 0x4}, /* MSTORM_TPA_TIMEOUT_US_OFFSET */ - { 0xc7c8, 0x0, 0x0, 0x0, 0x4}, + { 0xc7d0, 0x0, 0x0, 0x0, 0x4}, /* MSTORM_ETH_PF_STAT_OFFSET(pf_id) */ - { 0x4ba0, 0x80, 0x0, 0x0, 0x20}, + { 0x4ba8, 0x80, 0x0, 0x0, 0x20}, /* USTORM_QUEUE_STAT_OFFSET(stat_counter_id) */ - { 0x8150, 0x40, 0x0, 0x0, 0x30}, + { 0x8158, 0x40, 0x0, 0x0, 0x30}, /* USTORM_ETH_PF_STAT_OFFSET(pf_id) */ { 0xe770, 0x60, 0x0, 0x0, 0x60}, /* PSTORM_QUEUE_STAT_OFFSET(stat_counter_id) */ - { 0x2ce8, 0x80, 0x0, 0x0, 0x38}, + { 0x2d10, 0x80, 0x0, 0x0, 0x38}, /* PSTORM_ETH_PF_STAT_OFFSET(pf_id) */ - { 0xf2b0, 0x78, 0x0, 0x0, 0x78}, + { 0xf2b8, 0x78, 0x0, 0x0, 0x78}, /* PSTORM_CTL_FRAME_ETHTYPE_OFFSET(ethType_id) */ { 0x1f8, 0x4, 0x0, 0x0, 0x4}, /* TSTORM_ETH_PRS_INPUT_OFFSET */ - { 0xaef8, 0x0, 0x0, 0x0, 0xf0}, + { 0xaf20, 0x0, 0x0, 0x0, 0xf0}, /* ETH_RX_RATE_LIMIT_OFFSET(pf_id) */ - { 0xafe8, 0x8, 0x0, 0x0, 0x8}, + { 0xb010, 0x8, 0x0, 0x0, 0x8}, /* XSTORM_ETH_QUEUE_ZONE_OFFSET(queue_id) */ { 0x1f8, 0x8, 0x0, 0x0, 0x8}, /* YSTORM_TOE_CQ_PROD_OFFSET(rss_id) */ @@ -81,37 +81,37 @@ /* TSTORM_SCSI_CMDQ_CONS_OFFSET(cmdq_queue_id) */ { 0x0, 0x8, 0x0, 0x0, 0x8}, /* TSTORM_SCSI_BDQ_EXT_PROD_OFFSET(func_id,bdq_id) */ - { 0x200, 0x18, 0x8, 0x0, 0x8}, + { 0x400, 0x18, 0x8, 0x0, 0x8}, /* MSTORM_SCSI_BDQ_EXT_PROD_OFFSET(func_id,bdq_id) */ { 0xb78, 0x18, 0x8, 0x0, 0x2}, /* TSTORM_ISCSI_RX_STATS_OFFSET(pf_id) */ - { 0xd878, 0x50, 0x0, 0x0, 0x3c}, + { 0xd898, 0x50, 0x0, 0x0, 0x3c}, /* MSTORM_ISCSI_RX_STATS_OFFSET(pf_id) */ { 0x12908, 0x18, 0x0, 0x0, 0x10}, /* USTORM_ISCSI_RX_STATS_OFFSET(pf_id) */ { 0x11aa8, 0x40, 0x0, 0x0, 0x18}, /* XSTORM_ISCSI_TX_STATS_OFFSET(pf_id) */ - { 0xa580, 0x50, 0x0, 0x0, 0x20}, + { 0xa588, 0x50, 0x0, 0x0, 0x20}, /* YSTORM_ISCSI_TX_STATS_OFFSET(pf_id) */ - { 0x86f8, 0x40, 0x0, 0x0, 0x28}, + { 0x8700, 0x40, 0x0, 0x0, 0x28}, /* PSTORM_ISCSI_TX_STATS_OFFSET(pf_id) */ - { 0x102f8, 0x18, 0x0, 0x0, 0x10}, + { 0x10300, 0x18, 0x0, 0x0, 0x10}, /* TSTORM_FCOE_RX_STATS_OFFSET(pf_id) */ - { 0xde28, 0x48, 0x0, 0x0, 0x38}, + { 0xde48, 0x48, 0x0, 0x0, 0x38}, /* PSTORM_FCOE_TX_STATS_OFFSET(pf_id) */ - { 0x10760, 0x20, 0x0, 0x0, 0x20}, + { 0x10768, 0x20, 0x0, 0x0, 0x20}, /* PSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id) */ - { 0x2d20, 0x80, 0x0, 0x0, 0x10}, + { 0x2d48, 0x80, 0x0, 0x0, 0x10}, /* TSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id) */ - { 0x5020, 0x10, 0x0, 0x0, 0x10}, + { 0x5048, 0x10, 0x0, 0x0, 0x10}, /* XSTORM_IWARP_RXMIT_STATS_OFFSET(pf_id) */ - { 0xc9b0, 0x30, 0x0, 0x0, 0x10}, + { 0xc9b8, 0x30, 0x0, 0x0, 0x10}, /* TSTORM_ROCE_EVENTS_STAT_OFFSET(roce_pf_id) */ - { 0xeec0, 0x10, 0x0, 0x0, 0x10}, + { 0xed90, 0x10, 0x0, 0x0, 0x10}, /* YSTORM_ROCE_DCQCN_RECEIVED_STATS_OFFSET(roce_pf_id) */ - { 0xa398, 0x10, 0x0, 0x0, 0x10}, + { 0xa520, 0x10, 0x0, 0x0, 0x10}, /* PSTORM_ROCE_DCQCN_SENT_STATS_OFFSET(roce_pf_id) */ - { 0x13100, 0x8, 0x0, 0x0, 0x8}, + { 0x13108, 0x8, 0x0, 0x0, 0x8}, }; #endif /* __IRO_VALUES_H__ */ diff --git a/drivers/net/qede/base/ecore_l2.c b/drivers/net/qede/base/ecore_l2.c index e3afc8a..a0ee87a 100644 --- a/drivers/net/qede/base/ecore_l2.c +++ b/drivers/net/qede/base/ecore_l2.c @@ -2150,7 +2150,7 @@ enum _ecore_status_t p_ramrod->flow_id_valid = 0; p_ramrod->flow_id = 0; - p_ramrod->vport_id = abs_vport_id; + p_ramrod->vport_id = OSAL_CPU_TO_LE16((u16)abs_vport_id); p_ramrod->filter_action = b_is_add ? GFT_ADD_FILTER : GFT_DELETE_FILTER; diff --git a/drivers/net/qede/base/ecore_rt_defs.h b/drivers/net/qede/base/ecore_rt_defs.h index 401e4b6..e20c98d 100644 --- a/drivers/net/qede/base/ecore_rt_defs.h +++ b/drivers/net/qede/base/ecore_rt_defs.h @@ -205,330 +205,334 @@ #define QM_REG_MAXPQSIZETXSEL_63_RT_OFFSET 34082 #define QM_REG_BASEADDROTHERPQ_RT_OFFSET 34083 #define QM_REG_BASEADDROTHERPQ_RT_SIZE 128 -#define QM_REG_AFULLQMBYPTHRPFWFQ_RT_OFFSET 34211 -#define QM_REG_AFULLQMBYPTHRVPWFQ_RT_OFFSET 34212 -#define QM_REG_AFULLQMBYPTHRPFRL_RT_OFFSET 34213 -#define QM_REG_AFULLQMBYPTHRGLBLRL_RT_OFFSET 34214 -#define QM_REG_AFULLOPRTNSTCCRDMASK_RT_OFFSET 34215 -#define QM_REG_WRROTHERPQGRP_0_RT_OFFSET 34216 -#define QM_REG_WRROTHERPQGRP_1_RT_OFFSET 34217 -#define QM_REG_WRROTHERPQGRP_2_RT_OFFSET 34218 -#define QM_REG_WRROTHERPQGRP_3_RT_OFFSET 34219 -#define QM_REG_WRROTHERPQGRP_4_RT_OFFSET 34220 -#define QM_REG_WRROTHERPQGRP_5_RT_OFFSET 34221 -#define QM_REG_WRROTHERPQGRP_6_RT_OFFSET 34222 -#define QM_REG_WRROTHERPQGRP_7_RT_OFFSET 34223 -#define QM_REG_WRROTHERPQGRP_8_RT_OFFSET 34224 -#define QM_REG_WRROTHERPQGRP_9_RT_OFFSET 34225 -#define QM_REG_WRROTHERPQGRP_10_RT_OFFSET 34226 -#define QM_REG_WRROTHERPQGRP_11_RT_OFFSET 34227 -#define QM_REG_WRROTHERPQGRP_12_RT_OFFSET 34228 -#define QM_REG_WRROTHERPQGRP_13_RT_OFFSET 34229 -#define QM_REG_WRROTHERPQGRP_14_RT_OFFSET 34230 -#define QM_REG_WRROTHERPQGRP_15_RT_OFFSET 34231 -#define QM_REG_WRROTHERGRPWEIGHT_0_RT_OFFSET 34232 -#define QM_REG_WRROTHERGRPWEIGHT_1_RT_OFFSET 34233 -#define QM_REG_WRROTHERGRPWEIGHT_2_RT_OFFSET 34234 -#define QM_REG_WRROTHERGRPWEIGHT_3_RT_OFFSET 34235 -#define QM_REG_WRRTXGRPWEIGHT_0_RT_OFFSET 34236 -#define QM_REG_WRRTXGRPWEIGHT_1_RT_OFFSET 34237 -#define QM_REG_PQTX2PF_0_RT_OFFSET 34238 -#define QM_REG_PQTX2PF_1_RT_OFFSET 34239 -#define QM_REG_PQTX2PF_2_RT_OFFSET 34240 -#define QM_REG_PQTX2PF_3_RT_OFFSET 34241 -#define QM_REG_PQTX2PF_4_RT_OFFSET 34242 -#define QM_REG_PQTX2PF_5_RT_OFFSET 34243 -#define QM_REG_PQTX2PF_6_RT_OFFSET 34244 -#define QM_REG_PQTX2PF_7_RT_OFFSET 34245 -#define QM_REG_PQTX2PF_8_RT_OFFSET 34246 -#define QM_REG_PQTX2PF_9_RT_OFFSET 34247 -#define QM_REG_PQTX2PF_10_RT_OFFSET 34248 -#define QM_REG_PQTX2PF_11_RT_OFFSET 34249 -#define QM_REG_PQTX2PF_12_RT_OFFSET 34250 -#define QM_REG_PQTX2PF_13_RT_OFFSET 34251 -#define QM_REG_PQTX2PF_14_RT_OFFSET 34252 -#define QM_REG_PQTX2PF_15_RT_OFFSET 34253 -#define QM_REG_PQTX2PF_16_RT_OFFSET 34254 -#define QM_REG_PQTX2PF_17_RT_OFFSET 34255 -#define QM_REG_PQTX2PF_18_RT_OFFSET 34256 -#define QM_REG_PQTX2PF_19_RT_OFFSET 34257 -#define QM_REG_PQTX2PF_20_RT_OFFSET 34258 -#define QM_REG_PQTX2PF_21_RT_OFFSET 34259 -#define QM_REG_PQTX2PF_22_RT_OFFSET 34260 -#define QM_REG_PQTX2PF_23_RT_OFFSET 34261 -#define QM_REG_PQTX2PF_24_RT_OFFSET 34262 -#define QM_REG_PQTX2PF_25_RT_OFFSET 34263 -#define QM_REG_PQTX2PF_26_RT_OFFSET 34264 -#define QM_REG_PQTX2PF_27_RT_OFFSET 34265 -#define QM_REG_PQTX2PF_28_RT_OFFSET 34266 -#define QM_REG_PQTX2PF_29_RT_OFFSET 34267 -#define QM_REG_PQTX2PF_30_RT_OFFSET 34268 -#define QM_REG_PQTX2PF_31_RT_OFFSET 34269 -#define QM_REG_PQTX2PF_32_RT_OFFSET 34270 -#define QM_REG_PQTX2PF_33_RT_OFFSET 34271 -#define QM_REG_PQTX2PF_34_RT_OFFSET 34272 -#define QM_REG_PQTX2PF_35_RT_OFFSET 34273 -#define QM_REG_PQTX2PF_36_RT_OFFSET 34274 -#define QM_REG_PQTX2PF_37_RT_OFFSET 34275 -#define QM_REG_PQTX2PF_38_RT_OFFSET 34276 -#define QM_REG_PQTX2PF_39_RT_OFFSET 34277 -#define QM_REG_PQTX2PF_40_RT_OFFSET 34278 -#define QM_REG_PQTX2PF_41_RT_OFFSET 34279 -#define QM_REG_PQTX2PF_42_RT_OFFSET 34280 -#define QM_REG_PQTX2PF_43_RT_OFFSET 34281 -#define QM_REG_PQTX2PF_44_RT_OFFSET 34282 -#define QM_REG_PQTX2PF_45_RT_OFFSET 34283 -#define QM_REG_PQTX2PF_46_RT_OFFSET 34284 -#define QM_REG_PQTX2PF_47_RT_OFFSET 34285 -#define QM_REG_PQTX2PF_48_RT_OFFSET 34286 -#define QM_REG_PQTX2PF_49_RT_OFFSET 34287 -#define QM_REG_PQTX2PF_50_RT_OFFSET 34288 -#define QM_REG_PQTX2PF_51_RT_OFFSET 34289 -#define QM_REG_PQTX2PF_52_RT_OFFSET 34290 -#define QM_REG_PQTX2PF_53_RT_OFFSET 34291 -#define QM_REG_PQTX2PF_54_RT_OFFSET 34292 -#define QM_REG_PQTX2PF_55_RT_OFFSET 34293 -#define QM_REG_PQTX2PF_56_RT_OFFSET 34294 -#define QM_REG_PQTX2PF_57_RT_OFFSET 34295 -#define QM_REG_PQTX2PF_58_RT_OFFSET 34296 -#define QM_REG_PQTX2PF_59_RT_OFFSET 34297 -#define QM_REG_PQTX2PF_60_RT_OFFSET 34298 -#define QM_REG_PQTX2PF_61_RT_OFFSET 34299 -#define QM_REG_PQTX2PF_62_RT_OFFSET 34300 -#define QM_REG_PQTX2PF_63_RT_OFFSET 34301 -#define QM_REG_PQOTHER2PF_0_RT_OFFSET 34302 -#define QM_REG_PQOTHER2PF_1_RT_OFFSET 34303 -#define QM_REG_PQOTHER2PF_2_RT_OFFSET 34304 -#define QM_REG_PQOTHER2PF_3_RT_OFFSET 34305 -#define QM_REG_PQOTHER2PF_4_RT_OFFSET 34306 -#define QM_REG_PQOTHER2PF_5_RT_OFFSET 34307 -#define QM_REG_PQOTHER2PF_6_RT_OFFSET 34308 -#define QM_REG_PQOTHER2PF_7_RT_OFFSET 34309 -#define QM_REG_PQOTHER2PF_8_RT_OFFSET 34310 -#define QM_REG_PQOTHER2PF_9_RT_OFFSET 34311 -#define QM_REG_PQOTHER2PF_10_RT_OFFSET 34312 -#define QM_REG_PQOTHER2PF_11_RT_OFFSET 34313 -#define QM_REG_PQOTHER2PF_12_RT_OFFSET 34314 -#define QM_REG_PQOTHER2PF_13_RT_OFFSET 34315 -#define QM_REG_PQOTHER2PF_14_RT_OFFSET 34316 -#define QM_REG_PQOTHER2PF_15_RT_OFFSET 34317 -#define QM_REG_RLGLBLPERIOD_0_RT_OFFSET 34318 -#define QM_REG_RLGLBLPERIOD_1_RT_OFFSET 34319 -#define QM_REG_RLGLBLPERIODTIMER_0_RT_OFFSET 34320 -#define QM_REG_RLGLBLPERIODTIMER_1_RT_OFFSET 34321 -#define QM_REG_RLGLBLPERIODSEL_0_RT_OFFSET 34322 -#define QM_REG_RLGLBLPERIODSEL_1_RT_OFFSET 34323 -#define QM_REG_RLGLBLPERIODSEL_2_RT_OFFSET 34324 -#define QM_REG_RLGLBLPERIODSEL_3_RT_OFFSET 34325 -#define QM_REG_RLGLBLPERIODSEL_4_RT_OFFSET 34326 -#define QM_REG_RLGLBLPERIODSEL_5_RT_OFFSET 34327 -#define QM_REG_RLGLBLPERIODSEL_6_RT_OFFSET 34328 -#define QM_REG_RLGLBLPERIODSEL_7_RT_OFFSET 34329 -#define QM_REG_RLGLBLINCVAL_RT_OFFSET 34330 +#define QM_REG_PTRTBLOTHER_RT_OFFSET 34211 +#define QM_REG_PTRTBLOTHER_RT_SIZE 256 +#define QM_REG_AFULLQMBYPTHRPFWFQ_RT_OFFSET 34467 +#define QM_REG_AFULLQMBYPTHRVPWFQ_RT_OFFSET 34468 +#define QM_REG_AFULLQMBYPTHRPFRL_RT_OFFSET 34469 +#define QM_REG_AFULLQMBYPTHRGLBLRL_RT_OFFSET 34470 +#define QM_REG_AFULLOPRTNSTCCRDMASK_RT_OFFSET 34471 +#define QM_REG_WRROTHERPQGRP_0_RT_OFFSET 34472 +#define QM_REG_WRROTHERPQGRP_1_RT_OFFSET 34473 +#define QM_REG_WRROTHERPQGRP_2_RT_OFFSET 34474 +#define QM_REG_WRROTHERPQGRP_3_RT_OFFSET 34475 +#define QM_REG_WRROTHERPQGRP_4_RT_OFFSET 34476 +#define QM_REG_WRROTHERPQGRP_5_RT_OFFSET 34477 +#define QM_REG_WRROTHERPQGRP_6_RT_OFFSET 34478 +#define QM_REG_WRROTHERPQGRP_7_RT_OFFSET 34479 +#define QM_REG_WRROTHERPQGRP_8_RT_OFFSET 34480 +#define QM_REG_WRROTHERPQGRP_9_RT_OFFSET 34481 +#define QM_REG_WRROTHERPQGRP_10_RT_OFFSET 34482 +#define QM_REG_WRROTHERPQGRP_11_RT_OFFSET 34483 +#define QM_REG_WRROTHERPQGRP_12_RT_OFFSET 34484 +#define QM_REG_WRROTHERPQGRP_13_RT_OFFSET 34485 +#define QM_REG_WRROTHERPQGRP_14_RT_OFFSET 34486 +#define QM_REG_WRROTHERPQGRP_15_RT_OFFSET 34487 +#define QM_REG_WRROTHERGRPWEIGHT_0_RT_OFFSET 34488 +#define QM_REG_WRROTHERGRPWEIGHT_1_RT_OFFSET 34489 +#define QM_REG_WRROTHERGRPWEIGHT_2_RT_OFFSET 34490 +#define QM_REG_WRROTHERGRPWEIGHT_3_RT_OFFSET 34491 +#define QM_REG_WRRTXGRPWEIGHT_0_RT_OFFSET 34492 +#define QM_REG_WRRTXGRPWEIGHT_1_RT_OFFSET 34493 +#define QM_REG_PQTX2PF_0_RT_OFFSET 34494 +#define QM_REG_PQTX2PF_1_RT_OFFSET 34495 +#define QM_REG_PQTX2PF_2_RT_OFFSET 34496 +#define QM_REG_PQTX2PF_3_RT_OFFSET 34497 +#define QM_REG_PQTX2PF_4_RT_OFFSET 34498 +#define QM_REG_PQTX2PF_5_RT_OFFSET 34499 +#define QM_REG_PQTX2PF_6_RT_OFFSET 34500 +#define QM_REG_PQTX2PF_7_RT_OFFSET 34501 +#define QM_REG_PQTX2PF_8_RT_OFFSET 34502 +#define QM_REG_PQTX2PF_9_RT_OFFSET 34503 +#define QM_REG_PQTX2PF_10_RT_OFFSET 34504 +#define QM_REG_PQTX2PF_11_RT_OFFSET 34505 +#define QM_REG_PQTX2PF_12_RT_OFFSET 34506 +#define QM_REG_PQTX2PF_13_RT_OFFSET 34507 +#define QM_REG_PQTX2PF_14_RT_OFFSET 34508 +#define QM_REG_PQTX2PF_15_RT_OFFSET 34509 +#define QM_REG_PQTX2PF_16_RT_OFFSET 34510 +#define QM_REG_PQTX2PF_17_RT_OFFSET 34511 +#define QM_REG_PQTX2PF_18_RT_OFFSET 34512 +#define QM_REG_PQTX2PF_19_RT_OFFSET 34513 +#define QM_REG_PQTX2PF_20_RT_OFFSET 34514 +#define QM_REG_PQTX2PF_21_RT_OFFSET 34515 +#define QM_REG_PQTX2PF_22_RT_OFFSET 34516 +#define QM_REG_PQTX2PF_23_RT_OFFSET 34517 +#define QM_REG_PQTX2PF_24_RT_OFFSET 34518 +#define QM_REG_PQTX2PF_25_RT_OFFSET 34519 +#define QM_REG_PQTX2PF_26_RT_OFFSET 34520 +#define QM_REG_PQTX2PF_27_RT_OFFSET 34521 +#define QM_REG_PQTX2PF_28_RT_OFFSET 34522 +#define QM_REG_PQTX2PF_29_RT_OFFSET 34523 +#define QM_REG_PQTX2PF_30_RT_OFFSET 34524 +#define QM_REG_PQTX2PF_31_RT_OFFSET 34525 +#define QM_REG_PQTX2PF_32_RT_OFFSET 34526 +#define QM_REG_PQTX2PF_33_RT_OFFSET 34527 +#define QM_REG_PQTX2PF_34_RT_OFFSET 34528 +#define QM_REG_PQTX2PF_35_RT_OFFSET 34529 +#define QM_REG_PQTX2PF_36_RT_OFFSET 34530 +#define QM_REG_PQTX2PF_37_RT_OFFSET 34531 +#define QM_REG_PQTX2PF_38_RT_OFFSET 34532 +#define QM_REG_PQTX2PF_39_RT_OFFSET 34533 +#define QM_REG_PQTX2PF_40_RT_OFFSET 34534 +#define QM_REG_PQTX2PF_41_RT_OFFSET 34535 +#define QM_REG_PQTX2PF_42_RT_OFFSET 34536 +#define QM_REG_PQTX2PF_43_RT_OFFSET 34537 +#define QM_REG_PQTX2PF_44_RT_OFFSET 34538 +#define QM_REG_PQTX2PF_45_RT_OFFSET 34539 +#define QM_REG_PQTX2PF_46_RT_OFFSET 34540 +#define QM_REG_PQTX2PF_47_RT_OFFSET 34541 +#define QM_REG_PQTX2PF_48_RT_OFFSET 34542 +#define QM_REG_PQTX2PF_49_RT_OFFSET 34543 +#define QM_REG_PQTX2PF_50_RT_OFFSET 34544 +#define QM_REG_PQTX2PF_51_RT_OFFSET 34545 +#define QM_REG_PQTX2PF_52_RT_OFFSET 34546 +#define QM_REG_PQTX2PF_53_RT_OFFSET 34547 +#define QM_REG_PQTX2PF_54_RT_OFFSET 34548 +#define QM_REG_PQTX2PF_55_RT_OFFSET 34549 +#define QM_REG_PQTX2PF_56_RT_OFFSET 34550 +#define QM_REG_PQTX2PF_57_RT_OFFSET 34551 +#define QM_REG_PQTX2PF_58_RT_OFFSET 34552 +#define QM_REG_PQTX2PF_59_RT_OFFSET 34553 +#define QM_REG_PQTX2PF_60_RT_OFFSET 34554 +#define QM_REG_PQTX2PF_61_RT_OFFSET 34555 +#define QM_REG_PQTX2PF_62_RT_OFFSET 34556 +#define QM_REG_PQTX2PF_63_RT_OFFSET 34557 +#define QM_REG_PQOTHER2PF_0_RT_OFFSET 34558 +#define QM_REG_PQOTHER2PF_1_RT_OFFSET 34559 +#define QM_REG_PQOTHER2PF_2_RT_OFFSET 34560 +#define QM_REG_PQOTHER2PF_3_RT_OFFSET 34561 +#define QM_REG_PQOTHER2PF_4_RT_OFFSET 34562 +#define QM_REG_PQOTHER2PF_5_RT_OFFSET 34563 +#define QM_REG_PQOTHER2PF_6_RT_OFFSET 34564 +#define QM_REG_PQOTHER2PF_7_RT_OFFSET 34565 +#define QM_REG_PQOTHER2PF_8_RT_OFFSET 34566 +#define QM_REG_PQOTHER2PF_9_RT_OFFSET 34567 +#define QM_REG_PQOTHER2PF_10_RT_OFFSET 34568 +#define QM_REG_PQOTHER2PF_11_RT_OFFSET 34569 +#define QM_REG_PQOTHER2PF_12_RT_OFFSET 34570 +#define QM_REG_PQOTHER2PF_13_RT_OFFSET 34571 +#define QM_REG_PQOTHER2PF_14_RT_OFFSET 34572 +#define QM_REG_PQOTHER2PF_15_RT_OFFSET 34573 +#define QM_REG_RLGLBLPERIOD_0_RT_OFFSET 34574 +#define QM_REG_RLGLBLPERIOD_1_RT_OFFSET 34575 +#define QM_REG_RLGLBLPERIODTIMER_0_RT_OFFSET 34576 +#define QM_REG_RLGLBLPERIODTIMER_1_RT_OFFSET 34577 +#define QM_REG_RLGLBLPERIODSEL_0_RT_OFFSET 34578 +#define QM_REG_RLGLBLPERIODSEL_1_RT_OFFSET 34579 +#define QM_REG_RLGLBLPERIODSEL_2_RT_OFFSET 34580 +#define QM_REG_RLGLBLPERIODSEL_3_RT_OFFSET 34581 +#define QM_REG_RLGLBLPERIODSEL_4_RT_OFFSET 34582 +#define QM_REG_RLGLBLPERIODSEL_5_RT_OFFSET 34583 +#define QM_REG_RLGLBLPERIODSEL_6_RT_OFFSET 34584 +#define QM_REG_RLGLBLPERIODSEL_7_RT_OFFSET 34585 +#define QM_REG_RLGLBLINCVAL_RT_OFFSET 34586 #define QM_REG_RLGLBLINCVAL_RT_SIZE 256 -#define QM_REG_RLGLBLUPPERBOUND_RT_OFFSET 34586 +#define QM_REG_RLGLBLUPPERBOUND_RT_OFFSET 34842 #define QM_REG_RLGLBLUPPERBOUND_RT_SIZE 256 -#define QM_REG_RLGLBLCRD_RT_OFFSET 34842 +#define QM_REG_RLGLBLCRD_RT_OFFSET 35098 #define QM_REG_RLGLBLCRD_RT_SIZE 256 -#define QM_REG_RLGLBLENABLE_RT_OFFSET 35098 -#define QM_REG_RLPFPERIOD_RT_OFFSET 35099 -#define QM_REG_RLPFPERIODTIMER_RT_OFFSET 35100 -#define QM_REG_RLPFINCVAL_RT_OFFSET 35101 +#define QM_REG_RLGLBLENABLE_RT_OFFSET 35354 +#define QM_REG_RLPFPERIOD_RT_OFFSET 35355 +#define QM_REG_RLPFPERIODTIMER_RT_OFFSET 35356 +#define QM_REG_RLPFINCVAL_RT_OFFSET 35357 #define QM_REG_RLPFINCVAL_RT_SIZE 16 -#define QM_REG_RLPFUPPERBOUND_RT_OFFSET 35117 +#define QM_REG_RLPFUPPERBOUND_RT_OFFSET 35373 #define QM_REG_RLPFUPPERBOUND_RT_SIZE 16 -#define QM_REG_RLPFCRD_RT_OFFSET 35133 +#define QM_REG_RLPFCRD_RT_OFFSET 35389 #define QM_REG_RLPFCRD_RT_SIZE 16 -#define QM_REG_RLPFENABLE_RT_OFFSET 35149 -#define QM_REG_RLPFVOQENABLE_RT_OFFSET 35150 -#define QM_REG_WFQPFWEIGHT_RT_OFFSET 35151 +#define QM_REG_RLPFENABLE_RT_OFFSET 35405 +#define QM_REG_RLPFVOQENABLE_RT_OFFSET 35406 +#define QM_REG_WFQPFWEIGHT_RT_OFFSET 35407 #define QM_REG_WFQPFWEIGHT_RT_SIZE 16 -#define QM_REG_WFQPFUPPERBOUND_RT_OFFSET 35167 +#define QM_REG_WFQPFUPPERBOUND_RT_OFFSET 35423 #define QM_REG_WFQPFUPPERBOUND_RT_SIZE 16 -#define QM_REG_WFQPFCRD_RT_OFFSET 35183 +#define QM_REG_WFQPFCRD_RT_OFFSET 35439 #define QM_REG_WFQPFCRD_RT_SIZE 256 -#define QM_REG_WFQPFENABLE_RT_OFFSET 35439 -#define QM_REG_WFQVPENABLE_RT_OFFSET 35440 -#define QM_REG_BASEADDRTXPQ_RT_OFFSET 35441 +#define QM_REG_WFQPFENABLE_RT_OFFSET 35695 +#define QM_REG_WFQVPENABLE_RT_OFFSET 35696 +#define QM_REG_BASEADDRTXPQ_RT_OFFSET 35697 #define QM_REG_BASEADDRTXPQ_RT_SIZE 512 -#define QM_REG_TXPQMAP_RT_OFFSET 35953 +#define QM_REG_TXPQMAP_RT_OFFSET 36209 #define QM_REG_TXPQMAP_RT_SIZE 512 -#define QM_REG_WFQVPWEIGHT_RT_OFFSET 36465 +#define QM_REG_WFQVPWEIGHT_RT_OFFSET 36721 #define QM_REG_WFQVPWEIGHT_RT_SIZE 512 -#define QM_REG_WFQVPCRD_RT_OFFSET 36977 +#define QM_REG_WFQVPCRD_RT_OFFSET 37233 #define QM_REG_WFQVPCRD_RT_SIZE 512 -#define QM_REG_WFQVPMAP_RT_OFFSET 37489 +#define QM_REG_WFQVPMAP_RT_OFFSET 37745 #define QM_REG_WFQVPMAP_RT_SIZE 512 -#define QM_REG_WFQPFCRD_MSB_RT_OFFSET 38001 +#define QM_REG_PTRTBLTX_RT_OFFSET 38257 +#define QM_REG_PTRTBLTX_RT_SIZE 1024 +#define QM_REG_WFQPFCRD_MSB_RT_OFFSET 39281 #define QM_REG_WFQPFCRD_MSB_RT_SIZE 320 -#define QM_REG_VOQCRDLINE_RT_OFFSET 38321 +#define QM_REG_VOQCRDLINE_RT_OFFSET 39601 #define QM_REG_VOQCRDLINE_RT_SIZE 36 -#define QM_REG_VOQINITCRDLINE_RT_OFFSET 38357 +#define QM_REG_VOQINITCRDLINE_RT_OFFSET 39637 #define QM_REG_VOQINITCRDLINE_RT_SIZE 36 -#define QM_REG_RLPFVOQENABLE_MSB_RT_OFFSET 38393 -#define NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET 38394 -#define NIG_REG_BRB_GATE_DNTFWD_PORT_RT_OFFSET 38395 -#define NIG_REG_OUTER_TAG_VALUE_LIST0_RT_OFFSET 38396 -#define NIG_REG_OUTER_TAG_VALUE_LIST1_RT_OFFSET 38397 -#define NIG_REG_OUTER_TAG_VALUE_LIST2_RT_OFFSET 38398 -#define NIG_REG_OUTER_TAG_VALUE_LIST3_RT_OFFSET 38399 -#define NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET 38400 -#define NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET 38401 +#define QM_REG_RLPFVOQENABLE_MSB_RT_OFFSET 39673 +#define NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET 39674 +#define NIG_REG_BRB_GATE_DNTFWD_PORT_RT_OFFSET 39675 +#define NIG_REG_OUTER_TAG_VALUE_LIST0_RT_OFFSET 39676 +#define NIG_REG_OUTER_TAG_VALUE_LIST1_RT_OFFSET 39677 +#define NIG_REG_OUTER_TAG_VALUE_LIST2_RT_OFFSET 39678 +#define NIG_REG_OUTER_TAG_VALUE_LIST3_RT_OFFSET 39679 +#define NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET 39680 +#define NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET 39681 #define NIG_REG_LLH_FUNC_TAG_EN_RT_SIZE 4 -#define NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET 38405 +#define NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET 39685 #define NIG_REG_LLH_FUNC_TAG_VALUE_RT_SIZE 4 -#define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_OFFSET 38409 +#define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_OFFSET 39689 #define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_SIZE 32 -#define NIG_REG_LLH_FUNC_FILTER_EN_RT_OFFSET 38441 +#define NIG_REG_LLH_FUNC_FILTER_EN_RT_OFFSET 39721 #define NIG_REG_LLH_FUNC_FILTER_EN_RT_SIZE 16 -#define NIG_REG_LLH_FUNC_FILTER_MODE_RT_OFFSET 38457 +#define NIG_REG_LLH_FUNC_FILTER_MODE_RT_OFFSET 39737 #define NIG_REG_LLH_FUNC_FILTER_MODE_RT_SIZE 16 -#define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_OFFSET 38473 +#define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_OFFSET 39753 #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_SIZE 16 -#define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET 38489 +#define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET 39769 #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_SIZE 16 -#define NIG_REG_TX_EDPM_CTRL_RT_OFFSET 38505 -#define NIG_REG_ROCE_DUPLICATE_TO_HOST_RT_OFFSET 38506 -#define NIG_REG_PPF_TO_ENGINE_SEL_RT_OFFSET 38507 +#define NIG_REG_TX_EDPM_CTRL_RT_OFFSET 39785 +#define NIG_REG_ROCE_DUPLICATE_TO_HOST_RT_OFFSET 39786 +#define NIG_REG_PPF_TO_ENGINE_SEL_RT_OFFSET 39787 #define NIG_REG_PPF_TO_ENGINE_SEL_RT_SIZE 8 -#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_VALUE_RT_OFFSET 38515 +#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_VALUE_RT_OFFSET 39795 #define NIG_REG_LLH_PF_CLS_FUNC_FILTER_VALUE_RT_SIZE 1024 -#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_EN_RT_OFFSET 39539 +#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_EN_RT_OFFSET 40819 #define NIG_REG_LLH_PF_CLS_FUNC_FILTER_EN_RT_SIZE 512 -#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_MODE_RT_OFFSET 40051 +#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_MODE_RT_OFFSET 41331 #define NIG_REG_LLH_PF_CLS_FUNC_FILTER_MODE_RT_SIZE 512 -#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_PROTOCOL_TYPE_RT_OFFSET 40563 +#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_PROTOCOL_TYPE_RT_OFFSET 41843 #define NIG_REG_LLH_PF_CLS_FUNC_FILTER_PROTOCOL_TYPE_RT_SIZE 512 -#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_HDR_SEL_RT_OFFSET 41075 +#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_HDR_SEL_RT_OFFSET 42355 #define NIG_REG_LLH_PF_CLS_FUNC_FILTER_HDR_SEL_RT_SIZE 512 -#define NIG_REG_LLH_PF_CLS_FILTERS_MAP_RT_OFFSET 41587 +#define NIG_REG_LLH_PF_CLS_FILTERS_MAP_RT_OFFSET 42867 #define NIG_REG_LLH_PF_CLS_FILTERS_MAP_RT_SIZE 32 -#define CDU_REG_CID_ADDR_PARAMS_RT_OFFSET 41619 -#define CDU_REG_SEGMENT0_PARAMS_RT_OFFSET 41620 -#define CDU_REG_SEGMENT1_PARAMS_RT_OFFSET 41621 -#define CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET 41622 -#define CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET 41623 -#define CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET 41624 -#define CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET 41625 -#define CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET 41626 -#define CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET 41627 -#define CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET 41628 -#define CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET 41629 -#define CDU_REG_VF_SEG_TYPE_OFFSET_RT_OFFSET 41630 -#define CDU_REG_VF_FL_SEG_TYPE_OFFSET_RT_OFFSET 41631 -#define PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET 41632 -#define PBF_REG_BTB_SHARED_AREA_SIZE_RT_OFFSET 41633 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET 41634 -#define PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET 41635 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ0_RT_OFFSET 41636 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ1_RT_OFFSET 41637 -#define PBF_REG_BTB_GUARANTEED_VOQ1_RT_OFFSET 41638 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ1_RT_OFFSET 41639 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ2_RT_OFFSET 41640 -#define PBF_REG_BTB_GUARANTEED_VOQ2_RT_OFFSET 41641 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ2_RT_OFFSET 41642 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ3_RT_OFFSET 41643 -#define PBF_REG_BTB_GUARANTEED_VOQ3_RT_OFFSET 41644 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ3_RT_OFFSET 41645 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ4_RT_OFFSET 41646 -#define PBF_REG_BTB_GUARANTEED_VOQ4_RT_OFFSET 41647 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ4_RT_OFFSET 41648 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ5_RT_OFFSET 41649 -#define PBF_REG_BTB_GUARANTEED_VOQ5_RT_OFFSET 41650 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ5_RT_OFFSET 41651 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ6_RT_OFFSET 41652 -#define PBF_REG_BTB_GUARANTEED_VOQ6_RT_OFFSET 41653 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ6_RT_OFFSET 41654 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ7_RT_OFFSET 41655 -#define PBF_REG_BTB_GUARANTEED_VOQ7_RT_OFFSET 41656 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ7_RT_OFFSET 41657 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ8_RT_OFFSET 41658 -#define PBF_REG_BTB_GUARANTEED_VOQ8_RT_OFFSET 41659 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ8_RT_OFFSET 41660 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ9_RT_OFFSET 41661 -#define PBF_REG_BTB_GUARANTEED_VOQ9_RT_OFFSET 41662 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ9_RT_OFFSET 41663 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ10_RT_OFFSET 41664 -#define PBF_REG_BTB_GUARANTEED_VOQ10_RT_OFFSET 41665 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ10_RT_OFFSET 41666 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ11_RT_OFFSET 41667 -#define PBF_REG_BTB_GUARANTEED_VOQ11_RT_OFFSET 41668 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ11_RT_OFFSET 41669 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ12_RT_OFFSET 41670 -#define PBF_REG_BTB_GUARANTEED_VOQ12_RT_OFFSET 41671 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ12_RT_OFFSET 41672 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ13_RT_OFFSET 41673 -#define PBF_REG_BTB_GUARANTEED_VOQ13_RT_OFFSET 41674 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ13_RT_OFFSET 41675 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ14_RT_OFFSET 41676 -#define PBF_REG_BTB_GUARANTEED_VOQ14_RT_OFFSET 41677 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ14_RT_OFFSET 41678 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ15_RT_OFFSET 41679 -#define PBF_REG_BTB_GUARANTEED_VOQ15_RT_OFFSET 41680 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ15_RT_OFFSET 41681 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ16_RT_OFFSET 41682 -#define PBF_REG_BTB_GUARANTEED_VOQ16_RT_OFFSET 41683 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ16_RT_OFFSET 41684 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ17_RT_OFFSET 41685 -#define PBF_REG_BTB_GUARANTEED_VOQ17_RT_OFFSET 41686 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ17_RT_OFFSET 41687 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ18_RT_OFFSET 41688 -#define PBF_REG_BTB_GUARANTEED_VOQ18_RT_OFFSET 41689 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ18_RT_OFFSET 41690 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ19_RT_OFFSET 41691 -#define PBF_REG_BTB_GUARANTEED_VOQ19_RT_OFFSET 41692 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ19_RT_OFFSET 41693 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ20_RT_OFFSET 41694 -#define PBF_REG_BTB_GUARANTEED_VOQ20_RT_OFFSET 41695 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ20_RT_OFFSET 41696 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ21_RT_OFFSET 41697 -#define PBF_REG_BTB_GUARANTEED_VOQ21_RT_OFFSET 41698 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ21_RT_OFFSET 41699 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ22_RT_OFFSET 41700 -#define PBF_REG_BTB_GUARANTEED_VOQ22_RT_OFFSET 41701 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ22_RT_OFFSET 41702 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ23_RT_OFFSET 41703 -#define PBF_REG_BTB_GUARANTEED_VOQ23_RT_OFFSET 41704 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ23_RT_OFFSET 41705 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ24_RT_OFFSET 41706 -#define PBF_REG_BTB_GUARANTEED_VOQ24_RT_OFFSET 41707 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ24_RT_OFFSET 41708 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ25_RT_OFFSET 41709 -#define PBF_REG_BTB_GUARANTEED_VOQ25_RT_OFFSET 41710 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ25_RT_OFFSET 41711 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ26_RT_OFFSET 41712 -#define PBF_REG_BTB_GUARANTEED_VOQ26_RT_OFFSET 41713 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ26_RT_OFFSET 41714 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ27_RT_OFFSET 41715 -#define PBF_REG_BTB_GUARANTEED_VOQ27_RT_OFFSET 41716 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ27_RT_OFFSET 41717 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ28_RT_OFFSET 41718 -#define PBF_REG_BTB_GUARANTEED_VOQ28_RT_OFFSET 41719 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ28_RT_OFFSET 41720 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ29_RT_OFFSET 41721 -#define PBF_REG_BTB_GUARANTEED_VOQ29_RT_OFFSET 41722 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ29_RT_OFFSET 41723 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ30_RT_OFFSET 41724 -#define PBF_REG_BTB_GUARANTEED_VOQ30_RT_OFFSET 41725 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ30_RT_OFFSET 41726 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ31_RT_OFFSET 41727 -#define PBF_REG_BTB_GUARANTEED_VOQ31_RT_OFFSET 41728 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ31_RT_OFFSET 41729 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ32_RT_OFFSET 41730 -#define PBF_REG_BTB_GUARANTEED_VOQ32_RT_OFFSET 41731 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ32_RT_OFFSET 41732 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ33_RT_OFFSET 41733 -#define PBF_REG_BTB_GUARANTEED_VOQ33_RT_OFFSET 41734 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ33_RT_OFFSET 41735 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ34_RT_OFFSET 41736 -#define PBF_REG_BTB_GUARANTEED_VOQ34_RT_OFFSET 41737 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ34_RT_OFFSET 41738 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ35_RT_OFFSET 41739 -#define PBF_REG_BTB_GUARANTEED_VOQ35_RT_OFFSET 41740 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ35_RT_OFFSET 41741 -#define XCM_REG_CON_PHY_Q3_RT_OFFSET 41742 +#define CDU_REG_CID_ADDR_PARAMS_RT_OFFSET 42899 +#define CDU_REG_SEGMENT0_PARAMS_RT_OFFSET 42900 +#define CDU_REG_SEGMENT1_PARAMS_RT_OFFSET 42901 +#define CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET 42902 +#define CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET 42903 +#define CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET 42904 +#define CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET 42905 +#define CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET 42906 +#define CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET 42907 +#define CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET 42908 +#define CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET 42909 +#define CDU_REG_VF_SEG_TYPE_OFFSET_RT_OFFSET 42910 +#define CDU_REG_VF_FL_SEG_TYPE_OFFSET_RT_OFFSET 42911 +#define PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET 42912 +#define PBF_REG_BTB_SHARED_AREA_SIZE_RT_OFFSET 42913 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET 42914 +#define PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET 42915 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ0_RT_OFFSET 42916 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ1_RT_OFFSET 42917 +#define PBF_REG_BTB_GUARANTEED_VOQ1_RT_OFFSET 42918 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ1_RT_OFFSET 42919 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ2_RT_OFFSET 42920 +#define PBF_REG_BTB_GUARANTEED_VOQ2_RT_OFFSET 42921 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ2_RT_OFFSET 42922 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ3_RT_OFFSET 42923 +#define PBF_REG_BTB_GUARANTEED_VOQ3_RT_OFFSET 42924 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ3_RT_OFFSET 42925 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ4_RT_OFFSET 42926 +#define PBF_REG_BTB_GUARANTEED_VOQ4_RT_OFFSET 42927 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ4_RT_OFFSET 42928 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ5_RT_OFFSET 42929 +#define PBF_REG_BTB_GUARANTEED_VOQ5_RT_OFFSET 42930 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ5_RT_OFFSET 42931 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ6_RT_OFFSET 42932 +#define PBF_REG_BTB_GUARANTEED_VOQ6_RT_OFFSET 42933 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ6_RT_OFFSET 42934 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ7_RT_OFFSET 42935 +#define PBF_REG_BTB_GUARANTEED_VOQ7_RT_OFFSET 42936 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ7_RT_OFFSET 42937 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ8_RT_OFFSET 42938 +#define PBF_REG_BTB_GUARANTEED_VOQ8_RT_OFFSET 42939 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ8_RT_OFFSET 42940 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ9_RT_OFFSET 42941 +#define PBF_REG_BTB_GUARANTEED_VOQ9_RT_OFFSET 42942 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ9_RT_OFFSET 42943 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ10_RT_OFFSET 42944 +#define PBF_REG_BTB_GUARANTEED_VOQ10_RT_OFFSET 42945 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ10_RT_OFFSET 42946 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ11_RT_OFFSET 42947 +#define PBF_REG_BTB_GUARANTEED_VOQ11_RT_OFFSET 42948 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ11_RT_OFFSET 42949 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ12_RT_OFFSET 42950 +#define PBF_REG_BTB_GUARANTEED_VOQ12_RT_OFFSET 42951 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ12_RT_OFFSET 42952 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ13_RT_OFFSET 42953 +#define PBF_REG_BTB_GUARANTEED_VOQ13_RT_OFFSET 42954 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ13_RT_OFFSET 42955 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ14_RT_OFFSET 42956 +#define PBF_REG_BTB_GUARANTEED_VOQ14_RT_OFFSET 42957 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ14_RT_OFFSET 42958 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ15_RT_OFFSET 42959 +#define PBF_REG_BTB_GUARANTEED_VOQ15_RT_OFFSET 42960 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ15_RT_OFFSET 42961 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ16_RT_OFFSET 42962 +#define PBF_REG_BTB_GUARANTEED_VOQ16_RT_OFFSET 42963 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ16_RT_OFFSET 42964 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ17_RT_OFFSET 42965 +#define PBF_REG_BTB_GUARANTEED_VOQ17_RT_OFFSET 42966 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ17_RT_OFFSET 42967 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ18_RT_OFFSET 42968 +#define PBF_REG_BTB_GUARANTEED_VOQ18_RT_OFFSET 42969 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ18_RT_OFFSET 42970 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ19_RT_OFFSET 42971 +#define PBF_REG_BTB_GUARANTEED_VOQ19_RT_OFFSET 42972 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ19_RT_OFFSET 42973 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ20_RT_OFFSET 42974 +#define PBF_REG_BTB_GUARANTEED_VOQ20_RT_OFFSET 42975 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ20_RT_OFFSET 42976 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ21_RT_OFFSET 42977 +#define PBF_REG_BTB_GUARANTEED_VOQ21_RT_OFFSET 42978 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ21_RT_OFFSET 42979 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ22_RT_OFFSET 42980 +#define PBF_REG_BTB_GUARANTEED_VOQ22_RT_OFFSET 42981 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ22_RT_OFFSET 42982 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ23_RT_OFFSET 42983 +#define PBF_REG_BTB_GUARANTEED_VOQ23_RT_OFFSET 42984 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ23_RT_OFFSET 42985 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ24_RT_OFFSET 42986 +#define PBF_REG_BTB_GUARANTEED_VOQ24_RT_OFFSET 42987 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ24_RT_OFFSET 42988 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ25_RT_OFFSET 42989 +#define PBF_REG_BTB_GUARANTEED_VOQ25_RT_OFFSET 42990 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ25_RT_OFFSET 42991 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ26_RT_OFFSET 42992 +#define PBF_REG_BTB_GUARANTEED_VOQ26_RT_OFFSET 42993 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ26_RT_OFFSET 42994 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ27_RT_OFFSET 42995 +#define PBF_REG_BTB_GUARANTEED_VOQ27_RT_OFFSET 42996 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ27_RT_OFFSET 42997 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ28_RT_OFFSET 42998 +#define PBF_REG_BTB_GUARANTEED_VOQ28_RT_OFFSET 42999 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ28_RT_OFFSET 43000 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ29_RT_OFFSET 43001 +#define PBF_REG_BTB_GUARANTEED_VOQ29_RT_OFFSET 43002 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ29_RT_OFFSET 43003 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ30_RT_OFFSET 43004 +#define PBF_REG_BTB_GUARANTEED_VOQ30_RT_OFFSET 43005 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ30_RT_OFFSET 43006 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ31_RT_OFFSET 43007 +#define PBF_REG_BTB_GUARANTEED_VOQ31_RT_OFFSET 43008 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ31_RT_OFFSET 43009 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ32_RT_OFFSET 43010 +#define PBF_REG_BTB_GUARANTEED_VOQ32_RT_OFFSET 43011 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ32_RT_OFFSET 43012 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ33_RT_OFFSET 43013 +#define PBF_REG_BTB_GUARANTEED_VOQ33_RT_OFFSET 43014 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ33_RT_OFFSET 43015 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ34_RT_OFFSET 43016 +#define PBF_REG_BTB_GUARANTEED_VOQ34_RT_OFFSET 43017 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ34_RT_OFFSET 43018 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ35_RT_OFFSET 43019 +#define PBF_REG_BTB_GUARANTEED_VOQ35_RT_OFFSET 43020 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ35_RT_OFFSET 43021 +#define XCM_REG_CON_PHY_Q3_RT_OFFSET 43022 -#define RUNTIME_ARRAY_SIZE 41743 +#define RUNTIME_ARRAY_SIZE 43023 /* Init Callbacks */ #define DMAE_READY_CB 0 diff --git a/drivers/net/qede/base/eth_common.h b/drivers/net/qede/base/eth_common.h index 45a0356..75bad54 100644 --- a/drivers/net/qede/base/eth_common.h +++ b/drivers/net/qede/base/eth_common.h @@ -119,6 +119,9 @@ /* Number of etherType values configured by driver for control frame check */ #define ETH_CTL_FRAME_ETH_TYPE_NUM 4 +/* GFS constants */ +#define ETH_GFT_TRASHCAN_VPORT 0x1FF /* GFT drop flow vport number */ + /* diff --git a/drivers/net/qede/base/reg_addr.h b/drivers/net/qede/base/reg_addr.h index ad15d28..eeb81b6 100644 --- a/drivers/net/qede/base/reg_addr.h +++ b/drivers/net/qede/base/reg_addr.h @@ -1222,3 +1222,5 @@ #define MCP_REG_CPU_STATE_SOFT_HALTED (0x1 << 10) #define PRS_REG_SEARCH_TENANT_ID 0x1f044cUL #define PGLUE_B_REG_VF_BAR1_SIZE 0x2aae68UL + +#define RSS_REG_RSS_RAM_MASK 0x238c10UL diff --git a/drivers/net/qede/qede_main.c b/drivers/net/qede/qede_main.c index ae18732..650f2cf 100644 --- a/drivers/net/qede/qede_main.c +++ b/drivers/net/qede/qede_main.c @@ -19,7 +19,7 @@ char fw_file[PATH_MAX]; const char *QEDE_DEFAULT_FIRMWARE = - "/lib/firmware/qed/qed_init_values-8.30.12.0.bin"; + "/lib/firmware/qed/qed_init_values-8.33.12.0.bin"; static void qed_update_pf_params(struct ecore_dev *edev, struct ecore_pf_params *params) -- 1.7.10.3