From mboxrd@z Thu Jan  1 00:00:00 1970
Return-Path: <zijie.pan@6wind.com>
Received: from mail-wr0-f193.google.com (mail-wr0-f193.google.com
 [209.85.128.193]) by dpdk.org (Postfix) with ESMTP id 60DCA2583
 for <dev@dpdk.org>; Tue, 24 Apr 2018 12:18:05 +0200 (CEST)
Received: by mail-wr0-f193.google.com with SMTP id p5-v6so21399642wre.12
 for <dev@dpdk.org>; Tue, 24 Apr 2018 03:18:05 -0700 (PDT)
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed;
 d=6wind-com.20150623.gappssmtp.com; s=20150623;
 h=from:to:cc:subject:date:message-id:in-reply-to:references;
 bh=VBL1SWjn0hnDjlMGaUukcYB4FwerA0oEIFCHk2vnH6Q=;
 b=t3C5hv+u3L5+giUp5mPa6l8qK5jYV/N7/6G+ahymWwNufUyujXFrVSJ6nZA1FNsAjs
 R9NexQK6kN/6hOGaouz5IOb3S4twirBuldXrY+LUaoZwi4qJBl2bcp4YKXkiyaipTOS0
 FbHoI0v527ALDRU8qvO8AXxdchgv0Eno6wKgwcetfov+YlzAIllsiPthUZHqsv/S8OFK
 BekqiXzWW5rUrvhut4FjWYD3N8AEJobBd36KVL89Az21Dl3pFmYv6Ru2EBlhdM241tZS
 ljhz6johTqMKH1dgNCtFpKVHLtqRfhu4AcD5jBLs6WgpdL3pNhXIDpW5Iyd1kfjHuOGt
 ABKQ==
X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed;
 d=1e100.net; s=20161025;
 h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to
 :references;
 bh=VBL1SWjn0hnDjlMGaUukcYB4FwerA0oEIFCHk2vnH6Q=;
 b=OkmSCl1uyJmdPQdbbiDTsuZWmdItx1sx58Nx0a87ZBwRtc1A1FGsHh4y6AN3LLYc24
 Ge5BDwcuPTc44o/r16/LgIhJw/rj2ywYZW2mkISuKj0/H4P0bOXJf5rdLCahwoqzUkwt
 q+eopN+SxrNTc0N8bhxXTxrxWvfos7nD6Hk+uunCnwvMoHJFTUPoUvN2am1AlALO20VX
 mI03ElLLmhvHc9XAJI3WsZaLBLGMUmx5MQIPmRsQ10Q2V3xZiiwk+A853HCOQK/K+sno
 yW5jb68AjMAcXPSZsycDgvxl4aWowx3UI1YVU+ROqnlVbzdepZVPttRxusQz81BPTCFE
 a1iQ==
X-Gm-Message-State: ALQs6tCoxhW6A1VnQ6T6qYRR2/xE9xC4VUJcZatGo2ol9/LKlY5K/AEG
 Noc58Ud43UI18yE32JweAuWAbOeIfKs=
X-Google-Smtp-Source: AB8JxZoTX6iFomkctMvbo61mrymfvNGEdri4iVuXbpMU3sVjPVUExTQMSKhw2ILa+m4QVk8E/+SCkQ==
X-Received: by 10.28.216.9 with SMTP id p9mr2739092wmg.6.1524565085480;
 Tue, 24 Apr 2018 03:18:05 -0700 (PDT)
Received: from cougar.6wind.com (host.78.145.23.62.rev.coltfrance.com.
 [62.23.145.78])
 by smtp.gmail.com with ESMTPSA id 60-v6sm12564155wrj.62.2018.04.24.03.18.04
 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);
 Tue, 24 Apr 2018 03:18:05 -0700 (PDT)
From: Zijie Pan <zijie.pan@6wind.com>
To: dev@dpdk.org
Cc: remy.horton@intel.com, ferruh.yigit@intel.com, thomas@monjalon.net,
 beilei.xing@intel.com, qi.z.zhang@intel.com
Date: Tue, 24 Apr 2018 12:17:24 +0200
Message-Id: <1524565044-8583-6-git-send-email-zijie.pan@6wind.com>
X-Mailer: git-send-email 1.7.10.4
In-Reply-To: <1524565044-8583-1-git-send-email-zijie.pan@6wind.com>
References: <1521630379-9554-1-git-send-email-zijie.pan@6wind.com>
 <1524565044-8583-1-git-send-email-zijie.pan@6wind.com>
Subject: [dpdk-dev] [PATCH v4 5/5] net/i40e: add module EEPROM callbacks for
	i40e
X-BeenThere: dev@dpdk.org
X-Mailman-Version: 2.1.15
Precedence: list
List-Id: DPDK patches and discussions <dev.dpdk.org>
List-Unsubscribe: <https://dpdk.org/ml/options/dev>,
 <mailto:dev-request@dpdk.org?subject=unsubscribe>
List-Archive: <http://dpdk.org/ml/archives/dev/>
List-Post: <mailto:dev@dpdk.org>
List-Help: <mailto:dev-request@dpdk.org?subject=help>
List-Subscribe: <https://dpdk.org/ml/listinfo/dev>,
 <mailto:dev-request@dpdk.org?subject=subscribe>
X-List-Received-Date: Tue, 24 Apr 2018 10:18:07 -0000

Add new callbacks for eth_dev_ops of i40e to get the information
and data of plugin module eeprom.

Signed-off-by: Zijie Pan <zijie.pan@6wind.com>
Acked-by: Remy Horton <remy.horton@intel.com>
---
Cc: beilei.xing@intel.com
Cc: qi.z.zhang@intel.com

 drivers/net/i40e/i40e_ethdev.c |  147 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 147 insertions(+)

diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c
index 180ac74..1a24cd7 100644
--- a/drivers/net/i40e/i40e_ethdev.c
+++ b/drivers/net/i40e/i40e_ethdev.c
@@ -369,6 +369,11 @@ static int i40e_get_regs(struct rte_eth_dev *dev,
 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 			   struct rte_dev_eeprom_info *eeprom);
 
+static int i40e_get_module_info(struct rte_eth_dev *dev,
+				struct rte_dev_module_info *modinfo);
+static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
+				  struct rte_dev_eeprom_info *info);
+
 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 				      struct ether_addr *mac_addr);
 
@@ -489,6 +494,8 @@ static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 	.get_reg                      = i40e_get_regs,
 	.get_eeprom_length            = i40e_get_eeprom_length,
 	.get_eeprom                   = i40e_get_eeprom,
+	.get_module_info              = i40e_get_module_info,
+	.get_module_eeprom            = i40e_get_module_eeprom,
 	.mac_addr_set                 = i40e_set_default_mac_addr,
 	.mtu_set                      = i40e_dev_mtu_set,
 	.tm_ops_get                   = i40e_tm_ops_get,
@@ -11327,6 +11334,146 @@ static int i40e_get_eeprom(struct rte_eth_dev *dev,
 	return 0;
 }
 
+static int i40e_get_module_info(struct rte_eth_dev *dev,
+				struct rte_dev_module_info *modinfo)
+{
+	struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+	uint32_t sff8472_comp = 0;
+	uint32_t sff8472_swap = 0;
+	uint32_t sff8636_rev = 0;
+	i40e_status status;
+	uint32_t type = 0;
+
+	/* Check if firmware supports reading module EEPROM. */
+	if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) {
+		PMD_DRV_LOG(ERR,
+			    "Module EEPROM memory read not supported. "
+			    "Please update the NVM image.\n");
+		return -EINVAL;
+	}
+
+	status = i40e_update_link_info(hw);
+	if (status)
+		return -EIO;
+
+	if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_EMPTY) {
+		PMD_DRV_LOG(ERR,
+			    "Cannot read module EEPROM memory. "
+			    "No module connected.\n");
+		return -EINVAL;
+	}
+
+	type = hw->phy.link_info.module_type[0];
+
+	switch (type) {
+	case I40E_MODULE_TYPE_SFP:
+		status = i40e_aq_get_phy_register(hw,
+				I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
+				I40E_I2C_EEPROM_DEV_ADDR,
+				I40E_MODULE_SFF_8472_COMP,
+				&sff8472_comp, NULL);
+		if (status)
+			return -EIO;
+
+		status = i40e_aq_get_phy_register(hw,
+				I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
+				I40E_I2C_EEPROM_DEV_ADDR,
+				I40E_MODULE_SFF_8472_SWAP,
+				&sff8472_swap, NULL);
+		if (status)
+			return -EIO;
+
+		/* Check if the module requires address swap to access
+		 * the other EEPROM memory page.
+		 */
+		if (sff8472_swap & I40E_MODULE_SFF_ADDR_MODE) {
+			PMD_DRV_LOG(WARNING,
+				    "Module address swap to access "
+				    "page 0xA2 is not supported.\n");
+			modinfo->type = RTE_ETH_MODULE_SFF_8079;
+			modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
+		} else if (sff8472_comp == 0x00) {
+			/* Module is not SFF-8472 compliant */
+			modinfo->type = RTE_ETH_MODULE_SFF_8079;
+			modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
+		} else {
+			modinfo->type = RTE_ETH_MODULE_SFF_8472;
+			modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
+		}
+		break;
+	case I40E_MODULE_TYPE_QSFP_PLUS:
+		/* Read from memory page 0. */
+		status = i40e_aq_get_phy_register(hw,
+				I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
+				0,
+				I40E_MODULE_REVISION_ADDR,
+				&sff8636_rev, NULL);
+		if (status)
+			return -EIO;
+		/* Determine revision compliance byte */
+		if (sff8636_rev > 0x02) {
+			/* Module is SFF-8636 compliant */
+			modinfo->type = RTE_ETH_MODULE_SFF_8636;
+			modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
+		} else {
+			modinfo->type = RTE_ETH_MODULE_SFF_8436;
+			modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
+		}
+		break;
+	case I40E_MODULE_TYPE_QSFP28:
+		modinfo->type = RTE_ETH_MODULE_SFF_8636;
+		modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
+		break;
+	default:
+		PMD_DRV_LOG(ERR, "Module type unrecognized\n");
+		return -EINVAL;
+	}
+	return 0;
+}
+
+static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
+				  struct rte_dev_eeprom_info *info)
+{
+	struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+	bool is_sfp = false;
+	i40e_status status;
+	uint8_t *data = info->data;
+	uint32_t value = 0;
+	uint32_t i;
+
+	if (!info || !info->length || !data)
+		return -EINVAL;
+
+	if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP)
+		is_sfp = true;
+
+	for (i = 0; i < info->length; i++) {
+		u32 offset = i + info->offset;
+		u32 addr = is_sfp ? I40E_I2C_EEPROM_DEV_ADDR : 0;
+
+		/* Check if we need to access the other memory page */
+		if (is_sfp) {
+			if (offset >= RTE_ETH_MODULE_SFF_8079_LEN) {
+				offset -= RTE_ETH_MODULE_SFF_8079_LEN;
+				addr = I40E_I2C_EEPROM_DEV_ADDR2;
+			}
+		} else {
+			while (offset >= RTE_ETH_MODULE_SFF_8436_LEN) {
+				/* Compute memory page number and offset. */
+				offset -= RTE_ETH_MODULE_SFF_8436_LEN / 2;
+				addr++;
+			}
+		}
+		status = i40e_aq_get_phy_register(hw,
+				I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
+				addr, offset, &value, NULL);
+		if (status)
+			return -EIO;
+		data[i] = (uint8_t)value;
+	}
+	return 0;
+}
+
 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 				     struct ether_addr *mac_addr)
 {
-- 
1.7.10.4