From: "Xu, Rosen" <rosen.xu@intel.com>
To: dev@dpdk.org
Cc: declan.doherty@intel.com, bruce.richardson@intel.com,
shreyansh.jain@nxp.com, ferruh.yigit@intel.com,
konstantin.ananyev@intel.com, tianfei.zhang@intel.com,
hao.wu@intel.com, gaetan.rivet@6wind.com, "Xu,
Rosen" <rosen.xu@intel.com>
Subject: [dpdk-dev] [PATCH v6 0/5] Introduce Intel FPGA BUS
Date: Thu, 26 Apr 2018 17:43:08 +0800 [thread overview]
Message-ID: <1524735793-37302-1-git-send-email-rosen.xu@intel.com> (raw)
In-Reply-To: <1521553556-62982-1-git-send-email-rosen.xu@intel.com>
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset=y, Size: 8996 bytes --]
From: "Xu, Rosen" <rosen.xu@intel.com>
Intel FPGA BUS in DPDK
-------------------------
This patch set introduces Intel FPGA BUS support in DPDK.
v6 updates:
===========
- Add documentation
- Add meson build script
- Split new patch for OPAE share code
v5 updates:
===========
- Fixed SHARED LIB Build issue
- Changed command name to IFPGA Rawdev name,
so remove pci library datastruct and function.
- Fixed PATCH v2/v3/v4 comments
v4 updates:
===========
- Remove all modifications from eal
- Create vdev to take IFPGA parameters configuration
- AFU Device Driver bind to AFU Device by uuid
- Take more test in scenario of Multi-FPGA System
v3 updates:
===========
- Remove all modifications of bus scan and probe
- FPGA BUS Scan is trigged by hotplug of Rawdev
- Took Modifications of comments
- Move AFU Device to IFPGA
- FPGA BUS Scan depend on it¡¯s IFPGA Rawdev
- Add Build Macros for FPGA BUS and IFPGA Rawdev
Questions
=========
Why not PCI Bus?
All of the AFUs of one FPGA may share same PCI BDF.
Why not vdev Bus?
Because AFUs depend on Rawdev, and it's hardware specpic.
Motivation
==========
FPGA is used more and more widely in Cloud and NFV, one primary reason is
that FPGA not only provide ASIC performance but also it's more flexible
than ASIC. FPGA use Partial Reconfigure(PR) Parts of Bitstream to achieve
its flexibility. Another reason is that one FPGA can be shared
by different Users, and each User can use some of AFUs of One FPGA.
That means One FPGA Device Bitstream is divided into many Parts of
Bitstream(each Part of Bitstream is defined as AFU-Accelerated
Function Unit), and each AFU is a Hardware Acceleration Unit and
it can dynamically Reload respectively.
Proposed Solution
=================
- Involve Rawdev to take FPGA Partial Configuration(Download/PR)
- Defined FPGA-BUS for Acceleration Drivers of AFUs
- FPGA PCI Scan(1st Scan) follows DPDK UIO/VFIO PCI Scan Process,
probe Intel FPGA Rawdev Driver. FPGA-BUS scan is called, but AFU
depend on Rawdev, so this scan doesn't trig AFU device create.
- AFU Scan(2nd Scan) bind DPDK Driver to FPGA Partial-Bitstream.
This scan is trigged by hotplug of IFPGA Rawdev probe, in this
scan the AFUs will be created and their dirves are also probed.
Scope
=====
The Intel FPGA BUS implementation is target towards various FPGA Devices
use PR to provide many Acceleration Function. Specific PMDs may also
bind to its AFU. And Applications don't care they are using ASIC
Acceleration or FPGA AFU Acceleration.
Status
=====
With integrating Intel PSG FPGA Software Stack OPAE(Open Programmable
Acceleration Engine) Share Code, Intel FPGA BUS runs well in
Intel PSG FPGA Cards.
Figo Zhang (2):
iFPGA: add meson build
iFPGA: add document for iFPGA driver
Rosen Xu (3):
iFPGA: Add Intel FPGA BUS Library
iFPGA: Add Intel FPGA OPAE Share Code
iFPGA: Add Intel FPGA BUS Rawdev Driver
config/common_base | 6 +
doc/guides/index.rst | 1 +
doc/guides/rawdevs/ifpga_rawdev.rst | 112 ++
doc/guides/rawdevs/index.rst | 11 +
doc/guides/rel_notes/release_18_05.rst | 13 +
drivers/bus/Makefile | 1 +
drivers/bus/ifpga/Makefile | 32 +
drivers/bus/ifpga/ifpga_bus.c | 503 ++++++
drivers/bus/ifpga/ifpga_common.c | 88 ++
drivers/bus/ifpga/ifpga_common.h | 18 +
drivers/bus/ifpga/ifpga_logs.h | 31 +
drivers/bus/ifpga/meson.build | 6 +
drivers/bus/ifpga/rte_bus_ifpga.h | 168 ++
drivers/bus/ifpga/rte_bus_ifpga_version.map | 10 +
drivers/bus/meson.build | 2 +-
drivers/meson.build | 3 +-
drivers/raw/Makefile | 1 +
drivers/raw/ifpga_rawdev/Makefile | 36 +
drivers/raw/ifpga_rawdev/base/Makefile | 26 +
drivers/raw/ifpga_rawdev/base/README | 31 +
drivers/raw/ifpga_rawdev/base/ifpga_api.c | 294 ++++
drivers/raw/ifpga_rawdev/base/ifpga_api.h | 28 +
drivers/raw/ifpga_rawdev/base/ifpga_compat.h | 57 +
drivers/raw/ifpga_rawdev/base/ifpga_defines.h | 1661 ++++++++++++++++++++
drivers/raw/ifpga_rawdev/base/ifpga_enumerate.c | 824 ++++++++++
drivers/raw/ifpga_rawdev/base/ifpga_enumerate.h | 11 +
drivers/raw/ifpga_rawdev/base/ifpga_feature_dev.c | 314 ++++
drivers/raw/ifpga_rawdev/base/ifpga_feature_dev.h | 164 ++
drivers/raw/ifpga_rawdev/base/ifpga_fme.c | 734 +++++++++
drivers/raw/ifpga_rawdev/base/ifpga_fme_dperf.c | 301 ++++
drivers/raw/ifpga_rawdev/base/ifpga_fme_error.c | 403 +++++
drivers/raw/ifpga_rawdev/base/ifpga_fme_iperf.c | 715 +++++++++
drivers/raw/ifpga_rawdev/base/ifpga_fme_pr.c | 372 +++++
drivers/raw/ifpga_rawdev/base/ifpga_hw.h | 127 ++
drivers/raw/ifpga_rawdev/base/ifpga_port.c | 408 +++++
drivers/raw/ifpga_rawdev/base/ifpga_port_error.c | 165 ++
drivers/raw/ifpga_rawdev/base/meson.build | 34 +
drivers/raw/ifpga_rawdev/base/opae_debug.c | 99 ++
drivers/raw/ifpga_rawdev/base/opae_debug.h | 19 +
drivers/raw/ifpga_rawdev/base/opae_hw_api.c | 381 +++++
drivers/raw/ifpga_rawdev/base/opae_hw_api.h | 253 +++
drivers/raw/ifpga_rawdev/base/opae_ifpga_hw_api.c | 145 ++
drivers/raw/ifpga_rawdev/base/opae_ifpga_hw_api.h | 279 ++++
drivers/raw/ifpga_rawdev/base/opae_osdep.h | 81 +
.../ifpga_rawdev/base/osdep_raw/osdep_generic.h | 75 +
.../ifpga_rawdev/base/osdep_rte/osdep_generic.h | 45 +
drivers/raw/ifpga_rawdev/ifpga_rawdev.c | 597 +++++++
drivers/raw/ifpga_rawdev/ifpga_rawdev.h | 37 +
drivers/raw/ifpga_rawdev/meson.build | 13 +
.../raw/ifpga_rawdev/rte_ifpga_rawdev_version.map | 4 +
drivers/raw/meson.build | 6 +
mk/rte.app.mk | 3 +
52 files changed, 9746 insertions(+), 2 deletions(-)
create mode 100644 doc/guides/rawdevs/ifpga_rawdev.rst
create mode 100644 doc/guides/rawdevs/index.rst
create mode 100644 drivers/bus/ifpga/Makefile
create mode 100644 drivers/bus/ifpga/ifpga_bus.c
create mode 100644 drivers/bus/ifpga/ifpga_common.c
create mode 100644 drivers/bus/ifpga/ifpga_common.h
create mode 100644 drivers/bus/ifpga/ifpga_logs.h
create mode 100644 drivers/bus/ifpga/meson.build
create mode 100644 drivers/bus/ifpga/rte_bus_ifpga.h
create mode 100644 drivers/bus/ifpga/rte_bus_ifpga_version.map
create mode 100644 drivers/raw/ifpga_rawdev/Makefile
create mode 100644 drivers/raw/ifpga_rawdev/base/Makefile
create mode 100644 drivers/raw/ifpga_rawdev/base/README
create mode 100644 drivers/raw/ifpga_rawdev/base/ifpga_api.c
create mode 100644 drivers/raw/ifpga_rawdev/base/ifpga_api.h
create mode 100644 drivers/raw/ifpga_rawdev/base/ifpga_compat.h
create mode 100644 drivers/raw/ifpga_rawdev/base/ifpga_defines.h
create mode 100644 drivers/raw/ifpga_rawdev/base/ifpga_enumerate.c
create mode 100644 drivers/raw/ifpga_rawdev/base/ifpga_enumerate.h
create mode 100644 drivers/raw/ifpga_rawdev/base/ifpga_feature_dev.c
create mode 100644 drivers/raw/ifpga_rawdev/base/ifpga_feature_dev.h
create mode 100644 drivers/raw/ifpga_rawdev/base/ifpga_fme.c
create mode 100644 drivers/raw/ifpga_rawdev/base/ifpga_fme_dperf.c
create mode 100644 drivers/raw/ifpga_rawdev/base/ifpga_fme_error.c
create mode 100644 drivers/raw/ifpga_rawdev/base/ifpga_fme_iperf.c
create mode 100644 drivers/raw/ifpga_rawdev/base/ifpga_fme_pr.c
create mode 100644 drivers/raw/ifpga_rawdev/base/ifpga_hw.h
create mode 100644 drivers/raw/ifpga_rawdev/base/ifpga_port.c
create mode 100644 drivers/raw/ifpga_rawdev/base/ifpga_port_error.c
create mode 100644 drivers/raw/ifpga_rawdev/base/meson.build
create mode 100644 drivers/raw/ifpga_rawdev/base/opae_debug.c
create mode 100644 drivers/raw/ifpga_rawdev/base/opae_debug.h
create mode 100644 drivers/raw/ifpga_rawdev/base/opae_hw_api.c
create mode 100644 drivers/raw/ifpga_rawdev/base/opae_hw_api.h
create mode 100644 drivers/raw/ifpga_rawdev/base/opae_ifpga_hw_api.c
create mode 100644 drivers/raw/ifpga_rawdev/base/opae_ifpga_hw_api.h
create mode 100644 drivers/raw/ifpga_rawdev/base/opae_osdep.h
create mode 100644 drivers/raw/ifpga_rawdev/base/osdep_raw/osdep_generic.h
create mode 100644 drivers/raw/ifpga_rawdev/base/osdep_rte/osdep_generic.h
create mode 100644 drivers/raw/ifpga_rawdev/ifpga_rawdev.c
create mode 100644 drivers/raw/ifpga_rawdev/ifpga_rawdev.h
create mode 100644 drivers/raw/ifpga_rawdev/meson.build
create mode 100644 drivers/raw/ifpga_rawdev/rte_ifpga_rawdev_version.map
create mode 100644 drivers/raw/meson.build
--
1.8.3.1
next prev parent reply other threads:[~2018-04-26 9:41 UTC|newest]
Thread overview: 149+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-03-20 13:45 [dpdk-dev] [PATCH V1 " Rosen Xu
2018-03-20 13:45 ` [dpdk-dev] [PATCH V1 1/5] Add Intel FPGA BUS Command Parse Code Rosen Xu
2018-03-20 13:45 ` [dpdk-dev] [PATCH V1 2/5] Add Intel FPGA BUS Probe Code Rosen Xu
2018-03-20 13:45 ` [dpdk-dev] [PATCH V1 3/5] Add Intel FPGA BUS Lib Code Rosen Xu
2018-03-20 13:45 ` [dpdk-dev] [PATCH V1 4/5] Add Intel FPGA BUS Rawdev Code Rosen Xu
2018-03-20 13:45 ` [dpdk-dev] [PATCH V1 5/5] Add Intel OPAE Share Code Rosen Xu
2018-03-20 14:58 ` [dpdk-dev] [PATCH V1 0/5] Introduce Intel FPGA BUS Gaëtan Rivet
2018-03-28 9:29 ` [dpdk-dev] [PATCH v3 0/6] " Rosen Xu
2018-03-28 9:29 ` [dpdk-dev] [PATCH v3 1/6] Add Intel FPGA BUS Command Parse Code Rosen Xu
2018-03-28 13:26 ` Gaëtan Rivet
2018-03-31 16:25 ` Xu, Rosen
2018-04-04 1:58 ` Xu, Rosen
2018-03-28 9:29 ` [dpdk-dev] [PATCH v3 2/6] config/common_base: Add Intel FPGA Build Configuration Macro Rosen Xu
2018-03-28 13:27 ` Gaëtan Rivet
2018-03-31 16:26 ` Xu, Rosen
2018-04-04 2:01 ` Xu, Rosen
2018-03-28 9:29 ` [dpdk-dev] [PATCH v3 3/6] mk/rte.app.mk: Add Intel FPGA Bus Build Configuration Macro To App Script Rosen Xu
2018-03-28 13:28 ` Gaëtan Rivet
2018-03-31 16:27 ` Xu, Rosen
2018-04-04 2:02 ` Xu, Rosen
2018-03-28 9:29 ` [dpdk-dev] [PATCH v3 4/6] drivers/bus: Add Intel FPGA Bus Lib Code Rosen Xu
2018-03-28 13:52 ` Gaëtan Rivet
2018-03-31 16:31 ` Xu, Rosen
2018-04-02 4:25 ` Xu, Rosen
2018-04-02 4:31 ` Xu, Rosen
2018-04-04 4:01 ` Xu, Rosen
2018-03-28 9:29 ` [dpdk-dev] [PATCH v3 5/6] drivers/raw/ifpga_rawdev: Add Intel FPGA Rawdev Driver Code Rosen Xu
2018-03-28 9:29 ` [dpdk-dev] [PATCH v3 6/6] drivers/raw/ifpga_rawdev: Add Intel FPGA OPAE Share Code Rosen Xu
2018-03-28 9:37 ` [dpdk-dev] [PATCH v3 0/6] Introduce Intel FPGA BUS Bruce Richardson
2018-03-28 13:17 ` Gaëtan Rivet
2018-03-28 16:15 ` Zhang, Tianfei
2018-04-04 1:57 ` Xu, Rosen
2018-03-31 16:02 ` [dpdk-dev] [PATCH v4 0/3] " Rosen Xu
2018-03-31 16:03 ` [dpdk-dev] [PATCH v4 1/3] Add Intel FPGA BUS Lib Code Rosen Xu
2018-04-03 9:25 ` Shreyansh Jain
2018-04-04 1:44 ` Xu, Rosen
2018-03-31 16:03 ` [dpdk-dev] [PATCH v4 2/3] Add Intel FPGA BUS Rawdev Driver Rosen Xu
2018-04-03 9:34 ` Shreyansh Jain
2018-04-04 1:49 ` Xu, Rosen
2018-04-04 11:31 ` Shreyansh Jain
2018-04-26 10:47 ` Xu, Rosen
2018-03-31 16:03 ` [dpdk-dev] [PATCH v4 3/3] Add Intel FPGA OPAE Share Code Rosen Xu
2018-04-04 6:51 ` [dpdk-dev] [PATCH v5 0/3] Introduce Intel FPGA BUS Rosen Xu
2018-04-04 6:51 ` [dpdk-dev] [PATCH v5 1/3] Add Intel FPGA BUS Library Rosen Xu
2018-04-04 9:55 ` Bruce Richardson
2018-04-04 6:51 ` [dpdk-dev] [PATCH v5 2/3] Add Intel FPGA BUS Rawdev Driver Rosen Xu
2018-04-04 6:51 ` [dpdk-dev] [PATCH v5 3/3] Add Intel FPGA OPAE Share Code Rosen Xu
2018-04-04 11:59 ` Hemant Agrawal
2018-04-26 10:45 ` Xu, Rosen
2018-04-04 10:14 ` [dpdk-dev] [PATCH v5 0/3] Introduce Intel FPGA BUS Shreyansh Jain
2018-04-04 10:38 ` Richardson, Bruce
2018-04-04 11:11 ` Shreyansh Jain
2018-04-26 9:43 ` Xu, Rosen [this message]
2018-04-26 9:43 ` [dpdk-dev] [PATCH v6 1/5] iFPGA: Add Intel FPGA BUS Library Xu, Rosen
2018-05-02 13:14 ` Shreyansh Jain
2018-05-02 13:33 ` Zhang, Tianfei
2018-05-03 3:58 ` Tan, Jianfeng
2018-05-03 8:12 ` Tan, Jianfeng
2018-05-03 8:35 ` Zhang, Tianfei
2018-04-26 9:43 ` [dpdk-dev] [PATCH v6 2/5] iFPGA: Add Intel FPGA OPAE Share Code Xu, Rosen
2018-04-26 9:43 ` [dpdk-dev] [PATCH v6 3/5] iFPGA: Add Intel FPGA BUS Rawdev Driver Xu, Rosen
2018-05-04 9:14 ` Shreyansh Jain
2018-05-04 9:04 ` Zhang, Tianfei
2018-04-26 9:43 ` [dpdk-dev] [PATCH v6 4/5] iFPGA: add meson build Xu, Rosen
2018-05-02 9:46 ` Shreyansh Jain
2018-05-02 13:36 ` Zhang, Tianfei
2018-05-03 9:13 ` Shreyansh Jain
2018-05-03 15:12 ` Zhang, Tianfei
2018-04-26 9:43 ` [dpdk-dev] [PATCH v6 5/5] iFPGA: add document for iFPGA driver Xu, Rosen
2018-05-04 14:10 ` [dpdk-dev] [PATCH v7 0/5] Introduce Intel FPGA BUS Xu, Rosen
2018-05-04 14:10 ` [dpdk-dev] [PATCH v7 1/5] bus/ifpga: Add Intel FPGA BUS Library Xu, Rosen
2018-05-04 14:10 ` [dpdk-dev] [PATCH v7 2/5] iFPGA: Add Intel FPGA OPAE Share Code Xu, Rosen
2018-05-04 14:11 ` [dpdk-dev] [PATCH v7 3/5] iFPGA: Add Intel FPGA BUS Rawdev Driver Xu, Rosen
2018-05-05 18:42 ` Shreyansh Jain
2018-05-06 0:28 ` Zhang, Tianfei
2018-05-05 19:09 ` Shreyansh Jain
2018-05-06 0:52 ` Zhang, Tianfei
2018-05-04 14:11 ` [dpdk-dev] [PATCH v7 4/5] iFPGA: add meson build Xu, Rosen
2018-05-05 18:21 ` Shreyansh Jain
2018-05-06 0:27 ` Zhang, Tianfei
2018-05-04 14:11 ` [dpdk-dev] [PATCH v7 5/5] iFPGA: add document for iFPGA driver Xu, Rosen
2018-05-05 19:19 ` Shreyansh Jain
2018-05-06 8:40 ` [dpdk-dev] [PATCH v8 0/5] Introduce Intel FPGA BUS Xu, Rosen
2018-05-06 8:40 ` [dpdk-dev] [PATCH v8 1/5] bus/ifpga: Add Intel FPGA BUS Library Xu, Rosen
2018-05-06 8:40 ` [dpdk-dev] [PATCH v8 2/5] iFPGA: Add Intel FPGA OPAE Share Code Xu, Rosen
2018-05-06 8:40 ` [dpdk-dev] [PATCH v8 3/5] iFPGA: Add Intel FPGA BUS Rawdev Driver Xu, Rosen
2018-05-06 8:40 ` [dpdk-dev] [PATCH v8 4/5] iFPGA: add meson build Xu, Rosen
2018-05-06 8:40 ` [dpdk-dev] [PATCH v8 5/5] iFPGA: add document for iFPGA driver Xu, Rosen
2018-05-06 11:54 ` Shreyansh Jain
2018-05-06 14:24 ` Zhang, Tianfei
2018-05-08 14:18 ` [dpdk-dev] [PATCH v9 0/4] Introduce Intel FPGA BUS Xu, Rosen
2018-05-08 14:19 ` [dpdk-dev] [PATCH v9 1/4] bus/ifpga: Add Intel FPGA BUS Library Xu, Rosen
2018-05-08 14:42 ` Thomas Monjalon
2018-05-09 1:25 ` Xu, Rosen
2018-05-08 14:19 ` [dpdk-dev] [PATCH v9 2/4] iFPGA: Add Intel FPGA OPAE Share Code Xu, Rosen
2018-05-08 14:45 ` Thomas Monjalon
2018-05-09 1:24 ` Xu, Rosen
2018-05-08 14:19 ` [dpdk-dev] [PATCH v9 3/4] iFPGA: Add Intel FPGA BUS Rawdev Driver Xu, Rosen
2018-05-08 14:19 ` [dpdk-dev] [PATCH v9 4/4] iFPGA: add document for iFPGA driver Xu, Rosen
2018-05-08 14:49 ` Thomas Monjalon
2018-05-09 7:43 ` [dpdk-dev] [PATCH v10 0/3] Introduce Intel FPGA BUS Xu, Rosen
2018-05-09 7:43 ` [dpdk-dev] [PATCH v10 1/3] bus/ifpga: Add Intel FPGA BUS Library Xu, Rosen
2018-05-10 8:43 ` Wu, Jingjing
2018-05-10 12:20 ` Xu, Rosen
2018-05-10 22:39 ` Wu, Jingjing
2018-05-11 3:18 ` Xu, Rosen
2018-05-10 12:26 ` Zhang, Qi Z
2018-05-10 13:29 ` Xu, Rosen
2018-05-10 13:48 ` Zhang, Qi Z
2018-05-10 13:58 ` Xu, Rosen
2018-05-10 14:11 ` Zhang, Qi Z
2018-05-10 13:51 ` Xu, Rosen
2018-05-10 13:58 ` Zhang, Qi Z
2018-05-10 14:49 ` Thomas Monjalon
2018-05-09 7:43 ` [dpdk-dev] [PATCH v10 2/3] iFPGA: Add Intel FPGA OPAE Share Code Xu, Rosen
2018-05-09 7:43 ` [dpdk-dev] [PATCH v10 3/3] iFPGA: Add Intel FPGA BUS Rawdev Driver Xu, Rosen
2018-05-09 14:47 ` Thomas Monjalon
2018-05-09 15:33 ` Zhang, Tianfei
2018-05-09 15:37 ` Bruce Richardson
2018-05-09 15:57 ` Zhang, Tianfei
2018-05-10 13:31 ` Xu, Rosen
2018-05-10 9:21 ` Wu, Jingjing
2018-05-10 13:16 ` Xu, Rosen
2018-05-11 3:21 ` Xu, Rosen
2018-05-10 14:24 ` Zhang, Qi Z
2018-05-11 3:16 ` Xu, Rosen
2018-05-11 5:36 ` Zhang, Qi Z
2018-05-10 14:00 ` [dpdk-dev] [PATCH v11 0/3] Introduce Intel FPGA BUS Xu, Rosen
2018-05-10 14:00 ` [dpdk-dev] [PATCH v11 1/3] bus/ifpga: Add Intel FPGA BUS Library Xu, Rosen
2018-05-10 14:00 ` [dpdk-dev] [PATCH v11 2/3] iFPGA: Add Intel FPGA OPAE Share Code Xu, Rosen
2018-05-10 14:00 ` [dpdk-dev] [PATCH v11 3/3] iFPGA: Add Intel FPGA BUS Rawdev Driver Xu, Rosen
2018-05-11 8:31 ` [dpdk-dev] [PATCH v12 0/3] Introduce Intel FPGA BUS Xu, Rosen
2018-05-11 8:31 ` [dpdk-dev] [PATCH v12 1/3] bus/ifpga: Add Intel FPGA BUS Library Xu, Rosen
2018-05-11 8:31 ` [dpdk-dev] [PATCH v12 2/3] iFPGA: Add Intel FPGA OPAE Share Code Xu, Rosen
2018-05-11 8:31 ` [dpdk-dev] [PATCH v12 3/3] iFPGA: Add Intel FPGA BUS Rawdev Driver Xu, Rosen
2018-05-11 12:11 ` [dpdk-dev] [PATCH v12 0/3] Introduce Intel FPGA BUS Zhang, Qi Z
2018-05-11 13:45 ` Xu, Rosen
2018-05-11 15:12 ` Thomas Monjalon
2018-05-14 9:58 ` [dpdk-dev] [PATCH] raw/ifpga/base: fix compile error on ia32 icc compiler Xu, Rosen
2018-05-14 10:20 ` De Lara Guarch, Pablo
2018-05-14 10:32 ` Thomas Monjalon
2018-05-16 13:48 ` [dpdk-dev] [PATCH] drivers/bus/ifpga/: fix Coverity issue Rosen Xu
2018-05-21 14:00 ` [dpdk-dev] [dpdk-stable] " Thomas Monjalon
2018-05-22 10:26 ` [dpdk-dev] [PATCH v2 0/3] Fix bus/ifpga coverity issue: 279455, 279459 and 279454 Rosen Xu
2018-05-22 10:26 ` [dpdk-dev] [PATCH v2 1/3] bus/ifpga: fix error control flow issue Rosen Xu
2018-05-22 10:26 ` [dpdk-dev] [PATCH v2 2/3] bus/ifpga: fix resource leaks issue Rosen Xu
2018-05-22 10:26 ` [dpdk-dev] [PATCH v2 3/3] bus/ifpga: fix null pointer dereferences issue Rosen Xu
2018-05-22 15:15 ` [dpdk-dev] [PATCH v2 0/3] Fix bus/ifpga coverity issue: 279455, 279459 and 279454 Thomas Monjalon
2018-05-23 0:26 ` Xu, Rosen
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1524735793-37302-1-git-send-email-rosen.xu@intel.com \
--to=rosen.xu@intel.com \
--cc=bruce.richardson@intel.com \
--cc=declan.doherty@intel.com \
--cc=dev@dpdk.org \
--cc=ferruh.yigit@intel.com \
--cc=gaetan.rivet@6wind.com \
--cc=hao.wu@intel.com \
--cc=konstantin.ananyev@intel.com \
--cc=shreyansh.jain@nxp.com \
--cc=tianfei.zhang@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).