From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by dpdk.org (Postfix) with ESMTP id 701568E78 for ; Wed, 9 May 2018 09:42:04 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 09 May 2018 00:42:03 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.49,381,1520924400"; d="scan'208";a="226990328" Received: from dpdkx8602.sh.intel.com ([10.67.110.200]) by fmsmga005.fm.intel.com with ESMTP; 09 May 2018 00:42:01 -0700 From: "Xu, Rosen" To: dev@dpdk.org, thomas@monjalon.net Cc: rosen.xu@intel.com, roy.fan.zhang@intel.com, declan.doherty@intel.com, bruce.richardson@intel.com, shreyansh.jain@nxp.com, ferruh.yigit@intel.com, konstantin.ananyev@intel.com, tianfei.zhang@intel.com, song.liu@intel.com, hao.wu@intel.com, gaetan.rivet@6wind.com Date: Wed, 9 May 2018 15:43:18 +0800 Message-Id: <1525851801-16101-1-git-send-email-rosen.xu@intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1521553556-62982-1-git-send-email-rosen.xu@intel.com> References: <1521553556-62982-1-git-send-email-rosen.xu@intel.com> Subject: [dpdk-dev] [PATCH v10 0/3] Introduce Intel FPGA BUS X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 09 May 2018 07:42:05 -0000 From: "Xu, Rosen" Intel FPGA BUS in DPDK ------------------------- This patch set introduces Intel FPGA BUS support in DPDK. v10 updates: =========== - Add prefix rte_ for exported symbols - Fix alphabetical order error - Fix share code title well underlined comments - Squash the release notes parts in relevant patches - Update the MAINTAINERS file in patches 1, 2 and 3 v9 updates: ========== - Rebase ifpga_rawdev on QDMA and CMDIF driver - Split and squash the patch 4(v8 patch) into patch 2 and patch 3 v8 updates: ========== - Fix some comments from Shreyansh Jain - Patch 3 and Patch 5 will continue rebase when qcom patches merging into mainline - add Shreyansh Jain's Acked-by v7 updates: ========== - Fix some comments from DPDK community - Fix the CLANG compile error - Fix the meson build warring. v6 updates: =========== - Add documentation - Add meson build script - Split new patch for OPAE share code v5 updates: =========== - Fixed SHARED LIB Build issue - Changed command name to IFPGA Rawdev name, so remove pci library datastruct and function. - Fixed PATCH v2/v3/v4 comments v4 updates: =========== - Remove all modifications from eal - Create vdev to take IFPGA parameters configuration - AFU Device Driver bind to AFU Device by uuid - Take more test in scenario of Multi-FPGA System v3 updates: =========== - Remove all modifications of bus scan and probe - FPGA BUS Scan is trigged by hotplug of Rawdev - Took Modifications of comments - Move AFU Device to IFPGA - FPGA BUS Scan depend on it's IFPGA Rawdev - Add Build Macros for FPGA BUS and IFPGA Rawdev Questions ========= Why not PCI Bus? All of the AFUs of one FPGA may share same PCI BDF. Why not vdev Bus? Because AFUs depend on Rawdev, and it's hardware specpic. Motivation ========== FPGA is used more and more widely in Cloud and NFV, one primary reason is that FPGA not only provide ASIC performance but also it's more flexible than ASIC. FPGA use Partial Reconfigure(PR) Parts of Bitstream to achieve its flexibility. Another reason is that one FPGA can be shared by different Users, and each User can use some of AFUs of One FPGA. That means One FPGA Device Bitstream is divided into many Parts of Bitstream(each Part of Bitstream is defined as AFU-Accelerated Function Unit), and each AFU is a Hardware Acceleration Unit and it can dynamically Reload respectively. Proposed Solution ================= - Involve Rawdev to take FPGA Partial Configuration(Download/PR) - Defined FPGA-BUS for Acceleration Drivers of AFUs - FPGA PCI Scan(1st Scan) follows DPDK UIO/VFIO PCI Scan Process, probe Intel FPGA Rawdev Driver. FPGA-BUS scan is called, but AFU depend on Rawdev, so this scan doesn't trig AFU device create. - AFU Scan(2nd Scan) bind DPDK Driver to FPGA Partial-Bitstream. This scan is trigged by hotplug of IFPGA Rawdev probe, in this scan the AFUs will be created and their dirves are also probed. Scope ===== The Intel FPGA BUS implementation is target towards various FPGA Devices use PR to provide many Acceleration Function. Specific PMDs may also bind to its AFU. And Applications don't care they are using ASIC Acceleration or FPGA AFU Acceleration. Status ===== With integrating Intel PSG FPGA Software Stack OPAE(Open Programmable Acceleration Engine) Share Code, Intel FPGA BUS runs well in Intel PSG FPGA Cards. Rosen Xu (2): bus/ifpga: Add Intel FPGA BUS Library iFPGA: Add Intel FPGA BUS Rawdev Driver Tianfei Zhang (1): iFPGA: Add Intel FPGA OPAE Share Code MAINTAINERS | 11 + config/common_base | 10 + doc/guides/rawdevs/ifpga_rawdev.rst | 112 ++ doc/guides/rawdevs/index.rst | 1 + doc/guides/rel_notes/release_18_05.rst | 13 + drivers/bus/Makefile | 1 + drivers/bus/ifpga/Makefile | 32 + drivers/bus/ifpga/ifpga_bus.c | 501 ++++++ drivers/bus/ifpga/ifpga_common.c | 88 ++ drivers/bus/ifpga/ifpga_common.h | 18 + drivers/bus/ifpga/ifpga_logs.h | 31 + drivers/bus/ifpga/meson.build | 8 + drivers/bus/ifpga/rte_bus_ifpga.h | 160 ++ drivers/bus/ifpga/rte_bus_ifpga_version.map | 10 + drivers/bus/meson.build | 2 +- drivers/raw/Makefile | 1 + drivers/raw/ifpga_rawdev/Makefile | 36 + drivers/raw/ifpga_rawdev/base/Makefile | 30 + drivers/raw/ifpga_rawdev/base/README | 31 + drivers/raw/ifpga_rawdev/base/ifpga_api.c | 294 ++++ drivers/raw/ifpga_rawdev/base/ifpga_api.h | 28 + drivers/raw/ifpga_rawdev/base/ifpga_compat.h | 57 + drivers/raw/ifpga_rawdev/base/ifpga_defines.h | 1661 ++++++++++++++++++++ drivers/raw/ifpga_rawdev/base/ifpga_enumerate.c | 824 ++++++++++ drivers/raw/ifpga_rawdev/base/ifpga_enumerate.h | 11 + drivers/raw/ifpga_rawdev/base/ifpga_feature_dev.c | 314 ++++ drivers/raw/ifpga_rawdev/base/ifpga_feature_dev.h | 164 ++ drivers/raw/ifpga_rawdev/base/ifpga_fme.c | 734 +++++++++ drivers/raw/ifpga_rawdev/base/ifpga_fme_dperf.c | 301 ++++ drivers/raw/ifpga_rawdev/base/ifpga_fme_error.c | 403 +++++ drivers/raw/ifpga_rawdev/base/ifpga_fme_iperf.c | 715 +++++++++ drivers/raw/ifpga_rawdev/base/ifpga_fme_pr.c | 372 +++++ drivers/raw/ifpga_rawdev/base/ifpga_hw.h | 127 ++ drivers/raw/ifpga_rawdev/base/ifpga_port.c | 408 +++++ drivers/raw/ifpga_rawdev/base/ifpga_port_error.c | 165 ++ drivers/raw/ifpga_rawdev/base/meson.build | 34 + drivers/raw/ifpga_rawdev/base/opae_debug.c | 99 ++ drivers/raw/ifpga_rawdev/base/opae_debug.h | 19 + drivers/raw/ifpga_rawdev/base/opae_hw_api.c | 381 +++++ drivers/raw/ifpga_rawdev/base/opae_hw_api.h | 253 +++ drivers/raw/ifpga_rawdev/base/opae_ifpga_hw_api.c | 145 ++ drivers/raw/ifpga_rawdev/base/opae_ifpga_hw_api.h | 279 ++++ drivers/raw/ifpga_rawdev/base/opae_osdep.h | 81 + .../ifpga_rawdev/base/osdep_raw/osdep_generic.h | 75 + .../ifpga_rawdev/base/osdep_rte/osdep_generic.h | 45 + drivers/raw/ifpga_rawdev/ifpga_rawdev.c | 608 +++++++ drivers/raw/ifpga_rawdev/ifpga_rawdev.h | 37 + drivers/raw/ifpga_rawdev/meson.build | 15 + .../ifpga_rawdev/rte_pmd_ifpga_rawdev_version.map | 4 + drivers/raw/meson.build | 2 +- mk/rte.app.mk | 5 +- 51 files changed, 9753 insertions(+), 3 deletions(-) create mode 100644 doc/guides/rawdevs/ifpga_rawdev.rst create mode 100644 drivers/bus/ifpga/Makefile create mode 100644 drivers/bus/ifpga/ifpga_bus.c create mode 100644 drivers/bus/ifpga/ifpga_common.c create mode 100644 drivers/bus/ifpga/ifpga_common.h create mode 100644 drivers/bus/ifpga/ifpga_logs.h create mode 100644 drivers/bus/ifpga/meson.build create mode 100644 drivers/bus/ifpga/rte_bus_ifpga.h create mode 100644 drivers/bus/ifpga/rte_bus_ifpga_version.map create mode 100644 drivers/raw/ifpga_rawdev/Makefile create mode 100644 drivers/raw/ifpga_rawdev/base/Makefile create mode 100644 drivers/raw/ifpga_rawdev/base/README create mode 100644 drivers/raw/ifpga_rawdev/base/ifpga_api.c create mode 100644 drivers/raw/ifpga_rawdev/base/ifpga_api.h create mode 100644 drivers/raw/ifpga_rawdev/base/ifpga_compat.h create mode 100644 drivers/raw/ifpga_rawdev/base/ifpga_defines.h create mode 100644 drivers/raw/ifpga_rawdev/base/ifpga_enumerate.c create mode 100644 drivers/raw/ifpga_rawdev/base/ifpga_enumerate.h create mode 100644 drivers/raw/ifpga_rawdev/base/ifpga_feature_dev.c create mode 100644 drivers/raw/ifpga_rawdev/base/ifpga_feature_dev.h create mode 100644 drivers/raw/ifpga_rawdev/base/ifpga_fme.c create mode 100644 drivers/raw/ifpga_rawdev/base/ifpga_fme_dperf.c create mode 100644 drivers/raw/ifpga_rawdev/base/ifpga_fme_error.c create mode 100644 drivers/raw/ifpga_rawdev/base/ifpga_fme_iperf.c create mode 100644 drivers/raw/ifpga_rawdev/base/ifpga_fme_pr.c create mode 100644 drivers/raw/ifpga_rawdev/base/ifpga_hw.h create mode 100644 drivers/raw/ifpga_rawdev/base/ifpga_port.c create mode 100644 drivers/raw/ifpga_rawdev/base/ifpga_port_error.c create mode 100644 drivers/raw/ifpga_rawdev/base/meson.build create mode 100644 drivers/raw/ifpga_rawdev/base/opae_debug.c create mode 100644 drivers/raw/ifpga_rawdev/base/opae_debug.h create mode 100644 drivers/raw/ifpga_rawdev/base/opae_hw_api.c create mode 100644 drivers/raw/ifpga_rawdev/base/opae_hw_api.h create mode 100644 drivers/raw/ifpga_rawdev/base/opae_ifpga_hw_api.c create mode 100644 drivers/raw/ifpga_rawdev/base/opae_ifpga_hw_api.h create mode 100644 drivers/raw/ifpga_rawdev/base/opae_osdep.h create mode 100644 drivers/raw/ifpga_rawdev/base/osdep_raw/osdep_generic.h create mode 100644 drivers/raw/ifpga_rawdev/base/osdep_rte/osdep_generic.h create mode 100644 drivers/raw/ifpga_rawdev/ifpga_rawdev.c create mode 100644 drivers/raw/ifpga_rawdev/ifpga_rawdev.h create mode 100644 drivers/raw/ifpga_rawdev/meson.build create mode 100644 drivers/raw/ifpga_rawdev/rte_pmd_ifpga_rawdev_version.map -- 1.8.3.1