* Re: [dpdk-dev] [PATCH v2] net/i40e: print original value for global register change
2018-05-11 18:17 ` [dpdk-dev] [PATCH v2] " Beilei Xing
@ 2018-05-11 9:03 ` Zhang, Qi Z
2018-05-11 12:06 ` Ferruh Yigit
0 siblings, 1 reply; 4+ messages in thread
From: Zhang, Qi Z @ 2018-05-11 9:03 UTC (permalink / raw)
To: Xing, Beilei, Wu, Jingjing; +Cc: dev, stable
> -----Original Message-----
> From: Xing, Beilei
> Sent: Saturday, May 12, 2018 2:17 AM
> To: Wu, Jingjing <jingjing.wu@intel.com>; Zhang, Qi Z <qi.z.zhang@intel.com>
> Cc: dev@dpdk.org; stable@dpdk.org
> Subject: [PATCH v2] net/i40e: print original value for global register change
>
> Currently, only new value is printed during global register change. Add original
> value to help debugging facility.
>
> Fixes: bc66b9717c50 ("net/i40e: add debug logs when writing global registers")
> Cc: stable@dpdk.org
>
> Signed-off-by: Beilei Xing <beilei.xing@intel.com>
> ---
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [dpdk-dev] [PATCH v2] net/i40e: print original value for global register change
2018-05-11 9:03 ` Zhang, Qi Z
@ 2018-05-11 12:06 ` Ferruh Yigit
0 siblings, 0 replies; 4+ messages in thread
From: Ferruh Yigit @ 2018-05-11 12:06 UTC (permalink / raw)
To: Zhang, Qi Z, Xing, Beilei, Wu, Jingjing; +Cc: dev, stable
On 5/11/2018 10:03 AM, Zhang, Qi Z wrote:
>> -----Original Message-----
>> From: Xing, Beilei
>> Sent: Saturday, May 12, 2018 2:17 AM
>> To: Wu, Jingjing <jingjing.wu@intel.com>; Zhang, Qi Z <qi.z.zhang@intel.com>
>> Cc: dev@dpdk.org; stable@dpdk.org
>> Subject: [PATCH v2] net/i40e: print original value for global register change
>>
>> Currently, only new value is printed during global register change. Add original
>> value to help debugging facility.
>>
>> Fixes: bc66b9717c50 ("net/i40e: add debug logs when writing global registers")
>> Cc: stable@dpdk.org
>>
>> Signed-off-by: Beilei Xing <beilei.xing@intel.com>
>> ---
>
> Acked-by: Qi Zhang <qi.z.zhang@intel.com>
Applied to dpdk-next-net/master, thanks.
^ permalink raw reply [flat|nested] 4+ messages in thread
* [dpdk-dev] [PATCH] net/i40e: print original value for global register change
@ 2018-05-11 17:35 Beilei Xing
2018-05-11 18:17 ` [dpdk-dev] [PATCH v2] " Beilei Xing
0 siblings, 1 reply; 4+ messages in thread
From: Beilei Xing @ 2018-05-11 17:35 UTC (permalink / raw)
To: jingjing.wu, qi.z.zhang; +Cc: dev, stable
Currently, only new value is printed during global
register change. Add original value to help debugging
facility.
Fixes: bc66b9717c50 ("net/i40e: add debug logs when writing global registers")
Cc: stable@dpdk.org
Signed-off-by: Beilei Xing <beilei.xing@intel.com>
---
drivers/net/i40e/i40e_ethdev.c | 42 +++++++++++++++++++++++++++++++++++-------
drivers/net/i40e/i40e_ethdev.h | 8 +++++---
2 files changed, 40 insertions(+), 10 deletions(-)
diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c
index 894505f..1dbd8f7 100644
--- a/drivers/net/i40e/i40e_ethdev.c
+++ b/drivers/net/i40e/i40e_ethdev.c
@@ -1156,6 +1156,30 @@ i40e_support_multi_driver(struct rte_eth_dev *dev)
}
static int
+i40e_aq_debug_write_global_register(struct i40e_hw *hw,
+ uint32_t reg_addr, uint64_t reg_val,
+ struct i40e_asq_cmd_details *cmd_details)
+{
+ uint64_t ori_reg_val;
+ int ret;
+
+ ret = i40e_aq_debug_read_register(hw, reg_addr, &ori_reg_val, NULL);
+ if (ret != I40E_SUCCESS) {
+ PMD_DRV_LOG(ERR,
+ "Fail to debug read from 0x%08x",
+ reg_addr);
+ return -EIO;
+ }
+
+ PMD_DRV_LOG(DEBUG,
+ "Global register [0x%08x] original: 0x%"PRIx64
+ ", after: 0x%"PRIx64,
+ reg_addr, ori_reg_val, reg_val);
+
+ return i40e_aq_debug_write_register(hw, reg_addr, reg_val, cmd_details);
+}
+
+static int
eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused)
{
struct rte_pci_device *pci_dev;
@@ -1262,7 +1286,8 @@ eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused)
/* initialise the L3_MAP register */
if (!pf->support_multi_driver) {
- ret = i40e_aq_debug_write_register(hw, I40E_GLQF_L3_MAP(40),
+ ret = i40e_aq_debug_write_global_register(hw,
+ I40E_GLQF_L3_MAP(40),
0x00000028, NULL);
if (ret)
PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d",
@@ -3459,7 +3484,8 @@ i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
return 0;
}
- ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
+ ret = i40e_aq_debug_write_global_register(hw,
+ I40E_GL_SWT_L2TAGCTRL(reg_id),
reg_w, NULL);
if (ret != I40E_SUCCESS) {
PMD_DRV_LOG(ERR,
@@ -3471,6 +3497,8 @@ i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
"Global register 0x%08x is changed with value 0x%08x",
I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
+ i40e_global_cfg_warning(I40E_WARNING_TPID);
+
return 0;
}
@@ -3520,7 +3548,6 @@ i40e_vlan_tpid_set(struct rte_eth_dev *dev,
/* If NVM API < 1.7, keep the register setting */
ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
tpid, qinq);
- i40e_global_cfg_warning(I40E_WARNING_TPID);
return ret;
}
@@ -8356,7 +8383,8 @@ i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
}
if (reg != val) {
- ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
+ ret = i40e_aq_debug_write_global_register(hw,
+ I40E_GL_PRS_FVBM(2),
reg, NULL);
if (ret != 0)
return ret;
@@ -9249,11 +9277,11 @@ i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
{
uint32_t reg = i40e_read_rx_ctl(hw, addr);
- PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
if (reg != val)
i40e_write_global_rx_ctl(hw, addr, val);
- PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
- (uint32_t)i40e_read_rx_ctl(hw, addr));
+ PMD_DRV_LOG(DEBUG,
+ "global register [0x%08x] original: 0x%08x, after: 0x%08x",
+ addr, reg, (uint32_t)i40e_read_rx_ctl(hw, addr));
}
static void
diff --git a/drivers/net/i40e/i40e_ethdev.h b/drivers/net/i40e/i40e_ethdev.h
index 4dd50eb..55c8875 100644
--- a/drivers/net/i40e/i40e_ethdev.h
+++ b/drivers/net/i40e/i40e_ethdev.h
@@ -86,11 +86,13 @@
#define I40E_WRITE_GLB_REG(hw, reg, value) \
do { \
+ uint32_t ori_val; \
+ ori_val = I40E_READ_REG((hw), (reg)); \
I40E_PCI_REG_WRITE(I40E_PCI_REG_ADDR((hw), \
(reg)), (value)); \
- PMD_DRV_LOG(DEBUG, "Global register 0x%08x is modified " \
- "with value 0x%08x", \
- (reg), (value)); \
+ PMD_DRV_LOG(DEBUG, "global register [0x%08x] " \
+ "original: 0x%08x, after: 0x%08x ", \
+ (reg), (ori_val), (value)); \
} while (0)
/* index flex payload per layer */
--
2.5.5
^ permalink raw reply [flat|nested] 4+ messages in thread
* [dpdk-dev] [PATCH v2] net/i40e: print original value for global register change
2018-05-11 17:35 [dpdk-dev] [PATCH] net/i40e: print original value for global register change Beilei Xing
@ 2018-05-11 18:17 ` Beilei Xing
2018-05-11 9:03 ` Zhang, Qi Z
0 siblings, 1 reply; 4+ messages in thread
From: Beilei Xing @ 2018-05-11 18:17 UTC (permalink / raw)
To: jingjing.wu, qi.z.zhang; +Cc: dev, stable
Currently, only new value is printed during global
register change. Add original value to help debugging
facility.
Fixes: bc66b9717c50 ("net/i40e: add debug logs when writing global registers")
Cc: stable@dpdk.org
Signed-off-by: Beilei Xing <beilei.xing@intel.com>
---
v2 changes:
- Add original value print in i40e_write_global_rx_ctl.
drivers/net/i40e/i40e_ethdev.c | 56 +++++++++++++++++++++++++++++++++---------
drivers/net/i40e/i40e_ethdev.h | 8 +++---
2 files changed, 49 insertions(+), 15 deletions(-)
diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c
index 894505f..80ebeaf 100644
--- a/drivers/net/i40e/i40e_ethdev.c
+++ b/drivers/net/i40e/i40e_ethdev.c
@@ -694,12 +694,16 @@ static struct rte_pci_driver rte_i40e_pmd = {
};
static inline void
-i40e_write_global_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
+i40e_write_global_rx_ctl(struct i40e_hw *hw, uint32_t reg_addr,
+ uint32_t reg_val)
{
+ uint32_t ori_reg_val;
+
+ ori_reg_val = i40e_read_rx_ctl(hw, reg_addr);
i40e_write_rx_ctl(hw, reg_addr, reg_val);
- PMD_DRV_LOG(DEBUG, "Global register 0x%08x is modified "
- "with value 0x%08x",
- reg_addr, reg_val);
+ PMD_DRV_LOG(DEBUG,
+ "Global register [0x%08x] original: 0x%08x, after: 0x%08x",
+ reg_addr, ori_reg_val, reg_val);
}
RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
@@ -1156,6 +1160,30 @@ i40e_support_multi_driver(struct rte_eth_dev *dev)
}
static int
+i40e_aq_debug_write_global_register(struct i40e_hw *hw,
+ uint32_t reg_addr, uint64_t reg_val,
+ struct i40e_asq_cmd_details *cmd_details)
+{
+ uint64_t ori_reg_val;
+ int ret;
+
+ ret = i40e_aq_debug_read_register(hw, reg_addr, &ori_reg_val, NULL);
+ if (ret != I40E_SUCCESS) {
+ PMD_DRV_LOG(ERR,
+ "Fail to debug read from 0x%08x",
+ reg_addr);
+ return -EIO;
+ }
+
+ PMD_DRV_LOG(DEBUG,
+ "Global register [0x%08x] original: 0x%"PRIx64
+ ", after: 0x%"PRIx64,
+ reg_addr, ori_reg_val, reg_val);
+
+ return i40e_aq_debug_write_register(hw, reg_addr, reg_val, cmd_details);
+}
+
+static int
eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused)
{
struct rte_pci_device *pci_dev;
@@ -1262,7 +1290,8 @@ eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused)
/* initialise the L3_MAP register */
if (!pf->support_multi_driver) {
- ret = i40e_aq_debug_write_register(hw, I40E_GLQF_L3_MAP(40),
+ ret = i40e_aq_debug_write_global_register(hw,
+ I40E_GLQF_L3_MAP(40),
0x00000028, NULL);
if (ret)
PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d",
@@ -3459,7 +3488,8 @@ i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
return 0;
}
- ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
+ ret = i40e_aq_debug_write_global_register(hw,
+ I40E_GL_SWT_L2TAGCTRL(reg_id),
reg_w, NULL);
if (ret != I40E_SUCCESS) {
PMD_DRV_LOG(ERR,
@@ -3471,6 +3501,8 @@ i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
"Global register 0x%08x is changed with value 0x%08x",
I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
+ i40e_global_cfg_warning(I40E_WARNING_TPID);
+
return 0;
}
@@ -3520,7 +3552,6 @@ i40e_vlan_tpid_set(struct rte_eth_dev *dev,
/* If NVM API < 1.7, keep the register setting */
ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
tpid, qinq);
- i40e_global_cfg_warning(I40E_WARNING_TPID);
return ret;
}
@@ -8356,7 +8387,8 @@ i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
}
if (reg != val) {
- ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
+ ret = i40e_aq_debug_write_global_register(hw,
+ I40E_GL_PRS_FVBM(2),
reg, NULL);
if (ret != 0)
return ret;
@@ -9249,11 +9281,11 @@ i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
{
uint32_t reg = i40e_read_rx_ctl(hw, addr);
- PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
if (reg != val)
- i40e_write_global_rx_ctl(hw, addr, val);
- PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
- (uint32_t)i40e_read_rx_ctl(hw, addr));
+ i40e_write_rx_ctl(hw, addr, val);
+ PMD_DRV_LOG(DEBUG,
+ "Global register [0x%08x] original: 0x%08x, after: 0x%08x",
+ addr, reg, (uint32_t)i40e_read_rx_ctl(hw, addr));
}
static void
diff --git a/drivers/net/i40e/i40e_ethdev.h b/drivers/net/i40e/i40e_ethdev.h
index 4dd50eb..55c8875 100644
--- a/drivers/net/i40e/i40e_ethdev.h
+++ b/drivers/net/i40e/i40e_ethdev.h
@@ -86,11 +86,13 @@
#define I40E_WRITE_GLB_REG(hw, reg, value) \
do { \
+ uint32_t ori_val; \
+ ori_val = I40E_READ_REG((hw), (reg)); \
I40E_PCI_REG_WRITE(I40E_PCI_REG_ADDR((hw), \
(reg)), (value)); \
- PMD_DRV_LOG(DEBUG, "Global register 0x%08x is modified " \
- "with value 0x%08x", \
- (reg), (value)); \
+ PMD_DRV_LOG(DEBUG, "global register [0x%08x] " \
+ "original: 0x%08x, after: 0x%08x ", \
+ (reg), (ori_val), (value)); \
} while (0)
/* index flex payload per layer */
--
2.5.5
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2018-05-11 12:06 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-05-11 17:35 [dpdk-dev] [PATCH] net/i40e: print original value for global register change Beilei Xing
2018-05-11 18:17 ` [dpdk-dev] [PATCH v2] " Beilei Xing
2018-05-11 9:03 ` Zhang, Qi Z
2018-05-11 12:06 ` Ferruh Yigit
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).