From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wi0-f178.google.com (mail-wi0-f178.google.com [209.85.212.178]) by dpdk.org (Postfix) with ESMTP id 9188B7F34 for ; Thu, 6 Nov 2014 14:48:11 +0100 (CET) Received: by mail-wi0-f178.google.com with SMTP id bs8so1559465wib.11 for ; Thu, 06 Nov 2014 05:57:39 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:organization :user-agent:in-reply-to:references:mime-version :content-transfer-encoding:content-type; bh=IP/49tovqqo51AfAIQv0WcgwIfHMvfGyL6tBf0R71Vo=; b=JAC77pDnMRzaMZ7CNZgAsdIOhsVwO19IoW8syFcrhiYm10zH+xa4WHk3MdBgZzA3oL y74S3fqIZVV+fpwShWlxsVD42JBiKifpRVGWbm/9k5MHIWCzPLTvicKe+ZB3gtI0w4Ym gSJVNtxAxjdcyZ3m6dB0KJIjLNLT9CENKeM8CP2Hx991PWFqTAIqLtq9dwhG8CABQq0i gw3tFUGFJOu6Ff4kZqm0d1rHvGZlunYYltVDdABGWXjuhTR+WZP5X7RyHHI33iI2mUmO O8vtvdI65/T9ag+pr/V4ru3eY/Fd6iZAOa2HTGq1mwHWGtGWFAamm7GV0TJa+lcI20eY IjSg== X-Gm-Message-State: ALoCoQnn3mY12+LnpdUruKgeccWt00H7Qep8wXtDlbrTq6E00oEeQqtcOaaVXDwsisRCPTAmsPET X-Received: by 10.180.212.42 with SMTP id nh10mr40645140wic.52.1415282259203; Thu, 06 Nov 2014 05:57:39 -0800 (PST) Received: from xps13.localnet (136-92-190-109.dsl.ovh.fr. [109.190.92.136]) by mx.google.com with ESMTPSA id q10sm7904309wjq.35.2014.11.06.05.57.37 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 06 Nov 2014 05:57:38 -0800 (PST) From: Thomas Monjalon To: Ouyang Changchun Date: Thu, 06 Nov 2014 14:57:19 +0100 Message-ID: <1527439.eYyC8gJdKq@xps13> Organization: 6WIND User-Agent: KMail/4.14.2 (Linux/3.17.2-1-ARCH; KDE/4.14.2; x86_64; ; ) In-Reply-To: <1414732757-7241-4-git-send-email-changchun.ouyang@intel.com> References: <1414381533-30370-1-git-send-email-changchun.ouyang@intel.com> <1414732757-7241-1-git-send-email-changchun.ouyang@intel.com> <1414732757-7241-4-git-send-email-changchun.ouyang@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Cc: dev@dpdk.org Subject: Re: [dpdk-dev] [PATCH v3 3/5] ixgbe: Config PFVML2FLT register X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 06 Nov 2014 13:48:11 -0000 Title would be more high level. Example: "ixgbe: configure Rx mode for VMDQ" 2014-10-31 13:19, Ouyang Changchun: > + for (i = 0; i < (int)num_pools; i++) { > + if (cfg->rx_mode & ETH_VMDQ_ACCEPT_UNTAG) > + vmolr |= IXGBE_VMOLR_AUPE; > + if (cfg->rx_mode & ETH_VMDQ_ACCEPT_HASH_MC) > + vmolr |= IXGBE_VMOLR_ROMPE; > + if (cfg->rx_mode & ETH_VMDQ_ACCEPT_HASH_UC) > + vmolr |= IXGBE_VMOLR_ROPE; > + if (cfg->rx_mode & ETH_VMDQ_ACCEPT_BROADCAST) > + vmolr |= IXGBE_VMOLR_BAM; > + if (cfg->rx_mode & ETH_VMDQ_ACCEPT_MULTICAST) > + vmolr |= IXGBE_VMOLR_MPE; > + > + IXGBE_WRITE_REG(hw, IXGBE_VMOLR(i), vmolr); > + } Please factorize code with ixgbe_set_pool_rx_mode() which is really similar. -- Thomas