[dpdk-dev] [PATCH v1 2/7] compress/octeontx: add device setup PMD ops

[Shally Verma <shally.verma@caviumnetworks.com>]

implement device configure and PMD ops.
setup stream resource memory pool
setup and enable hardware queue

Signed-off-by: Ashish Gupta <ashish.gupta@caviumnetworks.com>
Signed-off-by: Shally Verma <shally.verma@caviumnetworks.com>
Signed-off-by: Sunila Sahu <sunila.sahu@caviumnetworks.com>
---
 drivers/compress/octeontx/include/zip_regs.h | 721 +++++++++++++++++++++++++++
 drivers/compress/octeontx/zip_pmd.c          | 269 ++++++++++
 drivers/compress/octeontx/zipvf.c            |  81 +++
 drivers/compress/octeontx/zipvf.h            | 103 ++++
 4 files changed, 1174 insertions(+)

diff --git a/drivers/compress/octeontx/include/zip_regs.h b/drivers/compress/octeontx/include/zip_regs.h
new file mode 100644
index 000000000..1326dc030
--- /dev/null
+++ b/drivers/compress/octeontx/include/zip_regs.h
@@ -0,0 +1,721 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2017-2018 Cavium Networks
+ */
+
+#ifndef _RTE_OCTEONTX_ZIP_REGS_H_
+#define _RTE_OCTEONTX_ZIP_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stddef.h>
+#include <stdint.h>
+
+/**
+ * Enumeration zip_cc
+ *
+ * ZIP compression coding Enumeration
+ * Enumerates ZIP_INST_S[CC].
+ */
+enum {
+	ZIP_CC_DEFAULT = 0,
+	ZIP_CC_DYN_HUFF,
+	ZIP_CC_FIXED_HUFF,
+	ZIP_CC_LZS
+} zip_cc;
+
+/**
+ * Register (NCB) zip_vq#_ena
+ *
+ * ZIP VF Queue Enable Register
+ * If a queue is disabled, ZIP CTL stops fetching instructions from the queue.
+ */
+typedef union {
+	uint64_t u;
+	struct zip_vqx_ena_s {
+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */
+		uint64_t reserved_1_63         : 63;
+		uint64_t ena                   : 1;
+#else /* Word 0 - Little Endian */
+		uint64_t ena                   : 1;
+		uint64_t reserved_1_63         : 63;
+#endif /* Word 0 - End */
+	} s;
+	/* struct zip_vqx_ena_s cn; */
+} zip_vqx_ena_t;
+
+/**
+ * Register (NCB) zip_vq#_sbuf_addr
+ *
+ * ZIP VF Queue Starting Buffer Address Registers
+ * These registers set the buffer parameters for the instruction queues.
+ * When quiescent (i.e.
+ * outstanding doorbell count is 0), it is safe to rewrite this register
+ * to effectively reset the
+ * command buffer state machine.
+ * These registers must be programmed after software programs the
+ * corresponding ZIP_QUE()_SBUF_CTL.
+ */
+typedef union {
+	uint64_t u;
+	struct zip_vqx_sbuf_addr_s {
+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */
+		uint64_t reserved_49_63        : 15;
+		uint64_t ptr                   : 42;
+		uint64_t off                   : 7;
+#else /* Word 0 - Little Endian */
+		uint64_t off                   : 7;
+		uint64_t ptr                   : 42;
+		uint64_t reserved_49_63        : 15;
+#endif /* Word 0 - End */
+	} s;
+	/* struct zip_vqx_sbuf_addr_s cn; */
+} zip_vqx_sbuf_addr_t;
+
+/**
+ * Register (NCB) zip_que#_doorbell
+ *
+ * ZIP Queue Doorbell Registers
+ * Doorbells for the ZIP instruction queues.
+ */
+typedef union {
+	uint64_t u;
+	struct zip_quex_doorbell_s {
+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */
+		uint64_t reserved_20_63        : 44;
+		uint64_t dbell_cnt             : 20;
+#else /* Word 0 - Little Endian */
+		uint64_t dbell_cnt             : 20;
+		uint64_t reserved_20_63        : 44;
+#endif /* Word 0 - End */
+	} s;
+	/* struct zip_quex_doorbell_s cn; */
+} zip_quex_doorbell_t;
+
+/**
+ * Structure zip_nptr_s
+ *
+ * ZIP Instruction Next-Chunk-Buffer Pointer (NPTR) Structure
+ * This structure is used to chain all the ZIP instruction buffers
+ * together. ZIP instruction buffers are managed
+ * (allocated and released) by software.
+ */
+union zip_nptr_s {
+	uint64_t u;
+	struct zip_nptr_s_s {
+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */
+		uint64_t addr                  : 64;
+#else /* Word 0 - Little Endian */
+		uint64_t addr                  : 64;
+#endif /* Word 0 - End */
+	} s;
+	/* struct zip_nptr_s_s cn83xx; */
+};
+
+/**
+ * generic ptr address
+ */
+union zip_zptr_addr_s {
+	/** This field can be used to set/clear all bits, or do bitwise
+	 * operations over the entire structure.
+	 */
+	uint64_t u;
+	/** generic ptr address */
+	struct {
+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */
+		uint64_t addr : 64;
+#else /* Word 0 - Little Endian */
+		uint64_t addr : 64;
+#endif /* Word 0 - End */
+	} s;
+};
+
+/**
+ * generic ptr ctl
+ */
+union zip_zptr_ctl_s {
+	/** This field can be used to set/clear all bits, or do bitwise
+	 * operations over the entire structure.
+	 */
+	uint64_t u;
+	/** generic ptr ctl */
+	struct {
+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 1 - Big Endian */
+		uint64_t reserved_112_127      : 16;
+		uint64_t length                : 16;
+		uint64_t reserved_67_95        : 29;
+		uint64_t fw                    : 1;
+		uint64_t nc                    : 1;
+		uint64_t data_be               : 1;
+#else /* Word 1 - Little Endian */
+		uint64_t data_be               : 1;
+		uint64_t nc                    : 1;
+		uint64_t fw                    : 1;
+		uint64_t reserved_67_95        : 29;
+		uint64_t length                : 16;
+		uint64_t reserved_112_127      : 16;
+#endif /* Word 1 - End */
+	} s;
+
+};
+
+/**
+ * Structure zip_inst_s
+ *
+ * ZIP Instruction Structure
+ * Each ZIP instruction has 16 words (they are called IWORD0 to IWORD15
+ * within the structure).
+ */
+union zip_inst_s {
+	/** This field can be used to set/clear all bits, or do bitwise
+	 * operations over the entire structure.
+	 */
+	uint64_t u[16];
+	/** ZIP Instruction Structure */
+	struct zip_inst_s_s {
+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */
+		/** Done interrupt */
+		uint64_t doneint               : 1;
+		/** reserved */
+		uint64_t reserved_56_62        : 7;
+		/**  Total output length */
+		uint64_t totaloutputlength     : 24;
+		/** reserved */
+		uint64_t reserved_27_31        : 5;
+		/** EXNUM */
+		uint64_t exn                   : 3;
+		/**  HASH IV */
+		uint64_t iv                    : 1;
+		/** EXBITS */
+		uint64_t exbits                : 7;
+		/** Hash more-in-file */
+		uint64_t hmif                  : 1;
+		/** Hash Algorithm and enable */
+		uint64_t halg                  : 3;
+		/** Sync flush*/
+		uint64_t sf                    : 1;
+		/** Compression speed/storage */
+		uint64_t ss                    : 2;
+		/** Compression coding */
+		uint64_t cc                    : 2;
+		/** End of input data */
+		uint64_t ef                    : 1;
+		/** Beginning of file */
+		uint64_t bf                    : 1;
+		// uint64_t reserved_3_4          : 2;
+		/** Comp/decomp operation */
+		uint64_t op                    : 2;
+		/** Data sactter */
+		uint64_t ds                    : 1;
+		/** Data gather */
+		uint64_t dg                    : 1;
+		/** History gather */
+		uint64_t hg                    : 1;
+#else /* Word 0 - Little Endian */
+		uint64_t hg                    : 1;
+		uint64_t dg                    : 1;
+		uint64_t ds                    : 1;
+		//uint64_t reserved_3_4          : 2;
+		uint64_t op                    : 2;
+		uint64_t bf                    : 1;
+		uint64_t ef                    : 1;
+		uint64_t cc                    : 2;
+		uint64_t ss                    : 2;
+		uint64_t sf                    : 1;
+		uint64_t halg                  : 3;
+		uint64_t hmif                  : 1;
+		uint64_t exbits                : 7;
+		uint64_t iv                    : 1;
+		uint64_t exn                   : 3;
+		uint64_t reserved_27_31        : 5;
+		uint64_t totaloutputlength     : 24;
+		uint64_t reserved_56_62        : 7;
+		uint64_t doneint               : 1;
+
+#endif /* Word 0 - End */
+
+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 1 - Big Endian */
+		/** History length */
+		uint64_t historylength         : 16;
+		/** reserved */
+		uint64_t reserved_96_111       : 16;
+		/** adler/crc32 checksum*/
+		uint64_t adlercrc32            : 32;
+#else /* Word 1 - Little Endian */
+		uint64_t adlercrc32            : 32;
+		uint64_t reserved_96_111       : 16;
+		uint64_t historylength         : 16;
+#endif /* Word 1 - End */
+
+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 2 - Big Endian */
+		/** Decompression Context Pointer Address */
+		union zip_zptr_addr_s  ctx_ptr_addr;
+#else /* Word 2 - Little Endian */
+		union zip_zptr_addr_s  ctx_ptr_addr;
+#endif /* Word 2 - End */
+
+#if defined(__BIG_ENDIAN_BITFIELD)
+		/** Decompression Context Pointer Control */
+		union zip_zptr_ctl_s   ctx_ptr_ctl;
+#else /* Word 3 - Little Endian */
+		union zip_zptr_ctl_s   ctx_ptr_ctl;
+#endif /* Word 3 - End */
+
+#if defined(__BIG_ENDIAN_BITFIELD)
+		/** Decompression history pointer address */
+		union zip_zptr_addr_s  his_ptr_addr;
+#else /* Word 4 - Little Endian */
+		union zip_zptr_addr_s  his_ptr_addr;
+#endif /* Word 4 - End */
+
+#if defined(__BIG_ENDIAN_BITFIELD)
+		/** Decompression history pointer control */
+		union zip_zptr_ctl_s   his_ptr_ctl;
+#else /* Word 5 - Little Endian */
+		union zip_zptr_ctl_s   his_ptr_ctl;
+#endif /* Word 5 - End */
+
+#if defined(__BIG_ENDIAN_BITFIELD)
+		/** Input and compression history pointer address */
+		union zip_zptr_addr_s  inp_ptr_addr;
+#else /* Word 6 - Little Endian */
+		union zip_zptr_addr_s  inp_ptr_addr;
+#endif /* Word 6 - End */
+
+#if defined(__BIG_ENDIAN_BITFIELD)
+		/** Input and compression history pointer control */
+		union zip_zptr_ctl_s   inp_ptr_ctl;
+#else /* Word 7 - Little Endian */
+		union zip_zptr_ctl_s   inp_ptr_ctl;
+#endif /* Word 7 - End */
+
+#if defined(__BIG_ENDIAN_BITFIELD)
+		/** Output pointer address */
+		union zip_zptr_addr_s  out_ptr_addr;
+#else /* Word 8 - Little Endian */
+		union zip_zptr_addr_s  out_ptr_addr;
+#endif /* Word 8 - End */
+
+#if defined(__BIG_ENDIAN_BITFIELD)
+		/** Output pointer control */
+		union zip_zptr_ctl_s   out_ptr_ctl;
+#else /* Word 9 - Little Endian */
+		union zip_zptr_ctl_s   out_ptr_ctl;
+#endif /* Word 9 - End */
+
+#if defined(__BIG_ENDIAN_BITFIELD)
+		/** Result pointer address */
+		union zip_zptr_addr_s  res_ptr_addr;
+#else /* Word 10 - Little Endian */
+		union zip_zptr_addr_s  res_ptr_addr;
+#endif /* Word 10 - End */
+
+#if defined(__BIG_ENDIAN_BITFIELD)
+		/** Result pointer control */
+		union zip_zptr_ctl_s   res_ptr_ctl;
+#else /* Word 11 - Little Endian */
+		union zip_zptr_ctl_s   res_ptr_ctl;
+#endif /* Word 11 - End */
+
+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 12 - Big Endian */
+		/** reserved */
+		uint64_t reserved_812_831      : 20;
+		/** SSO guest group */
+		uint64_t ggrp                  : 10;
+		/** SSO tag type */
+		uint64_t tt                    : 2;
+		/** SSO tag */
+		uint64_t tag                   : 32;
+#else /* Word 12 - Little Endian */
+		uint64_t tag                   : 32;
+		uint64_t tt                    : 2;
+		uint64_t ggrp                  : 10;
+		uint64_t reserved_812_831      : 20;
+#endif /* Word 12 - End */
+
+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 13 - Big Endian */
+		/** Work queue entry pointer */
+		uint64_t wq_ptr                : 64;
+#else /* Word 13 - Little Endian */
+		uint64_t wq_ptr                : 64;
+#endif /* Word 13 - End */
+
+#if defined(__BIG_ENDIAN_BITFIELD)
+		/** reserved */
+		uint64_t reserved_896_959      : 64;
+#else /* Word 14 - Little Endian */
+		uint64_t reserved_896_959      : 64;
+#endif /* Word 14 - End */
+#if defined(__BIG_ENDIAN_BITFIELD)
+		/** Hash structure pointer */
+		uint64_t hash_ptr              : 64;
+#else /* Word 15 - Little Endian */
+		uint64_t hash_ptr              : 64;
+#endif /* Word 15 - End */
+	} /** ZIP 88xx Instruction Structure */zip88xx;
+
+	/** ZIP Instruction Structure */
+	struct zip_inst_s_cn83xx {
+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */
+		/** Done interrupt */
+		uint64_t doneint               : 1;
+		/** reserved */
+		uint64_t reserved_56_62        : 7;
+		/**  Total output length */
+		uint64_t totaloutputlength     : 24;
+		/** reserved */
+		uint64_t reserved_27_31        : 5;
+		/** EXNUM */
+		uint64_t exn                   : 3;
+		/**  HASH IV */
+		uint64_t iv                    : 1;
+		/** EXBITS */
+		uint64_t exbits                : 7;
+		/** Hash more-in-file */
+		uint64_t hmif                  : 1;
+		/** Hash Algorithm and enable */
+		uint64_t halg                  : 3;
+		/** Sync flush*/
+		uint64_t sf                    : 1;
+		/** Compression speed/storage */
+		uint64_t ss                    : 2;
+		/** Compression coding */
+		uint64_t cc                    : 2;
+		/** End of input data */
+		uint64_t ef                    : 1;
+		/** Beginning of file */
+		uint64_t bf                    : 1;
+		/** Comp/decomp operation */
+		uint64_t op                    : 2;
+		/** Data sactter */
+		uint64_t ds                    : 1;
+		/** Data gather */
+		uint64_t dg                    : 1;
+		/** History gather */
+		uint64_t hg                    : 1;
+#else /* Word 0 - Little Endian */
+		uint64_t hg                    : 1;
+		uint64_t dg                    : 1;
+		uint64_t ds                    : 1;
+		uint64_t op                    : 2;
+		uint64_t bf                    : 1;
+		uint64_t ef                    : 1;
+		uint64_t cc                    : 2;
+		uint64_t ss                    : 2;
+		uint64_t sf                    : 1;
+		uint64_t halg                  : 3;
+		uint64_t hmif                  : 1;
+		uint64_t exbits                : 7;
+		uint64_t iv                    : 1;
+		uint64_t exn                   : 3;
+		uint64_t reserved_27_31        : 5;
+		uint64_t totaloutputlength     : 24;
+		uint64_t reserved_56_62        : 7;
+		uint64_t doneint               : 1;
+#endif /* Word 0 - End */
+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 1 - Big Endian */
+		/** History length */
+		uint64_t historylength         : 16;
+		/** reserved */
+		uint64_t reserved_96_111       : 16;
+		/** adler/crc32 checksum*/
+		uint64_t adlercrc32            : 32;
+#else /* Word 1 - Little Endian */
+		uint64_t adlercrc32            : 32;
+		uint64_t reserved_96_111       : 16;
+		uint64_t historylength         : 16;
+#endif /* Word 1 - End */
+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 2 - Big Endian */
+		/** Decompression Context Pointer Address */
+		union zip_zptr_addr_s  ctx_ptr_addr;
+#else /* Word 2 - Little Endian */
+		union zip_zptr_addr_s  ctx_ptr_addr;
+#endif /* Word 2 - End */
+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 3 - Big Endian */
+		/** Decompression Context Pointer Control */
+		union zip_zptr_ctl_s   ctx_ptr_ctl;
+#else /* Word 3 - Little Endian */
+		union zip_zptr_ctl_s   ctx_ptr_ctl;
+#endif /* Word 3 - End */
+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 4 - Big Endian */
+		/** Decompression history pointer address */
+		union zip_zptr_addr_s  his_ptr_addr;
+#else /* Word 4 - Little Endian */
+		union zip_zptr_addr_s  his_ptr_addr;
+#endif /* Word 4 - End */
+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 5 - Big Endian */
+		/** Decompression history pointer control */
+		union zip_zptr_ctl_s   his_ptr_ctl;
+#else /* Word 5 - Little Endian */
+		union zip_zptr_ctl_s   his_ptr_ctl;
+#endif /* Word 5 - End */
+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 6 - Big Endian */
+		/** Input and compression history pointer address */
+		union zip_zptr_addr_s  inp_ptr_addr;
+#else /* Word 6 - Little Endian */
+		union zip_zptr_addr_s  inp_ptr_addr;
+#endif /* Word 6 - End */
+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 7 - Big Endian */
+		/** Input and compression history pointer control */
+		union zip_zptr_ctl_s   inp_ptr_ctl;
+#else /* Word 7 - Little Endian */
+		union zip_zptr_ctl_s   inp_ptr_ctl;
+#endif /* Word 7 - End */
+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 8 - Big Endian */
+		/** Output pointer address */
+		union zip_zptr_addr_s  out_ptr_addr;
+#else /* Word 8 - Little Endian */
+		union zip_zptr_addr_s  out_ptr_addr;
+#endif /* Word 8 - End */
+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 9 - Big Endian */
+		/** Output pointer control */
+		union zip_zptr_ctl_s   out_ptr_ctl;
+#else /* Word 9 - Little Endian */
+		union zip_zptr_ctl_s   out_ptr_ctl;
+#endif /* Word 9 - End */
+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 10 - Big Endian */
+		/** Result pointer address */
+		union zip_zptr_addr_s  res_ptr_addr;
+#else /* Word 10 - Little Endian */
+		union zip_zptr_addr_s  res_ptr_addr;
+#endif /* Word 10 - End */
+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 11 - Big Endian */
+		/** Result pointer control */
+		union zip_zptr_ctl_s   res_ptr_ctl;
+#else /* Word 11 - Little Endian */
+		union zip_zptr_ctl_s   res_ptr_ctl;
+#endif /* Word 11 - End */
+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 12 - Big Endian */
+		/** reserved */
+		uint64_t reserved_812_831      : 20;
+		/** SSO guest group */
+		uint64_t ggrp                  : 10;
+		/** SSO tag type */
+		uint64_t tt                    : 2;
+		/** SSO tag */
+		uint64_t tag                   : 32;
+#else /* Word 12 - Little Endian */
+		uint64_t tag                   : 32;
+		uint64_t tt                    : 2;
+		uint64_t ggrp                  : 10;
+		uint64_t reserved_812_831      : 20;
+#endif /* Word 12 - End */
+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 13 - Big Endian */
+		/** Work queue entry pointer */
+		uint64_t wq_ptr                : 64;
+#else /* Word 13 - Little Endian */
+		uint64_t wq_ptr                : 64;
+#endif /* Word 13 - End */
+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 14 - Big Endian */
+		/** reserved */
+		uint64_t reserved_896_959      : 64;
+#else /* Word 14 - Little Endian */
+		uint64_t reserved_896_959      : 64;
+#endif /* Word 14 - End */
+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 15 - Big Endian */
+		/** Hash structure pointer */
+		uint64_t hash_ptr              : 64;
+#else /* Word 15 - Little Endian */
+		uint64_t hash_ptr              : 64;
+#endif /* Word 15 - End */
+	} /** ZIP 83xx Instruction Structure */s;
+};
+
+/**
+ * Structure zip_zres_s
+ *
+ * ZIP Result Structure
+ * The ZIP coprocessor writes the result structure after it completes the
+ * invocation. The result structure is exactly 24 bytes, and each invocation
+ * of the ZIP coprocessor produces exactly one result structure.
+ */
+union zip_zres_s {
+	/** This field can be used to set/clear all bits, or do bitwise
+	 * operations over the entire structure.
+	 */
+	uint64_t u[8];
+	/** ZIP Result Structure */
+	struct zip_zres_s_s {
+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */
+		/** crc32 checksum of uncompressed stream */
+		uint64_t crc32                 : 32;
+		/** adler32 checksum of uncompressed stream*/
+		uint64_t adler32               : 32;
+#else /* Word 0 - Little Endian */
+		uint64_t adler32               : 32;
+		uint64_t crc32                 : 32;
+#endif /* Word 0 - End */
+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 1 - Big Endian */
+		/** Total numer of Bytes produced in output stream */
+		uint64_t totalbyteswritten     : 32;
+		/** Total number of bytes processed from the input stream */
+		uint64_t totalbytesread        : 32;
+#else /* Word 1 - Little Endian */
+		uint64_t totalbytesread        : 32;
+		uint64_t totalbyteswritten     : 32;
+#endif /* Word 1 - End */
+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 2 - Big Endian */
+		/** Total number of compressed input bits
+		 * consumed to decompress all blocks in the file
+		 */
+		uint64_t totalbitsprocessed    : 32;
+		/** Done interrupt*/
+		uint64_t doneint               : 1;
+		/** reserved */
+		uint64_t reserved_155_158      : 4;
+		/** EXNUM */
+		uint64_t exn                   : 3;
+		/** reserved */
+		uint64_t reserved_151          : 1;
+		/** EXBITS */
+		uint64_t exbits                : 7;
+		/** reserved */
+		uint64_t reserved_137_143      : 7;
+		/** End of file */
+		uint64_t ef                    : 1;
+		/** Completion/error code */
+		uint64_t compcode              : 8;
+#else /* Word 2 - Little Endian */
+		uint64_t compcode              : 8;
+		uint64_t ef                    : 1;
+		uint64_t reserved_137_143      : 7;
+		uint64_t exbits                : 7;
+		uint64_t reserved_151          : 1;
+		uint64_t exn                   : 3;
+		uint64_t reserved_155_158      : 4;
+		uint64_t doneint               : 1;
+		uint64_t totalbitsprocessed    : 32;
+#endif /* Word 2 - End */
+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 3 - Big Endian */
+		/** reserved */
+		uint64_t reserved_253_255      : 3;
+		/** Hash length in bytes */
+		uint64_t hshlen                : 61;
+#else /* Word 3 - Little Endian */
+		uint64_t hshlen                : 61;
+		uint64_t reserved_253_255      : 3;
+#endif /* Word 3 - End */
+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 4 - Big Endian */
+		/** Double-word 0 of computed hash */
+		uint64_t hash0                 : 64;
+#else /* Word 4 - Little Endian */
+		uint64_t hash0                 : 64;
+#endif /* Word 4 - End */
+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 5 - Big Endian */
+		/** Double-word 1 of computed hash */
+		uint64_t hash1                 : 64;
+#else /* Word 5 - Little Endian */
+		uint64_t hash1                 : 64;
+#endif /* Word 5 - End */
+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 6 - Big Endian */
+		/** Double-word 2 of computed hash */
+		uint64_t hash2                 : 64;
+#else /* Word 6 - Little Endian */
+		uint64_t hash2                 : 64;
+#endif /* Word 6 - End */
+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 7 - Big Endian */
+		/** Double-word 3 of computed hash */
+		uint64_t hash3                 : 64;
+#else /* Word 7 - Little Endian */
+		uint64_t hash3                 : 64;
+#endif /* Word 7 - End */
+	} /** ZIP Result Structure */s;
+
+	/* struct zip_zres_s_s cn83xx; */
+};
+
+/**
+ * Structure zip_zptr_s
+ *
+ * ZIP Generic Pointer Structure
+ * This structure is the generic format of pointers in ZIP_INST_S.
+ */
+union zip_zptr_s {
+	/** This field can be used to set/clear all bits, or do bitwise
+	 * operations over the entire structure.
+	 */
+	uint64_t u[2];
+	/** ZIP Generic Pointer Structure */
+	struct zip_zptr_s_s {
+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */
+		/** Pointer to Data or scatter-gather list */
+		uint64_t addr                  : 64;
+#else /* Word 0 - Little Endian */
+		uint64_t addr                  : 64;
+#endif /* Word 0 - End */
+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 1 - Big Endian */
+		/** reserved */
+		uint64_t reserved_112_127      : 16;
+		/** Length of Data or scatter-gather list*/
+		uint64_t length                : 16;
+		/** reserved */
+		uint64_t reserved_67_95        : 29;
+		/** Full-block write */
+		uint64_t fw                    : 1;
+		/** No cache allocation */
+		uint64_t nc                    : 1;
+		/** reserved */
+		uint64_t data_be               : 1;
+#else /* Word 1 - Little Endian */
+		uint64_t data_be               : 1;
+		uint64_t nc                    : 1;
+		uint64_t fw                    : 1;
+		uint64_t reserved_67_95        : 29;
+		uint64_t length                : 16;
+		uint64_t reserved_112_127      : 16;
+#endif /* Word 1 - End */
+	} /** ZIP Generic Pointer Structure */s;
+};
+
+/**
+ * Enumeration zip_comp_e
+ *
+ * ZIP Completion Enumeration
+ * Enumerates the values of ZIP_ZRES_S[COMPCODE].
+ */
+#define ZIP_COMP_E_NOTDONE       (0)
+#define ZIP_COMP_E_SUCCESS       (1)
+#define ZIP_COMP_E_DTRUNC        (2)
+#define ZIP_COMP_E_DSTOP         (3)
+#define ZIP_COMP_E_ITRUNC        (4)
+#define ZIP_COMP_E_RBLOCK        (5)
+#define ZIP_COMP_E_NLEN          (6)
+#define ZIP_COMP_E_BADCODE       (7)
+#define ZIP_COMP_E_BADCODE2      (8)
+#define ZIP_COMP_E_ZERO_LEN      (9)
+#define ZIP_COMP_E_PARITY        (0xa)
+#define ZIP_COMP_E_FATAL         (0xb)
+#define ZIP_COMP_E_TIMEOUT       (0xc)
+#define ZIP_COMP_E_INSTR_ERR     (0xd)
+#define ZIP_COMP_E_HCTX_ERR      (0xe)
+#define ZIP_COMP_E_STOP          (3)
+
+/**
+ * Enumeration zip_op_e
+ *
+ * ZIP Operation Enumeration
+ * Enumerates ZIP_INST_S[OP].
+ * Internal:
+ */
+#define ZIP_OP_E_DECOMP   (0)
+#define ZIP_OP_E_NOCOMP   (1)
+#define ZIP_OP_E_COMP     (2)
+
+/**
+ * Enumeration zip compression levels
+ *
+ * ZIP Compression Level Enumeration
+ * Enumerates ZIP_INST_S[SS].
+ * Internal:
+ */
+#define ZIP_COMP_E_LEVEL_MAX  (0)
+#define ZIP_COMP_E_LEVEL_MED  (1)
+#define ZIP_COMP_E_LEVEL_LOW  (2)
+#define ZIP_COMP_E_LEVEL_MIN  (3)
+
+#ifdef __cplusplus
+}
+#endif
+#endif	/* _RTE_ZIP_REGS_H_ */
+
diff --git a/drivers/compress/octeontx/zip_pmd.c b/drivers/compress/octeontx/zip_pmd.c
index 1181bed19..3bb7f6896 100644
--- a/drivers/compress/octeontx/zip_pmd.c
+++ b/drivers/compress/octeontx/zip_pmd.c
@@ -12,6 +12,275 @@
 /* global structure to keep driver info */
 struct zip_pmd_private zip_pmd_priv;
 
+static const struct rte_compressdev_capabilities
+				octtx_zip_pmd_capabilities[] = {
+	{       /* Deflate */
+		.algo = RTE_COMP_ALGO_DEFLATE,
+		/* Non sharable Priv XFORM and Stateless */
+		.comp_feature_flags = (RTE_COMP_FF_MBUF_SCATTER_GATHER |
+				      RTE_COMP_FF_ADLER32_CHECKSUM |
+				      RTE_COMP_FF_CRC32_CHECKSUM),
+		.window_size = {
+				/* size supported 2^1 to 2^14 */
+				.min = 1,
+				.max = 14,
+				.increment = 1
+		},
+	},
+	RTE_COMP_END_OF_CAPABILITIES_LIST()
+};
+
+/** Configure device */
+static int
+zip_pmd_config(struct rte_compressdev *dev,
+		struct rte_compressdev_config *config)
+{
+	int nb_streams;
+	char res_pool[RTE_MEMZONE_NAMESIZE];
+	struct zip_vf *vf;
+	struct rte_mempool *zip_buf_mp;
+
+	if (!config || !dev)
+		return -EIO;
+
+	vf = (struct zip_vf *)(dev->data->dev_private);
+
+	/* create pool with maximum numbers of resources
+	 * required by streams
+	 */
+
+	/* use common pool for non-shareable priv_xform and stream */
+	nb_streams = config->max_nb_priv_xforms + config->max_nb_streams;
+
+	snprintf(res_pool, RTE_MEMZONE_NAMESIZE, "octtx_zip_res_pool%u",
+		 dev->data->dev_id);
+
+	/** TBD Should we use the per core object cache for stream resources */
+	zip_buf_mp = rte_mempool_create(
+			res_pool,
+			nb_streams * MAX_BUFS_PER_STREAM,
+			ZIP_BUF_SIZE,
+			0,
+			0,
+			NULL,
+			NULL,
+			NULL,
+			NULL,
+			SOCKET_ID_ANY,
+			0);
+
+	if (zip_buf_mp == NULL) {
+		ZIP_PMD_ERR(
+			"Failed to create buf mempool octtx_zip_res_pool%u",
+			dev->data->dev_id);
+		return -1;
+	}
+
+	vf->zip_mp = zip_buf_mp;
+
+	return 0;
+}
+
+/** Start device */
+static int
+zip_pmd_start(struct rte_compressdev *dev)
+{
+	if (dev == NULL)
+		return -1;
+	return 0;
+}
+
+/** Stop device */
+static void
+zip_pmd_stop(__rte_unused struct rte_compressdev *dev)
+{
+
+}
+
+/** Close device */
+static int
+zip_pmd_close(struct rte_compressdev *dev)
+{
+	if (dev == NULL)
+		return -1;
+
+	struct zip_vf *vf = (struct zip_vf *)dev->data->dev_private;
+
+	for (int i = 0; dev->data->nb_queue_pairs; i++) {
+		if (dev->data->queue_pairs[i] != NULL)
+		/* qp not released, return error */
+		return -1;
+	}
+
+	rte_mempool_free(vf->zip_mp);
+	return 0;
+}
+
+/** Get device statistics */
+static void
+zip_pmd_stats_get(struct rte_compressdev *dev,
+		struct rte_compressdev_stats *stats)
+{
+	int qp_id;
+
+	for (qp_id = 0; qp_id < dev->data->nb_queue_pairs; qp_id++) {
+		struct zipvf_qp *qp = dev->data->queue_pairs[qp_id];
+
+		stats->enqueued_count += qp->qp_stats.enqueued_count;
+		stats->dequeued_count += qp->qp_stats.dequeued_count;
+
+		stats->enqueue_err_count += qp->qp_stats.enqueue_err_count;
+		stats->dequeue_err_count += qp->qp_stats.dequeue_err_count;
+	}
+}
+
+/** Reset device statistics */
+static void
+zip_pmd_stats_reset(struct rte_compressdev *dev)
+{
+	int qp_id;
+
+	for (qp_id = 0; qp_id < dev->data->nb_queue_pairs; qp_id++) {
+		struct zipvf_qp *qp = dev->data->queue_pairs[qp_id];
+		memset(&qp->qp_stats, 0, sizeof(qp->qp_stats));
+	}
+}
+
+/** Get device info */
+static void
+zip_pmd_info_get(struct rte_compressdev *dev,
+		struct rte_compressdev_info *dev_info)
+{
+	struct zip_vf *vf = (struct zip_vf *)dev->data->dev_private;
+
+	if (dev_info != NULL) {
+		dev_info->driver_name = dev->device->driver->name;
+		dev_info->feature_flags = dev->feature_flags;
+		dev_info->capabilities = octtx_zip_pmd_capabilities;
+		dev_info->max_nb_queue_pairs = vf->max_nb_queue_pairs;
+	}
+}
+
+/** Release queue pair */
+static int
+zip_pmd_qp_release(struct rte_compressdev *dev, uint16_t qp_id)
+{
+	struct zipvf_qp *qp = dev->data->queue_pairs[qp_id];
+	struct rte_ring *r = NULL;
+
+	if (qp != NULL) {
+		zipvf_q_term(qp);
+		r = rte_ring_lookup(qp->name);
+		if (r)
+			rte_ring_free(r);
+		rte_free(qp);
+		dev->data->queue_pairs[qp_id] = NULL;
+	}
+	return 0;
+}
+
+/** Create a ring to place process packets on */
+static struct rte_ring *
+zip_pmd_qp_create_processed_pkts_ring(struct zipvf_qp *qp,
+		unsigned int ring_size, int socket_id)
+{
+	struct rte_ring *r;
+
+	r = rte_ring_lookup(qp->name);
+	if (r) {
+		if (rte_ring_get_size(r) >= ring_size) {
+			ZIP_PMD_INFO("Reusing existing ring %s for processed"
+					" packets", qp->name);
+			return r;
+		}
+
+		ZIP_PMD_ERR("Unable to reuse existing ring %s for processed"
+				" packets", qp->name);
+		return NULL;
+	}
+
+	return rte_ring_create(qp->name, ring_size, socket_id,
+						RING_F_EXACT_SZ);
+}
+
+/** Setup a queue pair */
+static int
+zip_pmd_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,
+		uint32_t max_inflight_ops, int socket_id)
+{
+	struct zipvf_qp *qp = NULL;
+	struct zip_vf *vf = (struct zip_vf *) (dev->data->dev_private);
+	int ret;
+
+	if (!dev)
+		return -1;
+
+	/* Free memory prior to re-allocation if needed. */
+	if (dev->data->queue_pairs[qp_id] != NULL) {
+		ZIP_PMD_INFO("Using existing queue pair %d ", qp_id);
+		return 0;
+	}
+
+	/* Allocate the queue pair data structure. */
+	qp = rte_zmalloc_socket("ZIP PMD Queue Pair", sizeof(*qp),
+				RTE_CACHE_LINE_SIZE, socket_id);
+	if (qp == NULL)
+		return (-ENOMEM);
+
+	snprintf(qp->name, sizeof(qp->name),
+		 "zip_pmd_%u_qp_%u",
+		 dev->data->dev_id, qp_id);
+
+	/* Create completion queue upto max_inflight_ops */
+	qp->processed_pkts = zip_pmd_qp_create_processed_pkts_ring(qp,
+						max_inflight_ops, socket_id);
+	if (qp->processed_pkts == NULL)
+		goto qp_setup_cleanup;
+
+	qp->id = qp_id;
+	qp->vf = vf;
+
+	ret = zipvf_q_init(qp);
+	if (ret < 0)
+		goto qp_setup_cleanup;
+
+	dev->data->queue_pairs[qp_id] = qp;
+
+	memset(&qp->qp_stats, 0, sizeof(qp->qp_stats));
+	return 0;
+
+qp_setup_cleanup:
+	if (qp->processed_pkts) {
+		rte_ring_free(qp->processed_pkts);
+		qp->processed_pkts = NULL;
+	}
+	if (qp) {
+		rte_free(qp);
+		qp = NULL;
+	}
+	return -1;
+}
+
+struct rte_compressdev_ops octtx_zip_pmd_ops = {
+		.dev_configure		= zip_pmd_config,
+		.dev_start		= zip_pmd_start,
+		.dev_stop		= zip_pmd_stop,
+		.dev_close		= zip_pmd_close,
+
+		.stats_get		= zip_pmd_stats_get,
+		.stats_reset		= zip_pmd_stats_reset,
+
+		.dev_infos_get		= zip_pmd_info_get,
+
+		.queue_pair_setup	= zip_pmd_qp_setup,
+		.queue_pair_release	= zip_pmd_qp_release,
+
+		.private_xform_create	= zip_pmd_stream_create,
+		.private_xform_free	= zip_pmd_stream_free,
+		.stream_create		= zip_pmd_stream_create,
+		.stream_free		= zip_pmd_stream_free
+};
+
 static int
 zip_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 	struct rte_pci_device *pci_dev)
diff --git a/drivers/compress/octeontx/zipvf.c b/drivers/compress/octeontx/zipvf.c
index e082c2849..436e80b78 100644
--- a/drivers/compress/octeontx/zipvf.c
+++ b/drivers/compress/octeontx/zipvf.c
@@ -4,6 +4,87 @@
 
 #include "zipvf.h"
 
+uint64_t zip_reg_read64(uint8_t *hw_addr, uint64_t offset)
+{
+	uint8_t *base = hw_addr;
+	return *(volatile uint64_t *)(base + offset);
+}
+
+void zip_reg_write64(uint8_t *hw_addr, uint64_t offset, uint64_t val)
+{
+	uint8_t *base = hw_addr;
+	*(uint64_t *)(base + offset) = val;
+}
+
+static void zip_q_enable(struct zipvf_qp *qp)
+{
+	zip_vqx_ena_t que_ena;
+
+	/*ZIP VFx command queue init*/
+	que_ena.u = 0ull;
+	que_ena.s.ena = 1;
+
+	zip_reg_write64(qp->vf->vbar0, ZIP_VQ_ENA, que_ena.u);
+	rte_wmb();
+}
+
+/* initialize given qp on zip device */
+int zipvf_q_init(struct zipvf_qp *qp)
+{
+	zip_vqx_sbuf_addr_t que_sbuf_addr;
+
+	uint64_t size;
+	void *cmdq_addr;
+	uint64_t iova;
+	struct zipvf_cmdq *cmdq = &qp->cmdq;
+	struct zip_vf *vf = qp->vf;
+
+	/* allocate and setup instruction queue */
+	size = ZIP_MAX_CMDQ_SIZE;
+	size = ZIP_ALIGN_ROUNDUP(size, ZIP_CMDQ_ALIGN);
+
+	cmdq_addr = rte_zmalloc(qp->name, size, ZIP_CMDQ_ALIGN);
+	if (cmdq_addr == NULL)
+		return -1;
+
+	cmdq->sw_head = (uint64_t *)cmdq_addr;
+	cmdq->va = (uint8_t *)cmdq_addr;
+	iova = rte_mem_virt2iova(cmdq_addr);
+
+	/* Check for 128 byte alignment, if not align it*/
+	iova = (uint64_t)ZIP_ALIGN_ROUNDUP(iova, 128);
+	cmdq->iova = iova;
+
+	que_sbuf_addr.u = 0ull;
+	que_sbuf_addr.s.ptr = (cmdq->iova >> 7);
+	zip_reg_write64(vf->vbar0, ZIP_VQ_SBUF_ADDR, que_sbuf_addr.u);
+
+	zip_q_enable(qp);
+
+	memset(cmdq->va, 0, ZIP_MAX_CMDQ_SIZE);
+	rte_spinlock_init(&cmdq->qlock);
+
+	return 0;
+}
+
+int zipvf_q_term(struct zipvf_qp *qp)
+{
+	struct zipvf_cmdq *cmdq = &qp->cmdq;
+	zip_vqx_ena_t que_ena;
+	struct zip_vf *vf = qp->vf;
+
+	if (cmdq->va != NULL) {
+		memset(cmdq->va, 0, ZIP_MAX_CMDQ_SIZE);
+		rte_free(cmdq->va);
+	}
+
+	/*Disabling the ZIP queue*/
+	que_ena.u = 0ull;
+	zip_reg_write64(vf->vbar0, ZIP_VQ_ENA, que_ena.u);
+
+	return 0;
+}
+
 int zipvf_create(struct rte_compressdev *compressdev, int vfid)
 {
 	struct   rte_pci_device *pdev = RTE_DEV_TO_PCI(compressdev->device);
diff --git a/drivers/compress/octeontx/zipvf.h b/drivers/compress/octeontx/zipvf.h
index dcaaf4e46..9582d6119 100644
--- a/drivers/compress/octeontx/zipvf.h
+++ b/drivers/compress/octeontx/zipvf.h
@@ -4,13 +4,66 @@
 #ifndef _RTE_OCTEONTX_ZIP_VF_H_
 #define _RTE_OCTEONTX_ZIP_VF_H_
 
+#include <rte_bus_pci.h>
+#include <rte_spinlock.h>
+#include <rte_memory.h>
+#include <rte_malloc.h>
 #include <rte_comp.h>
 #include <rte_compressdev.h>
 #include <rte_compressdev_pmd.h>
+#include <zip_regs.h>
 #include <unistd.h>
 
 int octtx_zip_logtype_driver;
 
+/* ZIP VF Control/Status registers (CSRs): */
+/* VF_BAR0: */
+#define ZIP_VQ_ENA              (0x10)
+#define ZIP_VQ_SBUF_ADDR        (0x20)
+#define ZIP_VF_PF_MBOXX(x)      (0x400 | (x)<<3)
+#define ZIP_VQ_DOORBELL         (0x1000)
+
+/**< Vendor ID */
+#define PCI_VENDOR_ID_CAVIUM	0x177D
+/**< PCI device id of ZIP VF */
+#define PCI_DEVICE_ID_OCTEONTX_ZIPVF	0xA037
+
+/* maxmum number of zip vf devices */
+#define ZIP_MAX_VFS 8
+
+/* max size of one chunk */
+#define ZIP_MAX_CHUNK_SIZE	8192
+
+/* each instruction is fixed 128 bytes */
+#define ZIP_CMD_SIZE		128
+
+#define ZIP_CMD_SIZE_WORDS	(ZIP_CMD_SIZE >> 3) /* 16 64_bit words */
+
+/* size of next chunk buffer pointer */
+#define ZIP_MAX_NCBP_SIZE	8
+
+/* size of instruction queue in units of instruction size */
+#define ZIP_MAX_NUM_CMDS	((ZIP_MAX_CHUNK_SIZE - ZIP_MAX_NCBP_SIZE) / \
+				ZIP_CMD_SIZE) /* 63 */
+
+/* size of instruct queue in bytes */
+#define ZIP_MAX_CMDQ_SIZE	((ZIP_MAX_NUM_CMDS * ZIP_CMD_SIZE) + \
+				ZIP_MAX_NCBP_SIZE)/* ~8072ull */
+
+#define ZIP_BUF_SIZE	256
+
+#define ZIP_SGPTR_ALIGN	16
+#define ZIP_CMDQ_ALIGN	128
+#define MAX_SG_LEN	((ZIP_BUF_SIZE - ZIP_SGPTR_ALIGN) / sizeof(void *))
+
+/**< ZIP PMD specified queue pairs */
+#define ZIP_MAX_VF_QUEUE	1
+
+#define ZIP_ALIGN_ROUNDUP(x, _align) \
+	((_align) * (((x) + (_align) - 1) / (_align)))
+
+/**< ZIP PMD device name */
+#define COMPRESSDEV_NAME_ZIP_PMD	compress_octtx_zipvf
 
 #define ZIP_PMD_LOG(level, fmt, args...) \
 	rte_log(RTE_LOG_ ## level, \
@@ -24,6 +77,44 @@ int octtx_zip_logtype_driver;
 #define ZIP_PMD_WARN(fmt, args...) \
 	ZIP_PMD_LOG(WARNING, fmt, ## args)
 
+struct zip_pmd_private {
+	struct zip_vf *zipvf_table[ZIP_MAX_VFS];
+	/**< ZIP Devices List */
+	uint8_t num_zipvfs;
+	/**< Number of ZIP VFs attached to a Guest */
+};
+
+/**
+ * ZIP instruction Queue
+ */
+struct zipvf_cmdq {
+	rte_spinlock_t qlock;
+	/* queue lock */
+	uint64_t *sw_head;
+	/* 64-bit word pointer to queue head */
+	uint8_t *va;
+	/* pointer to iq virual address */
+	rte_iova_t iova;
+	/* iova addr of cmdq head*/
+};
+
+/**
+ * ZIP device queue structure
+ */
+struct zipvf_qp {
+	struct zipvf_cmdq cmdq;
+	/** Hardware queue handle */
+	struct rte_ring *processed_pkts;
+	/**< Ring for placing process packets */
+	struct rte_compressdev_stats qp_stats;
+	/**< Queue pair statistics */
+	uint16_t id;
+	/**< Queue Pair Identifier */
+	char name[RTE_COMPRESSDEV_NAME_MAX_LEN];
+	/**< Unique Queue Pair Name */
+	struct zip_vf *vf;
+} __rte_cache_aligned;
+
 /**
  * ZIP VF device structure.
  */
@@ -43,5 +134,17 @@ struct zip_vf {
 } __rte_cache_aligned;
 
 int zipvf_create(struct rte_compressdev *compressdev, int vfid);
+int zipvf_destroy(struct rte_compressdev *compressdev);
+int zipvf_q_init(struct zipvf_qp *qp);
+int zipvf_q_term(struct zipvf_qp *qp);
+int zip_set_stream_parameters(struct rte_compressdev *dev,
+				const struct rte_comp_xform *xform,
+				struct zip_stream *z_stream);
+int zip_process_op(struct rte_comp_op *op,
+				struct zipvf_qp *qp,
+				struct zip_stream *zstrm);
+
+uint64_t zip_reg_read64(uint8_t *hw_addr, uint64_t offset);
+void zip_reg_write64(uint8_t *hw_addr, uint64_t offset, uint64_t val);
 
 #endif /* _RTE_ZIP_VF_H_ */
-- 
2.14.3