[dpdk-dev] [PATCH 15/16] doc: add Cavium's CPT guide

[Anoob Joseph <anoob.joseph@caviumnetworks.com>]

From: Ragothaman Jayaraman <Ragothaman.Jayaraman@cavium.com>

The guide contains information about packages needed to compile
the CPT PMD. It also contains the compilation steps and how to
execute an examples application.

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@cavium.com>
Signed-off-by: Murthy NSSR <Nidadavolu.Murthy@cavium.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@cavium.com>
Signed-off-by: Ragothaman Jayaraman <Ragothaman.Jayaraman@cavium.com>
Signed-off-by: Srisivasubramanian Srinivasan <Srisivasubramanian.Srinivasan@cavium.com>
---
 doc/guides/cryptodevs/cpt.rst | 112 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 112 insertions(+)
 create mode 100644 doc/guides/cryptodevs/cpt.rst

diff --git a/doc/guides/cryptodevs/cpt.rst b/doc/guides/cryptodevs/cpt.rst
new file mode 100644
index 0000000..262ce9e
--- /dev/null
+++ b/doc/guides/cryptodevs/cpt.rst
@@ -0,0 +1,112 @@
+.. SPDX-License-Identifier: BSD-3-Clause
+   Copyright(c) 2017 Cavium, Inc
+
+*****************************
+Cavium's CPT Poll Mode Driver
+******************************
+
+The CPT poll mode driver provides support for offloading cryptographic
+operations on the Cavium's cryptographic accelerator unit(CPT) coprocessor
+hardware. This coprocessor is present on the Cavium's thunder boards(CN8xxx).
+The CPT poll mode driver enqueues the crypto request to this coprocessor and
+dequeues the response once the operation is completed.
+
+Supported Algorithms
+#####################
+
+Cipher Algorithms
+******************
+
+* ``RTE_CRYPTO_CIPHER_AES_CBC``
+* ``RTE_CRYPTO_CIPHER_AES_CTR``
+* ``RTE_CRYPTO_CIPHER_SNOW3G_UEA2``
+* ``RTE_CRYPTO_CIPHER_KASUMI_F8``
+* ``RTE_CRYPTO_CIPHER_ZUC_EEA3``
+* ``RTE_CRYPTO_CIPHER_3DES_CBC``
+* ``RTE_CRYPTO_CIPHER_NULL``
+
+Hash Algorithms
+****************
+
+* ``RTE_CRYPTO_AUTH_SHA1_HMAC``
+* ``RTE_CRYPTO_AUTH_SHA224_HMAC``
+* ``RTE_CRYPTO_AUTH_SHA256_HMAC``
+* ``RTE_CRYPTO_AUTH_SHA384_HMAC``
+* ``RTE_CRYPTO_AUTH_SHA512_HMAC``
+* ``RTE_CRYPTO_AUTH_MD5_HMAC``
+* ``RTE_CRYPTO_AUTH_AES_GMAC``
+* ``RTE_CRYPTO_AUTH_SNOW3G_UIA2``
+* ``RTE_CRYPTO_AUTH_NULL``
+* ``RTE_CRYPTO_AUTH_ZUC_EIA3``
+* ``RTE_CRYPTO_AUTH_KASUMI_F9``
+
+AEAD Algorithms
+****************
+
+* ``RTE_CRYPTO_AEAD_AES_GCM``
+
+Compilation
+############
+
+The thunder board must be running the linux kernel based on sdk-6.2.0 patch 2.
+In this the cpt pf driver is already built in. Also install the openssl package,
+because the cpt driver depends on the crypto library.
+
+For compiling the cpt poll mode driver, the CONFIG_RTE_LIBRTE_PMD_CPT setting
+should be made as `y` in config/common_base file. By default it is set to `n`.
+
+* ``CONFIG_RTE_LIBRTE_PMD_CPT=y``
+
+The following are the steps to compile the cpt poll mode driver:
+
+.. code-block:: console
+
+        cd <dpdk directory>
+        make config T=arm64-thunderx-linuxapp-gcc
+        make
+
+The example applications can be compiled using the following:
+
+.. code-block:: console
+
+        cd <dpdk directory>
+        export RTE_SDK=$PWD
+        export RTE_TARGET=build
+        cd examples/<application>
+        make
+
+Execution
+##########
+
+The sriov_numvfs should be assigned for the cpt pf driver using the following:
+
+.. code-block:: console
+
+        echo <num vfs> > /sys/bus/pci/devices/<device no>/sriov_numvfs
+
+The device number can be ascertained by running the dpdk-devbind.py scripts in
+the dpdk sources.
+
+Then the corresponding vf should be binded to the vfio-pci driver using the
+following:
+
+.. code-block:: console
+
+        cd <dpdk directory>
+        ./usertools/dpdk-devbind.py -u <vf device no>
+        ./usertools/dpdk-devbind.py -bvfio-pci <vf device no>
+
+Appropriate huge page need to be setup in order to run the examples dpdk
+application.
+
+.. code-block:: console
+
+        echo 8 > /sys/kernel/mm/hugepages/hugepages-524288kB/nr_hugepages
+        mkdir /mnt/huge
+        mount -t hugetlbfs nodev /mnt/huge
+
+After that the example dpdk application can be executed on the hardware.
+
+.. code-block:: console
+        ./build/ipsec-secgw --log-level=8 -c 0xff -- -P -p 0x3 -u 0x2 --config
+        "(0,0,0),(1,0,0)" -f ep0.cfg
-- 
1.9.3