From: Anoob Joseph <anoob.joseph@caviumnetworks.com>
To: Akhil Goyal <akhil.goyal@nxp.com>,
Pablo de Lara <pablo.de.lara.guarch@intel.com>,
Thomas Monjalon <thomas@monjalon.net>
Cc: Ankur Dwivedi <ankur.dwivedi@cavium.com>,
Jerin Jacob <jerin.jacob@caviumnetworks.com>,
Murthy NSSR <Nidadavolu.Murthy@cavium.com>,
Narayana Prasad <narayanaprasad.athreya@caviumnetworks.com>,
Nithin Dabilpuram <nithin.dabilpuram@cavium.com>,
Ragothaman Jayaraman <Ragothaman.Jayaraman@cavium.com>,
Srisivasubramanian Srinivasan
<Srisivasubramanian.Srinivasan@cavium.com>,
dev@dpdk.org
Subject: [dpdk-dev] [PATCH 06/16] crypto/cpt/base: add sym crypto request prepare for CPT
Date: Fri, 8 Jun 2018 22:15:15 +0530 [thread overview]
Message-ID: <1528476325-15585-7-git-send-email-anoob.joseph@caviumnetworks.com> (raw)
In-Reply-To: <1528476325-15585-1-git-send-email-anoob.joseph@caviumnetworks.com>
From: Ankur Dwivedi <ankur.dwivedi@cavium.com>
These functions help in preparing symmetric crypto requests
for the supported cipher/auth/aead. This includes all supported
algos except Kasumi, Snow3G, Zuc, HMAC_ONLY and HASH_ONLY cases.
Signed-off-by: Ankur Dwivedi <ankur.dwivedi@cavium.com>
Signed-off-by: Murthy NSSR <Nidadavolu.Murthy@cavium.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@cavium.com>
Signed-off-by: Ragothaman Jayaraman <Ragothaman.Jayaraman@cavium.com>
Signed-off-by: Srisivasubramanian Srinivasan <Srisivasubramanian.Srinivasan@cavium.com>
---
drivers/crypto/cpt/base/cpt.h | 129 +++++
drivers/crypto/cpt/base/cpt_ops.c | 1021 +++++++++++++++++++++++++++++++++++++
2 files changed, 1150 insertions(+)
diff --git a/drivers/crypto/cpt/base/cpt.h b/drivers/crypto/cpt/base/cpt.h
index 11407ae..54b1cb6 100644
--- a/drivers/crypto/cpt/base/cpt.h
+++ b/drivers/crypto/cpt/base/cpt.h
@@ -54,6 +54,135 @@
void *marker;
} app_data_t;
+/*
+ * Parameters for Flexi Crypto
+ * requests
+ */
+#define VALID_AAD_BUF 0x01
+#define VALID_MAC_BUF 0x02
+#define VALID_IV_BUF 0x04
+#define SINGLE_BUF_INPLACE 0x08
+#define SINGLE_BUF_HEADTAILROOM 0x10
+
+#define ENCR_IV_OFFSET(__d_offs) ((__d_offs >> 32) & 0xffff)
+#define ENCR_OFFSET(__d_offs) ((__d_offs >> 16) & 0xffff)
+#define AUTH_OFFSET(__d_offs) (__d_offs & 0xffff)
+#define ENCR_DLEN(__d_lens) (__d_lens >> 32)
+#define AUTH_DLEN(__d_lens) (__d_lens & 0xffffffff)
+
+typedef struct fc_params {
+ /* 0th cache line */
+ union {
+ buf_ptr_t bufs[1];
+ struct {
+ iov_ptr_t *src_iov;
+ iov_ptr_t *dst_iov;
+ };
+ };
+ void *iv_buf;
+ void *auth_iv_buf;
+ buf_ptr_t meta_buf;
+ buf_ptr_t ctx_buf;
+ uint64_t rsvd2;
+
+ /* 1st cache line */
+ buf_ptr_t aad_buf;
+ buf_ptr_t mac_buf;
+
+} fc_params_t;
+
+/*
+ * Parameters for digest
+ * generate requests
+ * Only src_iov, op, ctx_buf, mac_buf, prep_req
+ * meta_buf, auth_data_len are used for digest gen.
+ */
+typedef struct fc_params digest_params_t;
+
+/* Cipher Algorithms */
+typedef mc_cipher_type_t cipher_type_t;
+
+/* Auth Algorithms */
+typedef mc_hash_type_t auth_type_t;
+
+/* Flexi Crypto Operations */
+/*
+ * Encr | Encr + Hmac | HASH-HMAC generation
+ */
+/*
+ * ZUC/SNOW3g enc cipher/cipher+auth/auth-gen operation
+ */
+/*
+ * kasumi enc cipher/cipher+auth/auth-gen operation
+ * F8 iv_buf: 64 bits Bigendian format
+ * COUNT[63-32] || BEARER[31-27] ||
+ * DIRECTION[26] || 0...0[25-0]
+ * F9 mac gen auth_iv_buf: 64 bits BE + 8 bits
+ * COUNT[63-32] || FRESH[31-0]
+ * 0...0[7-1] || DIRECTION[0]
+ */
+void *cpt_fc_enc_hmac_prep(uint32_t flags,
+ uint64_t d_offs,
+ uint64_t d_lens,
+ fc_params_t *params,
+ void *op,
+ int *ret);
+/*
+ * Decr | Decr + Hmac
+ */
+/*
+ * ZUC/SNOW3g dec cipher/cipher+auth operation
+ */
+/*
+ * kasumi dec cipher/cipher+auth/ operation
+ * F8 iv_buf: 64 bits Bigendian format
+ * COUNT[63-32] || BEARER[31-27] ||
+ * DIRECTION[26] || 0...0[25-0]
+ */
+void *cpt_fc_dec_hmac_prep(uint32_t flags,
+ uint64_t d_offs,
+ uint64_t d_lens,
+ fc_params_t *params,
+ void *op,
+ int *ret);
+
+/* Flexi Crypto Ctrl Operations */
+int32_t cpt_fc_ciph_set_key(cpt_instance_t *inst,
+ void *ctx,
+ cipher_type_t type,
+ uint8_t *key,
+ uint16_t key_len,
+ uint8_t *salt);
+
+int32_t cpt_fc_ciph_set_iv(cpt_instance_t *inst,
+ void *ctx,
+ uint8_t *iv,
+ uint16_t iv_len);
+
+int32_t cpt_fc_auth_set_key(cpt_instance_t *inst,
+ void *ctx,
+ auth_type_t type,
+ uint8_t *key,
+ uint16_t key_len,
+ uint16_t mac_len);
+
+void
+cpt_fc_salt_update(void *ctx,
+ uint8_t *salt);
+/*
+ * Get's size of contiguous meta buffer
+ * to be allocated per op
+ */
+int32_t cpt_fc_get_op_meta_len(void);
+
+/* Get context length for a session */
+int32_t cpt_fc_get_ctx_len(void);
+
+/* Provides meta length required when it is
+ * direct mode i.e single buf inplace
+ */
+int32_t cpt_fc_get_op_sb_meta_len(void);
+
/* Instance operations */
/* Enqueue an SE/AE request */
diff --git a/drivers/crypto/cpt/base/cpt_ops.c b/drivers/crypto/cpt/base/cpt_ops.c
index e340006..31f8064 100644
--- a/drivers/crypto/cpt/base/cpt_ops.c
+++ b/drivers/crypto/cpt/base/cpt_ops.c
@@ -86,6 +86,14 @@ int32_t cpt_fc_get_ctx_len(void)
return sizeof(struct cpt_ctx);
}
+inline void
+cpt_fc_salt_update(void *ctx,
+ uint8_t *salt)
+{
+ struct cpt_ctx *cpt_ctx = ctx;
+ memcpy(&cpt_ctx->fctx.enc.encr_iv, salt, 4);
+}
+
int
cpt_fc_ciph_set_key(cpt_instance_t *instance,
void *ctx, cipher_type_t type, uint8_t *key,
@@ -306,3 +314,1016 @@ int32_t cpt_fc_get_ctx_len(void)
*ctrl_flags = htobe64(*ctrl_flags);
return 0;
}
+
+static inline uint32_t
+fill_sg_comp(sg_comp_t *list,
+ uint32_t i,
+ phys_addr_t dma_addr,
+ void *vaddr,
+ uint32_t size)
+{
+ sg_comp_t *to = &list[i>>2];
+
+ to->u.s.len[i%4] = htobe16(size);
+ to->ptr[i%4] = htobe64(dma_addr);
+ (void) vaddr;
+ i++;
+ return i;
+}
+
+static inline uint32_t
+fill_sg_comp_from_buf(sg_comp_t *list,
+ uint32_t i,
+ buf_ptr_t *from)
+{
+ sg_comp_t *to = &list[i>>2];
+
+ to->u.s.len[i%4] = htobe16(from->size);
+ to->ptr[i%4] = htobe64(from->dma_addr);
+ i++;
+ return i;
+}
+
+static inline uint32_t
+fill_sg_comp_from_buf_min(sg_comp_t *list,
+ uint32_t i,
+ buf_ptr_t *from,
+ uint32_t *psize)
+{
+ sg_comp_t *to = &list[i >> 2];
+ uint32_t size = *psize;
+ uint32_t e_len;
+
+ e_len = (size > from->size) ? from->size : size;
+ to->u.s.len[i % 4] = htobe16(e_len);
+ to->ptr[i % 4] = htobe64(from->dma_addr);
+ *psize -= e_len;
+ i++;
+ return i;
+}
+
+/*
+ * This fills the MC expected SGIO list
+ * from IOV given by user.
+ */
+static inline uint32_t
+fill_sg_comp_from_iov(sg_comp_t *list,
+ uint32_t i,
+ iov_ptr_t *from, uint32_t from_offset,
+ uint32_t *psize, buf_ptr_t *extra_buf,
+ uint32_t extra_offset)
+{
+ int32_t j;
+ uint32_t extra_len = extra_buf ? extra_buf->size : 0;
+ uint32_t size = *psize - extra_len;
+ buf_ptr_t *bufs;
+
+ bufs = from->bufs;
+ for (j = 0; (j < from->buf_cnt) && size; j++) {
+ phys_addr_t e_dma_addr;
+ uint32_t e_len;
+ sg_comp_t *to = &list[i >> 2];
+
+ if (!bufs[j].size)
+ continue;
+
+ if (unlikely(from_offset)) {
+ if (from_offset >= bufs[j].size) {
+ from_offset -= bufs[j].size;
+ continue;
+ }
+ e_dma_addr = bufs[j].dma_addr + from_offset;
+ e_len = (size > (bufs[j].size - from_offset)) ?
+ (bufs[j].size - from_offset) : size;
+ from_offset = 0;
+ } else {
+ e_dma_addr = bufs[j].dma_addr;
+ e_len = (size > bufs[j].size) ?
+ bufs[j].size : size;
+ }
+
+ to->u.s.len[i % 4] = htobe16(e_len);
+ to->ptr[i % 4] = htobe64(e_dma_addr);
+
+ if (extra_len && (e_len >= extra_offset)) {
+ /* Break the data at given offset */
+ uint32_t next_len = e_len - extra_offset;
+ phys_addr_t next_dma = e_dma_addr + extra_offset;
+
+ if (!extra_offset) {
+ i--;
+ } else {
+ e_len = extra_offset;
+ size -= e_len;
+ to->u.s.len[i % 4] = htobe16(e_len);
+ }
+
+ /* Insert extra data ptr */
+ if (extra_len) {
+ i++;
+ to = &list[i >> 2];
+ to->u.s.len[i % 4] = htobe16(extra_buf->size);
+ to->ptr[i % 4] = htobe64(extra_buf->dma_addr);
+
+ /* size already decremented by extra len */
+ }
+
+ /* insert the rest of the data */
+ if (next_len) {
+ i++;
+ to = &list[i >> 2];
+ to->u.s.len[i % 4] = htobe16(next_len);
+ to->ptr[i % 4] = htobe64(next_dma);
+ size -= next_len;
+ }
+ extra_len = 0;
+
+ } else {
+ size -= e_len;
+ }
+ if (extra_offset)
+ extra_offset -= size;
+ i++;
+ }
+
+ *psize = size;
+ return (uint32_t)i;
+}
+
+static inline int __attribute__((always_inline))
+cpt_enc_hmac_prep(uint32_t flags,
+ uint64_t d_offs,
+ uint64_t d_lens,
+ fc_params_t *fc_params,
+ void *op,
+ void **prep_req)
+{
+ uint32_t iv_offset = 0;
+ int32_t inputlen, outputlen, enc_dlen, auth_dlen;
+ struct cpt_ctx *cpt_ctx;
+ uint32_t cipher_type, hash_type;
+ uint32_t mac_len, size;
+ uint8_t iv_len = 16;
+ cpt_request_info_t *req;
+ buf_ptr_t *meta_p, *aad_buf = NULL;
+ uint32_t encr_offset, auth_offset;
+ uint32_t encr_data_len, auth_data_len, aad_len = 0;
+ uint32_t passthrough_len = 0;
+ void *m_vaddr, *offset_vaddr;
+ uint64_t m_dma, offset_dma, ctx_dma;
+ vq_cmd_word0_t vq_cmd_w0;
+ vq_cmd_word3_t vq_cmd_w3;
+ void *c_vaddr;
+ uint64_t c_dma;
+ int32_t m_size;
+ opcode_info_t opcode;
+
+ meta_p = &fc_params->meta_buf;
+#ifdef CPTVF_STRICT_PARAM_CHECK
+ if (!fc_params || !meta_p->vaddr || !meta_p->size)
+ return ERR_BAD_INPUT_ARG;
+#endif
+ m_vaddr = meta_p->vaddr;
+ m_dma = meta_p->dma_addr;
+ m_size = meta_p->size;
+
+ encr_offset = ENCR_OFFSET(d_offs);
+ auth_offset = AUTH_OFFSET(d_offs);
+ encr_data_len = ENCR_DLEN(d_lens);
+ auth_data_len = AUTH_DLEN(d_lens);
+ if (unlikely(flags & VALID_AAD_BUF)) {
+ /*
+ * We dont support both aad
+ * and auth data separately
+ */
+ auth_data_len = 0;
+ auth_offset = 0;
+ aad_len = fc_params->aad_buf.size;
+ aad_buf = &fc_params->aad_buf;
+ }
+ cpt_ctx = fc_params->ctx_buf.vaddr;
+ cipher_type = cpt_ctx->enc_cipher;
+ hash_type = cpt_ctx->hash_type;
+ mac_len = cpt_ctx->mac_len;
+
+ /*
+ * Save initial space that followed app data for completion code &
+ * alternate completion code to fall in same cache line as app data
+ */
+ m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE;
+ m_dma += COMPLETION_CODE_SIZE;
+ size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) -
+ (uint8_t *)m_vaddr;
+
+ c_vaddr = (uint8_t *)m_vaddr + size;
+ c_dma = m_dma + size;
+ size += sizeof(cpt_res_s_t);
+
+ m_vaddr = (uint8_t *)m_vaddr + size;
+ m_dma += size;
+ m_size -= size;
+
+ /* start cpt request info struct at 8 byte boundary */
+ size = (uint8_t *)RTE_PTR_ALIGN(m_vaddr, 8) -
+ (uint8_t *)m_vaddr;
+
+ req = (cpt_request_info_t *)((uint8_t *)m_vaddr + size);
+
+ size += sizeof(cpt_request_info_t);
+ m_vaddr = (uint8_t *)m_vaddr + size;
+ m_dma += size;
+ m_size -= size;
+
+ if (hash_type == GMAC_TYPE)
+ encr_data_len = 0;
+
+ if (unlikely(!(flags & VALID_IV_BUF))) {
+ iv_len = 0;
+ iv_offset = ENCR_IV_OFFSET(d_offs);
+ }
+
+ if (unlikely(flags & VALID_AAD_BUF)) {
+ /*
+ * When AAD is given, data above encr_offset is pass through
+ * Since AAD is given as separate pointer and not as offset,
+ * this is a special case as we need to fragment input data
+ * into passthrough + encr_data and then insert AAD in between.
+ */
+ if (hash_type != GMAC_TYPE) {
+ passthrough_len = encr_offset;
+ auth_offset = passthrough_len + iv_len;
+ encr_offset = passthrough_len + aad_len + iv_len;
+ auth_data_len = aad_len + encr_data_len;
+ } else {
+ passthrough_len = 16 + aad_len;
+ auth_offset = passthrough_len + iv_len;
+ auth_data_len = aad_len;
+ }
+ } else {
+ encr_offset += iv_len;
+ auth_offset += iv_len;
+ }
+
+ /* Initialising ctrl and opcode
+ * fields in cpt request structure
+ */
+
+ req->se_req = SE_CORE_REQ;
+ /*
+ * We are using DMA mode but indicate that
+ * SGIO list is already populated.
+ */
+ req->dma_mode = CTRL_DMA_MODE_SGIO;
+
+ /* Encryption */
+ opcode.s.major = MAJOR_OP_FC;
+ opcode.s.minor = 0;
+
+ auth_dlen = auth_offset + auth_data_len;
+ enc_dlen = encr_data_len + encr_offset;
+ if (unlikely(encr_data_len & 0xf)) {
+ if ((cipher_type == DES3_CBC) || (cipher_type == DES3_ECB))
+ enc_dlen = ROUNDUP8(encr_data_len) + encr_offset;
+ else if (likely((cipher_type == AES_CBC) ||
+ (cipher_type == AES_ECB)))
+ enc_dlen = ROUNDUP16(encr_data_len) + encr_offset;
+ }
+
+ /* TODO: MC issue */
+ if (unlikely(hash_type == GMAC_TYPE)) {
+ encr_offset = auth_dlen;
+ enc_dlen = 0;
+ }
+
+ if (unlikely(auth_dlen > enc_dlen)) {
+ inputlen = auth_dlen;
+ outputlen = auth_dlen + mac_len;
+ } else {
+ inputlen = enc_dlen;
+ outputlen = enc_dlen + mac_len;
+ }
+
+ /*GP op header */
+ vq_cmd_w0.u64 = 0;
+ vq_cmd_w0.s.param1 = htobe16(encr_data_len);
+ vq_cmd_w0.s.param2 = htobe16(auth_data_len);
+ /*
+ * In 83XX since we have a limitation of
+ * IV & Offset control word not part of instruction
+ * and need to be part of Data Buffer, we check if
+ * head room is there and then only do the Direct mode processing
+ */
+ if (likely((flags & SINGLE_BUF_INPLACE) &&
+ (flags & SINGLE_BUF_HEADTAILROOM))) {
+ void *dm_vaddr = fc_params->bufs[0].vaddr;
+ uint64_t dm_dma_addr = fc_params->bufs[0].dma_addr;
+ /*
+ * This flag indicates that there is 24 bytes head room and
+ * 8 bytes tail room available, so that we get to do
+ * DIRECT MODE with limitation
+ */
+
+ offset_vaddr = (uint8_t *)dm_vaddr - OFF_CTRL_LEN - iv_len;
+ offset_dma = dm_dma_addr - OFF_CTRL_LEN - iv_len;
+
+ /* DPTR */
+ req->ist.ei1 = offset_dma;
+ /* RPTR should just exclude offset control word */
+ req->ist.ei2 = dm_dma_addr - iv_len;
+ req->alternate_caddr = (uint64_t *)((uint8_t *)dm_vaddr
+ + outputlen - iv_len);
+ /* *req->alternate_caddr = ((uint64_t)0xdeadbeefdeadbeef) */
+
+ vq_cmd_w0.s.dlen = htobe16(inputlen + OFF_CTRL_LEN);
+
+ vq_cmd_w0.s.opcode = htobe16(opcode.flags);
+
+ if (likely(iv_len)) {
+ uint64_t *dest = (uint64_t *)((uint8_t *)offset_vaddr
+ + OFF_CTRL_LEN);
+ uint64_t *src = fc_params->iv_buf;
+ dest[0] = src[0];
+ dest[1] = src[1];
+ }
+
+ *(uint64_t *)offset_vaddr =
+ htobe64(((uint64_t)encr_offset << 16) |
+ ((uint64_t)iv_offset << 8) |
+ ((uint64_t)auth_offset));
+
+ } else {
+ uint32_t i, g_size_bytes, s_size_bytes;
+ uint64_t dptr_dma, rptr_dma;
+ sg_comp_t *gather_comp;
+ sg_comp_t *scatter_comp;
+ uint8_t *in_buffer;
+
+ /* This falls under strict SG mode */
+ offset_vaddr = m_vaddr;
+ offset_dma = m_dma;
+ size = OFF_CTRL_LEN + iv_len;
+
+ m_vaddr = (uint8_t *)m_vaddr + size;
+ m_dma += size;
+ m_size -= size;
+
+ opcode.s.major |= DMA_MODE;
+
+ vq_cmd_w0.s.opcode = htobe16(opcode.flags);
+
+ if (likely(iv_len)) {
+ uint64_t *dest = (uint64_t *)((uint8_t *)offset_vaddr
+ + OFF_CTRL_LEN);
+ uint64_t *src = fc_params->iv_buf;
+ dest[0] = src[0];
+ dest[1] = src[1];
+ }
+
+ *(uint64_t *)offset_vaddr =
+ htobe64(((uint64_t)encr_offset << 16) |
+ ((uint64_t)iv_offset << 8) |
+ ((uint64_t)auth_offset));
+
+ /* DPTR has SG list */
+ in_buffer = m_vaddr;
+ dptr_dma = m_dma;
+
+ ((uint16_t *)in_buffer)[0] = 0;
+ ((uint16_t *)in_buffer)[1] = 0;
+
+ /* TODO Add error check if space will be sufficient */
+ gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8);
+
+ /*
+ * Input Gather List
+ */
+
+ i = 0;
+
+ /* Offset control word that includes iv */
+ i = fill_sg_comp(gather_comp, i, offset_dma,
+ offset_vaddr, OFF_CTRL_LEN + iv_len);
+
+ /* Add input data */
+ size = inputlen - iv_len;
+ if (likely(size)) {
+ uint32_t aad_offset = aad_len ? passthrough_len : 0;
+
+ if (unlikely(flags & SINGLE_BUF_INPLACE)) {
+ i = fill_sg_comp_from_buf_min(gather_comp, i,
+ fc_params->bufs,
+ &size);
+ } else {
+
+ i = fill_sg_comp_from_iov(gather_comp, i,
+ fc_params->src_iov,
+ 0, &size,
+ aad_buf, aad_offset);
+ }
+
+ if (unlikely(size)) {
+ PMD_TX_LOG(ERR, "Insufficient buffer space,"
+ " size %d need\n", size);
+ return ERR_BAD_INPUT_ARG;
+ }
+ }
+ ((uint16_t *)in_buffer)[2] = htobe16(i);
+ g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
+
+ /*
+ * Output Scatter list
+ */
+ i = 0;
+ scatter_comp =
+ (sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes);
+
+ /* Add IV */
+ if (likely(iv_len)) {
+ i = fill_sg_comp(scatter_comp, i,
+ offset_dma + OFF_CTRL_LEN,
+ (uint8_t *)offset_vaddr + OFF_CTRL_LEN,
+ iv_len);
+ }
+
+ /* output data or output data + digest*/
+ if (unlikely(flags & VALID_MAC_BUF)) {
+ size = outputlen - iv_len - mac_len;
+ if (size) {
+ uint32_t aad_offset =
+ aad_len ? passthrough_len : 0;
+
+ if (unlikely(flags & SINGLE_BUF_INPLACE)) {
+ i = fill_sg_comp_from_buf_min(
+ scatter_comp,
+ i,
+ fc_params->bufs,
+ &size);
+ } else {
+ i = fill_sg_comp_from_iov(scatter_comp,
+ i,
+ fc_params->dst_iov,
+ 0,
+ &size,
+ aad_buf,
+ aad_offset);
+ }
+ if (size)
+ return ERR_BAD_INPUT_ARG;
+ }
+ /* mac_data */
+ if (mac_len) {
+ i = fill_sg_comp_from_buf(scatter_comp, i,
+ &fc_params->mac_buf);
+ }
+ } else {
+ /* Output including mac */
+ size = outputlen - iv_len;
+ if (likely(size)) {
+ uint32_t aad_offset =
+ aad_len ? passthrough_len : 0;
+
+ if (unlikely(flags & SINGLE_BUF_INPLACE)) {
+ i = fill_sg_comp_from_buf_min(
+ scatter_comp,
+ i,
+ fc_params->bufs,
+ &size);
+ } else {
+ i = fill_sg_comp_from_iov(scatter_comp,
+ i,
+ fc_params->dst_iov,
+ 0,
+ &size,
+ aad_buf,
+ aad_offset);
+ }
+ if (unlikely(size)) {
+ PMD_TX_LOG(ERR, "Insufficient buffer"
+ " space, size %d need\n", size);
+ return ERR_BAD_INPUT_ARG;
+ }
+ }
+ }
+ ((uint16_t *)in_buffer)[3] = htobe16(i);
+ s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
+
+ size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;
+
+ /* This is DPTR len incase of SG mode */
+ vq_cmd_w0.s.dlen = htobe16(size);
+
+ m_vaddr = (uint8_t *)m_vaddr + size;
+ m_dma += size;
+ m_size -= size;
+
+ /* cpt alternate completion address saved earlier */
+ req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8);
+ *req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);
+ rptr_dma = c_dma - 8;
+
+ req->ist.ei1 = dptr_dma;
+ req->ist.ei2 = rptr_dma;
+ }
+
+ /* First 16-bit swap then 64-bit swap */
+ /* TODO: HACK: Reverse the vq_cmd and cpt_req bit field definitions
+ * to eliminate all the swapping
+ */
+ vq_cmd_w0.u64 = htobe64(vq_cmd_w0.u64);
+
+ ctx_dma = fc_params->ctx_buf.dma_addr +
+ offsetof(struct cpt_ctx, fctx);
+ /* vq command w3 */
+ vq_cmd_w3.u64 = 0;
+ vq_cmd_w3.s.grp = 0;
+ vq_cmd_w3.s.cptr = ctx_dma;
+
+ /* 16 byte aligned cpt res address */
+ req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr);
+ *req->completion_addr = COMPLETION_CODE_INIT;
+ req->comp_baddr = c_dma;
+
+ /* Fill microcode part of instruction */
+ req->ist.ei0 = vq_cmd_w0.u64;
+ req->ist.ei3 = vq_cmd_w3.u64;
+
+ req->op = op;
+
+#ifdef CPTVF_STRICT_PARAM_CHECK
+ if (!(m_size >= 0)) {
+ PMD_TX_LOG(ERR, "!!! Buffer Overflow %d\n",
+ m_size);
+ abort();
+ }
+#endif
+ *prep_req = req;
+ return 0;
+}
+
+static inline int
+cpt_dec_hmac_prep(uint32_t flags,
+ uint64_t d_offs,
+ uint64_t d_lens,
+ fc_params_t *fc_params,
+ void *op,
+ void **prep_req)
+{
+ uint32_t iv_offset = 0, size;
+ int32_t inputlen, outputlen, enc_dlen, auth_dlen;
+ struct cpt_ctx *cpt_ctx;
+ int32_t hash_type, mac_len, m_size;
+ uint8_t iv_len = 16;
+ cpt_request_info_t *req;
+ buf_ptr_t *meta_p, *aad_buf = NULL;
+ uint32_t encr_offset, auth_offset;
+ uint32_t encr_data_len, auth_data_len, aad_len = 0;
+ uint32_t passthrough_len = 0;
+ void *m_vaddr, *offset_vaddr;
+ uint64_t m_dma, offset_dma, ctx_dma;
+ opcode_info_t opcode;
+ vq_cmd_word0_t vq_cmd_w0;
+ vq_cmd_word3_t vq_cmd_w3;
+ void *c_vaddr;
+ uint64_t c_dma;
+
+ meta_p = &fc_params->meta_buf;
+#ifdef CPTVF_STRICT_PARAM_CHECK
+ if (!fc_params || !meta_p->vaddr || !meta_p->size)
+ return ERR_BAD_INPUT_ARG;
+#endif
+ m_vaddr = meta_p->vaddr;
+ m_dma = meta_p->dma_addr;
+ m_size = meta_p->size;
+
+ encr_offset = ENCR_OFFSET(d_offs);
+ auth_offset = AUTH_OFFSET(d_offs);
+ encr_data_len = ENCR_DLEN(d_lens);
+ auth_data_len = AUTH_DLEN(d_lens);
+
+ if (unlikely(flags & VALID_AAD_BUF)) {
+ /*
+ * We dont support both aad
+ * and auth data separately
+ */
+ auth_data_len = 0;
+ auth_offset = 0;
+ aad_len = fc_params->aad_buf.size;
+ aad_buf = &fc_params->aad_buf;
+ }
+
+ cpt_ctx = fc_params->ctx_buf.vaddr;
+ hash_type = cpt_ctx->hash_type;
+ mac_len = cpt_ctx->mac_len;
+
+ if (hash_type == GMAC_TYPE)
+ encr_data_len = 0;
+
+ if (unlikely(!(flags & VALID_IV_BUF))) {
+ iv_len = 0;
+ iv_offset = ENCR_IV_OFFSET(d_offs);
+ }
+
+ if (unlikely(flags & VALID_AAD_BUF)) {
+ /*
+ * When AAD is given, data above encr_offset is pass through
+ * Since AAD is given as separate pointer and not as offset,
+ * this is a special case as we need to fragment input data
+ * into passthrough + encr_data and then insert AAD in between.
+ */
+ if (hash_type != GMAC_TYPE) {
+ passthrough_len = encr_offset;
+ auth_offset = passthrough_len + iv_len;
+ encr_offset = passthrough_len + aad_len + iv_len;
+ auth_data_len = aad_len + encr_data_len;
+ } else {
+ passthrough_len = 16 + aad_len;
+ auth_offset = passthrough_len + iv_len;
+ auth_data_len = aad_len;
+ }
+ } else {
+ encr_offset += iv_len;
+ auth_offset += iv_len;
+ }
+
+ /*
+ * Save initial space that followed app data for completion code &
+ * alternate completion code to fall in same cache line as app data
+ */
+ m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE;
+ m_dma += COMPLETION_CODE_SIZE;
+ size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) -
+ (uint8_t *)m_vaddr;
+ c_vaddr = (uint8_t *)m_vaddr + size;
+ c_dma = m_dma + size;
+ size += sizeof(cpt_res_s_t);
+
+ m_vaddr = (uint8_t *)m_vaddr + size;
+ m_dma += size;
+ m_size -= size;
+
+ /* start cpt request info structure at 8 byte alignment */
+ size = (uint8_t *)RTE_PTR_ALIGN(m_vaddr, 8) -
+ (uint8_t *)m_vaddr;
+
+ req = (cpt_request_info_t *)((uint8_t *)m_vaddr + size);
+
+ size += sizeof(cpt_request_info_t);
+ m_vaddr = (uint8_t *)m_vaddr + size;
+ m_dma += size;
+ m_size -= size;
+
+ /* Initialising ctrl and opcode
+ * fields in cpt request structure
+ */
+
+ req->se_req = SE_CORE_REQ;
+ /*
+ * We are using DMA mode but indicate that
+ * SGIO list is already populated.
+ */
+ req->dma_mode = CTRL_DMA_MODE_SGIO;
+
+ /* Decryption */
+ opcode.s.major = MAJOR_OP_FC;
+ opcode.s.minor = 1;
+
+ enc_dlen = encr_offset + encr_data_len;
+ auth_dlen = auth_offset + auth_data_len;
+
+ if (auth_dlen > enc_dlen) {
+ inputlen = auth_dlen + mac_len;
+ outputlen = auth_dlen;
+ } else {
+ inputlen = enc_dlen + mac_len;
+ outputlen = enc_dlen;
+ }
+
+ if (hash_type == GMAC_TYPE)
+ encr_offset = inputlen;
+
+ vq_cmd_w0.u64 = 0;
+ vq_cmd_w0.s.param1 = htobe16(encr_data_len);
+ vq_cmd_w0.s.param2 = htobe16(auth_data_len);
+
+ /*
+ * In 83XX since we have a limitation of
+ * IV & Offset control word not part of instruction
+ * and need to be part of Data Buffer, we check if
+ * head room is there and then only do the Direct mode processing
+ */
+ if (likely((flags & SINGLE_BUF_INPLACE) &&
+ (flags & SINGLE_BUF_HEADTAILROOM))) {
+ void *dm_vaddr = fc_params->bufs[0].vaddr;
+ uint64_t dm_dma_addr = fc_params->bufs[0].dma_addr;
+ /*
+ * This flag indicates that there is 24 bytes head room and
+ * 8 bytes tail room available, so that we get to do
+ * DIRECT MODE with limitation
+ */
+
+ offset_vaddr = (uint8_t *)dm_vaddr - OFF_CTRL_LEN - iv_len;
+ offset_dma = dm_dma_addr - OFF_CTRL_LEN - iv_len;
+ req->ist.ei1 = offset_dma;
+
+ /* RPTR should just exclude offset control word */
+ req->ist.ei2 = dm_dma_addr - iv_len;
+
+ /* In direct mode,changing the alternate completion code address
+ * to start of rptr,the assumption is that most auth iv failure
+ * are reported at first byte only.This will not give the
+ * correct alternate completion code the auth iv fail is
+ * reported after some bytes.
+ * FIXME
+ */
+ req->alternate_caddr = (uint64_t *)((uint8_t *)dm_vaddr -
+ iv_len);
+ /* since this is decryption,
+ * don't touch the content of
+ * alternate ccode space as it contains
+ * hmac.
+ */
+
+ vq_cmd_w0.s.dlen = htobe16(inputlen + OFF_CTRL_LEN);
+
+ vq_cmd_w0.s.opcode = htobe16(opcode.flags);
+
+ if (likely(iv_len)) {
+ uint64_t *dest = (uint64_t *)((uint8_t *)offset_vaddr +
+ OFF_CTRL_LEN);
+ uint64_t *src = fc_params->iv_buf;
+ dest[0] = src[0];
+ dest[1] = src[1];
+ }
+
+ *(uint64_t *)offset_vaddr =
+ htobe64(((uint64_t)encr_offset << 16) |
+ ((uint64_t)iv_offset << 8) |
+ ((uint64_t)auth_offset));
+
+ } else {
+ uint64_t dptr_dma, rptr_dma;
+ uint32_t g_size_bytes, s_size_bytes;
+ sg_comp_t *gather_comp;
+ sg_comp_t *scatter_comp;
+ uint8_t *in_buffer;
+ uint8_t i = 0;
+
+ /* This falls under strict SG mode */
+ offset_vaddr = m_vaddr;
+ offset_dma = m_dma;
+ size = OFF_CTRL_LEN + iv_len;
+
+ m_vaddr = (uint8_t *)m_vaddr + size;
+ m_dma += size;
+ m_size -= size;
+
+ opcode.s.major |= DMA_MODE;
+
+ vq_cmd_w0.s.opcode = htobe16(opcode.flags);
+
+ if (likely(iv_len)) {
+ uint64_t *dest = (uint64_t *)((uint8_t *)offset_vaddr +
+ OFF_CTRL_LEN);
+ uint64_t *src = fc_params->iv_buf;
+ dest[0] = src[0];
+ dest[1] = src[1];
+ }
+
+ *(uint64_t *)offset_vaddr =
+ htobe64(((uint64_t)encr_offset << 16) |
+ ((uint64_t)iv_offset << 8) |
+ ((uint64_t)auth_offset));
+
+
+ /* DPTR has SG list */
+ in_buffer = m_vaddr;
+ dptr_dma = m_dma;
+
+ ((uint16_t *)in_buffer)[0] = 0;
+ ((uint16_t *)in_buffer)[1] = 0;
+
+ /* TODO Add error check if space will be sufficient */
+ gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8);
+
+ /*
+ * Input Gather List
+ */
+ i = 0;
+
+ /* Offset control word that includes iv */
+ i = fill_sg_comp(gather_comp, i, offset_dma,
+ offset_vaddr, OFF_CTRL_LEN + iv_len);
+
+ /* Add input data */
+ if (flags & VALID_MAC_BUF) {
+ size = inputlen - iv_len - mac_len;
+ if (size) {
+ /* input data only */
+ if (unlikely(flags & SINGLE_BUF_INPLACE)) {
+ i = fill_sg_comp_from_buf_min(
+ gather_comp, i,
+ fc_params->bufs,
+ &size);
+ } else {
+ uint32_t aad_offset = aad_len ?
+ passthrough_len : 0;
+
+ i = fill_sg_comp_from_iov(gather_comp,
+ i,
+ fc_params->src_iov,
+ 0, &size,
+ aad_buf,
+ aad_offset);
+ }
+ if (size)
+ return ERR_BAD_INPUT_ARG;
+ }
+
+ /* mac data */
+ if (mac_len) {
+ i = fill_sg_comp_from_buf(gather_comp, i,
+ &fc_params->mac_buf);
+ }
+ } else {
+ /* input data + mac */
+ size = inputlen - iv_len;
+ if (size) {
+ if (unlikely(flags & SINGLE_BUF_INPLACE)) {
+ i = fill_sg_comp_from_buf_min(
+ gather_comp, i,
+ fc_params->bufs,
+ &size);
+ } else {
+ uint32_t aad_offset = aad_len ?
+ passthrough_len : 0;
+
+ if (!fc_params->src_iov)
+ return ERR_BAD_INPUT_ARG;
+
+ i = fill_sg_comp_from_iov(gather_comp, i,
+ fc_params->src_iov,
+ 0, &size,
+ aad_buf,
+ aad_offset);
+ }
+
+ if (size)
+ return ERR_BAD_INPUT_ARG;
+ }
+ }
+ ((uint16_t *)in_buffer)[2] = htobe16(i);
+ g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
+
+ /*
+ * Output Scatter List
+ */
+
+ i = 0;
+ scatter_comp =
+ (sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes);
+
+ /* Add iv */
+ if (iv_len) {
+ i = fill_sg_comp(scatter_comp, i,
+ offset_dma + OFF_CTRL_LEN,
+ (uint8_t *)offset_vaddr + OFF_CTRL_LEN,
+ iv_len);
+ }
+
+ /* Add output data */
+ size = outputlen - iv_len;
+ if (size) {
+ if (unlikely(flags & SINGLE_BUF_INPLACE)) {
+ /* handle single buffer here */
+ i = fill_sg_comp_from_buf_min(scatter_comp, i,
+ fc_params->bufs,
+ &size);
+ } else {
+ uint32_t aad_offset = aad_len ?
+ passthrough_len : 0;
+
+ if (!fc_params->dst_iov)
+ return ERR_BAD_INPUT_ARG;
+
+ i = fill_sg_comp_from_iov(scatter_comp, i,
+ fc_params->dst_iov, 0,
+ &size, aad_buf,
+ aad_offset);
+ }
+
+ if (unlikely(size))
+ return ERR_BAD_INPUT_ARG;
+ }
+
+ ((uint16_t *)in_buffer)[3] = htobe16(i);
+ s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
+
+ size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;
+
+ /* This is DPTR len incase of SG mode */
+ vq_cmd_w0.s.dlen = htobe16(size);
+
+ m_vaddr = (uint8_t *)m_vaddr + size;
+ m_dma += size;
+ m_size -= size;
+
+ /* cpt alternate completion address saved earlier */
+ req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8);
+ *req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);
+ rptr_dma = c_dma - 8;
+ size += COMPLETION_CODE_SIZE;
+
+ req->ist.ei1 = dptr_dma;
+ req->ist.ei2 = rptr_dma;
+ }
+
+ /* First 16-bit swap then 64-bit swap */
+ /* TODO: HACK: Reverse the vq_cmd and cpt_req bit field definitions
+ * to eliminate all the swapping
+ */
+ vq_cmd_w0.u64 = htobe64(vq_cmd_w0.u64);
+
+ ctx_dma = fc_params->ctx_buf.dma_addr +
+ offsetof(struct cpt_ctx, fctx);
+ /* vq command w3 */
+ vq_cmd_w3.u64 = 0;
+ vq_cmd_w3.s.grp = 0;
+ vq_cmd_w3.s.cptr = ctx_dma;
+
+ /* 16 byte aligned cpt res address */
+ req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr);
+ *req->completion_addr = COMPLETION_CODE_INIT;
+ req->comp_baddr = c_dma;
+
+ /* Fill microcode part of instruction */
+ req->ist.ei0 = vq_cmd_w0.u64;
+ req->ist.ei3 = vq_cmd_w3.u64;
+
+ req->op = op;
+
+#ifdef CPTVF_STRICT_PARAM_CHECK
+ if (!(m_size >= 0)) {
+ PMD_TX_LOG(ERR, "!!! Buffer Overflow %d\n",
+ m_size);
+ abort();
+ }
+#endif
+ *prep_req = req;
+ return 0;
+}
+
+void *
+cpt_fc_dec_hmac_prep(uint32_t flags,
+ uint64_t d_offs,
+ uint64_t d_lens,
+ fc_params_t *fc_params,
+ void *op, int *ret_val)
+{
+ struct cpt_ctx *ctx = fc_params->ctx_buf.vaddr;
+ uint8_t fc_type;
+ void *prep_req = NULL;
+ int ret;
+
+ fc_type = ctx->fc_type;
+
+ if (likely(fc_type == FC_GEN)) {
+ ret = cpt_dec_hmac_prep(flags, d_offs, d_lens,
+ fc_params, op, &prep_req);
+ } else {
+ /*
+ * For AUTH_ONLY case,
+ * MC only supports digest generation and verification
+ * should be done in software by memcmp()
+ */
+
+ ret = ERR_EIO;
+ }
+
+ if (unlikely(!prep_req))
+ *ret_val = ret;
+ return prep_req;
+}
+
+void *__hot
+cpt_fc_enc_hmac_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens,
+ fc_params_t *fc_params, void *op, int *ret_val)
+{
+ struct cpt_ctx *ctx = fc_params->ctx_buf.vaddr;
+ uint8_t fc_type;
+ void *prep_req = NULL;
+ int ret;
+
+ fc_type = ctx->fc_type;
+
+ /* Common api for rest of the ops */
+ if (likely(fc_type == FC_GEN)) {
+ ret = cpt_enc_hmac_prep(flags, d_offs, d_lens,
+ fc_params, op, &prep_req);
+ } else {
+ ret = ERR_EIO;
+ }
+
+ if (unlikely(!prep_req))
+ *ret_val = ret;
+ return prep_req;
+}
--
1.9.3
next prev parent reply other threads:[~2018-06-08 16:49 UTC|newest]
Thread overview: 185+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-06-08 16:45 [dpdk-dev] [PATCH 00/16] Adding Cavium's crypto device(CPT) driver Anoob Joseph
2018-06-08 16:45 ` [dpdk-dev] [PATCH 01/16] config: add Cavium CPT PMD skeleton Anoob Joseph
2018-06-14 2:56 ` Jerin Jacob
2018-06-19 13:39 ` De Lara Guarch, Pablo
2018-06-08 16:45 ` [dpdk-dev] [PATCH 02/16] crypto/cpt/base: add hardware definitions Cavium CPT Anoob Joseph
2018-06-14 3:02 ` Jerin Jacob
2018-06-08 16:45 ` [dpdk-dev] [PATCH 03/16] crypto/cpt/base: add hardware initialization API for CPT Anoob Joseph
2018-06-14 3:13 ` Jerin Jacob
2018-06-19 13:56 ` De Lara Guarch, Pablo
2018-06-08 16:45 ` [dpdk-dev] [PATCH 04/16] crypto/cpt/base: add hardware enq/deq " Anoob Joseph
2018-06-14 3:20 ` Jerin Jacob
2018-06-19 14:36 ` De Lara Guarch, Pablo
2018-06-19 15:08 ` De Lara Guarch, Pablo
2018-06-08 16:45 ` [dpdk-dev] [PATCH 05/16] crypto/cpt/base: add sym crypto session init " Anoob Joseph
2018-06-08 16:45 ` Anoob Joseph [this message]
2018-06-14 3:24 ` [dpdk-dev] [PATCH 06/16] crypto/cpt/base: add sym crypto request prepare " Jerin Jacob
2018-06-08 16:45 ` [dpdk-dev] [PATCH 07/16] crypto/cpt/base: add request prepare API for ZUC and SNOW3G Anoob Joseph
2018-06-08 16:45 ` [dpdk-dev] [PATCH 08/16] crypto/cpt/base: add request prepare API for Kasumi Anoob Joseph
2018-06-08 16:45 ` [dpdk-dev] [PATCH 09/16] crypto/cpt/base: add prepare request API for HASH and HMAC Anoob Joseph
2018-06-08 16:45 ` [dpdk-dev] [PATCH 10/16] crypto/cpt: add driver initializations Anoob Joseph
2018-06-19 15:25 ` De Lara Guarch, Pablo
2018-06-08 16:45 ` [dpdk-dev] [PATCH 11/16] crypto/cpt: add the basic device callback functions Anoob Joseph
2018-06-19 15:58 ` De Lara Guarch, Pablo
2018-06-08 16:45 ` [dpdk-dev] [PATCH 12/16] crypto/cpt: adds some more callback functions for CPT Anoob Joseph
2018-06-08 16:45 ` [dpdk-dev] [PATCH 13/16] crypto/cpt: adds the session related function callbacks Anoob Joseph
2018-06-08 16:45 ` [dpdk-dev] [PATCH 14/16] crypto/cpt: adds the enqueue and dequeue callbacks Anoob Joseph
2018-06-08 16:45 ` [dpdk-dev] [PATCH 15/16] doc: add Cavium's CPT guide Anoob Joseph
2018-06-19 16:10 ` De Lara Guarch, Pablo
2018-06-08 16:45 ` [dpdk-dev] [PATCH 16/16] crypto/cpt: build with meson Anoob Joseph
2018-06-18 14:54 ` De Lara Guarch, Pablo
2018-06-18 13:02 ` [dpdk-dev] [PATCH 00/16] Adding Cavium's crypto device(CPT) driver Anoob Joseph
2018-06-18 14:29 ` De Lara Guarch, Pablo
2018-07-09 22:55 ` De Lara Guarch, Pablo
2018-07-10 3:41 ` Anoob Joseph
2018-07-10 8:11 ` De Lara Guarch, Pablo
2018-09-04 3:58 ` [dpdk-dev] [PATCH v2 00/33] Adding Cavium's OcteonTX crypto PMD Anoob Joseph
2018-09-04 3:58 ` [dpdk-dev] [PATCH v2 01/33] config: add Cavium OcteonTX crypto PMD skeleton Anoob Joseph
2018-09-14 12:11 ` Akhil Goyal
2018-09-17 4:22 ` Joseph, Anoob
2018-09-17 10:37 ` Akhil Goyal
2018-09-17 11:42 ` Joseph, Anoob
2018-09-17 12:20 ` Akhil Goyal
2018-09-17 14:13 ` Joseph, Anoob
2018-09-17 14:36 ` Thomas Monjalon
2018-09-17 14:50 ` Joseph, Anoob
2018-09-18 12:31 ` Akhil Goyal
2018-09-18 12:40 ` Joseph
2018-09-18 12:44 ` Akhil Goyal
2018-09-04 3:58 ` [dpdk-dev] [PATCH v2 02/33] common/cpt: add common logging support Anoob Joseph
2018-09-14 12:29 ` Akhil Goyal
2018-09-04 3:58 ` [dpdk-dev] [PATCH v2 03/33] crypto/octeontx: add PCI probe and remove Anoob Joseph
2018-09-14 12:39 ` Akhil Goyal
2018-09-17 4:40 ` Joseph, Anoob
2018-09-17 10:34 ` Akhil Goyal
2018-09-17 10:38 ` Joseph, Anoob
2018-09-04 3:58 ` [dpdk-dev] [PATCH v2 04/33] crypto/octeontx: add register addresses Anoob Joseph
2018-09-04 3:58 ` [dpdk-dev] [PATCH v2 05/33] common/cpt: add common code for init routine Anoob Joseph
2018-09-17 10:45 ` Akhil Goyal
2018-09-17 11:46 ` Thomas Monjalon
2018-09-17 12:29 ` Joseph, Anoob
2018-09-17 12:32 ` Akhil Goyal
2018-09-17 12:51 ` Thomas Monjalon
2018-09-04 3:58 ` [dpdk-dev] [PATCH v2 06/33] crypto/octeontx: add hardware " Anoob Joseph
2018-09-04 3:58 ` [dpdk-dev] [PATCH v2 07/33] common/cpt: add hardware register defines Anoob Joseph
2018-09-17 11:18 ` Akhil Goyal
2018-09-17 14:15 ` Joseph, Anoob
2018-09-04 3:58 ` [dpdk-dev] [PATCH v2 08/33] crypto/octeontx: add hardware register access for misc poll Anoob Joseph
2018-09-04 3:58 ` [dpdk-dev] [PATCH v2 09/33] crypto/octeontx: adds symmetric capabilities Anoob Joseph
2018-09-17 12:01 ` Akhil Goyal
2018-09-17 12:35 ` Joseph, Anoob
2018-09-24 11:36 ` Joseph, Anoob
2018-09-28 11:14 ` Joseph, Anoob
2018-10-01 10:05 ` Thomas Monjalon
2018-10-08 15:59 ` Trahe, Fiona
2018-10-08 20:27 ` Thomas Monjalon
2018-10-10 5:39 ` Joseph, Anoob
2018-10-17 5:40 ` Joseph, Anoob
2018-10-19 21:09 ` Trahe, Fiona
2018-10-22 3:49 ` Joseph, Anoob
2018-10-22 6:51 ` Thomas Monjalon
2018-10-23 8:48 ` Joseph, Anoob
2018-10-23 9:03 ` Thomas Monjalon
2018-09-04 3:58 ` [dpdk-dev] [PATCH v2 10/33] common/cpt: add PMD ops helper functions Anoob Joseph
2018-09-17 12:47 ` Akhil Goyal
2018-09-17 14:17 ` Joseph, Anoob
2018-09-04 3:58 ` [dpdk-dev] [PATCH v2 11/33] crypto/octeontx: add global resource init Anoob Joseph
2018-09-04 3:58 ` [dpdk-dev] [PATCH v2 12/33] crypto/octeontx: add mailbox routines Anoob Joseph
2018-09-04 3:59 ` [dpdk-dev] [PATCH v2 13/33] crypto/octeontx: add basic dev ops Anoob Joseph
2018-09-04 3:59 ` [dpdk-dev] [PATCH v2 14/33] common/cpt: add common macros for queue pair ops Anoob Joseph
2018-09-04 3:59 ` [dpdk-dev] [PATCH v2 15/33] crypto/octeontx: add queue pair functions Anoob Joseph
2018-09-04 3:59 ` [dpdk-dev] [PATCH v2 16/33] common/cpt: add common code required for session management Anoob Joseph
2018-09-04 3:59 ` [dpdk-dev] [PATCH v2 17/33] crypto/octeontx: add session management ops Anoob Joseph
2018-09-04 3:59 ` [dpdk-dev] [PATCH v2 18/33] common/cpt: add common code for fill session data Anoob Joseph
2018-09-04 3:59 ` [dpdk-dev] [PATCH v2 19/33] crypto/octeontx: add supported sessions Anoob Joseph
2018-09-04 3:59 ` [dpdk-dev] [PATCH v2 20/33] common/cpt: add common defines for microcode Anoob Joseph
2018-09-04 3:59 ` [dpdk-dev] [PATCH v2 21/33] common/cpt: add microcode interface for encryption Anoob Joseph
2018-09-04 3:59 ` [dpdk-dev] [PATCH v2 22/33] common/cpt: add microcode interface for decryption Anoob Joseph
2018-09-04 3:59 ` [dpdk-dev] [PATCH v2 23/33] common/cpt: add crypo op enqueue request manager framework Anoob Joseph
2018-09-04 3:59 ` [dpdk-dev] [PATCH v2 24/33] common/cpt: add support for zuc and snow3g Anoob Joseph
2018-09-04 3:59 ` [dpdk-dev] [PATCH v2 25/33] common/cpt: add support for kasumi Anoob Joseph
2018-09-04 3:59 ` [dpdk-dev] [PATCH v2 26/33] common/cpt: add support for hash Anoob Joseph
2018-09-04 3:59 ` [dpdk-dev] [PATCH v2 27/33] crypto/octeontx: add routines to prepare instructions Anoob Joseph
2018-09-04 3:59 ` [dpdk-dev] [PATCH v2 28/33] common/cpt: add common code for enqueuing cpt instruction Anoob Joseph
2018-09-04 3:59 ` [dpdk-dev] [PATCH v2 29/33] crypto/octeontx: add enqueue burst op Anoob Joseph
2018-09-04 3:59 ` [dpdk-dev] [PATCH v2 30/33] common/cpt: add common code for cpt dequeue Anoob Joseph
2018-09-04 3:59 ` [dpdk-dev] [PATCH v2 31/33] crypto/octeontx: add dequeue burst op Anoob Joseph
2018-09-04 3:59 ` [dpdk-dev] [PATCH v2 32/33] test: adds validation test Anoob Joseph
2018-09-04 3:59 ` [dpdk-dev] [PATCH v2 33/33] doc: adds doc file Anoob Joseph
2018-09-17 13:30 ` Akhil Goyal
2018-09-14 9:16 ` [dpdk-dev] [PATCH v2 00/33] Adding Cavium's OcteonTX crypto PMD Joseph, Anoob
2018-09-14 9:42 ` Akhil Goyal
2018-10-05 12:58 ` [dpdk-dev] [PATCH v3 00/32] Adding Cavium's OCTEONTX " Anoob Joseph
2018-10-05 12:58 ` [dpdk-dev] [PATCH v3 01/32] common/cpt: add common logging support Anoob Joseph
2018-10-08 12:27 ` Thomas Monjalon
2018-10-08 13:07 ` Joseph, Anoob
2018-10-08 13:37 ` Thomas Monjalon
2018-10-08 14:39 ` Anoob Joseph
2018-10-05 12:58 ` [dpdk-dev] [PATCH v3 02/32] config: add Cavium OCTEONTX crypto PMD skeleton Anoob Joseph
2018-10-08 12:28 ` Thomas Monjalon
2018-10-05 12:58 ` [dpdk-dev] [PATCH v3 03/32] crypto/octeontx: add register addresses Anoob Joseph
2018-10-05 12:58 ` [dpdk-dev] [PATCH v3 04/32] common/cpt: add common code for init routine Anoob Joseph
2018-10-05 12:58 ` [dpdk-dev] [PATCH v3 05/32] crypto/octeontx: add hardware " Anoob Joseph
2018-10-05 12:58 ` [dpdk-dev] [PATCH v3 06/32] common/cpt: add hardware register defines Anoob Joseph
2018-10-05 12:58 ` [dpdk-dev] [PATCH v3 07/32] crypto/octeontx: add hardware register access for misc poll Anoob Joseph
2018-10-05 12:58 ` [dpdk-dev] [PATCH v3 08/32] crypto/octeontx: adds symmetric capabilities Anoob Joseph
2018-10-05 12:59 ` [dpdk-dev] [PATCH v3 09/32] common/cpt: add PMD ops helper functions Anoob Joseph
2018-10-05 12:59 ` [dpdk-dev] [PATCH v3 10/32] crypto/octeontx: add global resource init Anoob Joseph
2018-10-05 12:59 ` [dpdk-dev] [PATCH v3 11/32] crypto/octeontx: add mailbox routines Anoob Joseph
2018-10-05 12:59 ` [dpdk-dev] [PATCH v3 12/32] crypto/octeontx: add basic dev ops Anoob Joseph
2018-10-05 12:59 ` [dpdk-dev] [PATCH v3 13/32] common/cpt: add common macros for queue pair ops Anoob Joseph
2018-10-05 12:59 ` [dpdk-dev] [PATCH v3 14/32] crypto/octeontx: add queue pair functions Anoob Joseph
2018-10-05 12:59 ` [dpdk-dev] [PATCH v3 15/32] common/cpt: add common code required for session management Anoob Joseph
2018-10-05 12:59 ` [dpdk-dev] [PATCH v3 16/32] crypto/octeontx: add session management ops Anoob Joseph
2018-10-05 12:59 ` [dpdk-dev] [PATCH v3 17/32] common/cpt: add common code for fill session data Anoob Joseph
2018-10-05 12:59 ` [dpdk-dev] [PATCH v3 18/32] crypto/octeontx: add supported sessions Anoob Joseph
2018-10-05 12:59 ` [dpdk-dev] [PATCH v3 19/32] common/cpt: add common defines for microcode Anoob Joseph
2018-10-05 12:59 ` [dpdk-dev] [PATCH v3 20/32] common/cpt: add microcode interface for encryption Anoob Joseph
2018-10-05 12:59 ` [dpdk-dev] [PATCH v3 21/32] common/cpt: add microcode interface for decryption Anoob Joseph
2018-10-05 12:59 ` [dpdk-dev] [PATCH v3 22/32] common/cpt: add crypo op enqueue request manager framework Anoob Joseph
2018-10-05 12:59 ` [dpdk-dev] [PATCH v3 23/32] common/cpt: add support for zuc and snow3g Anoob Joseph
2018-10-05 12:59 ` [dpdk-dev] [PATCH v3 24/32] common/cpt: add support for kasumi Anoob Joseph
2018-10-05 12:59 ` [dpdk-dev] [PATCH v3 25/32] common/cpt: add support for hash Anoob Joseph
2018-10-05 12:59 ` [dpdk-dev] [PATCH v3 26/32] crypto/octeontx: add routines to prepare instructions Anoob Joseph
2018-10-05 12:59 ` [dpdk-dev] [PATCH v3 27/32] common/cpt: add common code for enqueuing cpt instruction Anoob Joseph
2018-10-05 12:59 ` [dpdk-dev] [PATCH v3 28/32] crypto/octeontx: add enqueue burst op Anoob Joseph
2018-10-05 12:59 ` [dpdk-dev] [PATCH v3 29/32] common/cpt: add common code for cpt dequeue Anoob Joseph
2018-10-05 12:59 ` [dpdk-dev] [PATCH v3 30/32] crypto/octeontx: add dequeue burst op Anoob Joseph
2018-10-05 12:59 ` [dpdk-dev] [PATCH v3 31/32] test: adds validation test Anoob Joseph
2018-10-08 12:33 ` Akhil Goyal
2018-10-08 12:56 ` Akhil Goyal
2018-10-05 12:59 ` [dpdk-dev] [PATCH v3 32/32] doc: adds doc file Anoob Joseph
2018-10-08 12:31 ` Thomas Monjalon
2018-10-05 13:04 ` [dpdk-dev] [PATCH v3 00/32] Adding Cavium's OCTEONTX crypto PMD Akhil Goyal
2018-10-05 13:13 ` Joseph, Anoob
2018-10-05 13:14 ` Akhil Goyal
2018-10-05 13:35 ` Joseph, Anoob
2018-10-08 12:33 ` Thomas Monjalon
2018-10-08 12:58 ` Joseph, Anoob
2018-10-08 13:06 ` Thomas Monjalon
2018-10-09 9:07 ` [dpdk-dev] [PATCH v4 00/23] Adding Cavium's OCTEON TX " Anoob Joseph
2018-10-09 9:07 ` [dpdk-dev] [PATCH v4 01/23] crypto/octeontx: add PMD skeleton Anoob Joseph
2018-10-09 9:07 ` [dpdk-dev] [PATCH v4 02/23] crypto/octeontx: add hardware init routine Anoob Joseph
2018-10-09 9:07 ` [dpdk-dev] [PATCH v4 03/23] crypto/octeontx: add hardware register access for misc poll Anoob Joseph
2018-10-09 9:07 ` [dpdk-dev] [PATCH v4 04/23] crypto/octeontx: add symmetric capabilities Anoob Joseph
2018-10-09 9:07 ` [dpdk-dev] [PATCH v4 05/23] common/cpt: add PMD ops helper functions Anoob Joseph
2018-10-09 9:07 ` [dpdk-dev] [PATCH v4 06/23] crypto/octeontx: add global resource init Anoob Joseph
2018-10-09 9:07 ` [dpdk-dev] [PATCH v4 07/23] crypto/octeontx: add mailbox routines Anoob Joseph
2018-10-09 9:07 ` [dpdk-dev] [PATCH v4 08/23] crypto/octeontx: add basic dev ops Anoob Joseph
2018-10-09 9:07 ` [dpdk-dev] [PATCH v4 09/23] crypto/octeontx: add queue pair functions Anoob Joseph
2018-10-09 9:07 ` [dpdk-dev] [PATCH v4 10/23] crypto/octeontx: add session management ops Anoob Joseph
2018-10-09 9:07 ` [dpdk-dev] [PATCH v4 11/23] crypto/octeontx: add supported sessions Anoob Joseph
2018-10-09 9:07 ` [dpdk-dev] [PATCH v4 12/23] common/cpt: add common defines for microcode Anoob Joseph
2018-10-09 9:07 ` [dpdk-dev] [PATCH v4 13/23] common/cpt: add microcode interface for encryption Anoob Joseph
2018-10-09 9:07 ` [dpdk-dev] [PATCH v4 14/23] common/cpt: add microcode interface for decryption Anoob Joseph
2018-10-09 9:07 ` [dpdk-dev] [PATCH v4 15/23] common/cpt: add crypo op enqueue request manager framework Anoob Joseph
2018-10-09 9:07 ` [dpdk-dev] [PATCH v4 16/23] common/cpt: support zuc and snow3g Anoob Joseph
2018-10-09 9:07 ` [dpdk-dev] [PATCH v4 17/23] common/cpt: support kasumi Anoob Joseph
2018-10-09 9:07 ` [dpdk-dev] [PATCH v4 18/23] common/cpt: support hash Anoob Joseph
2018-10-09 9:07 ` [dpdk-dev] [PATCH v4 19/23] crypto/octeontx: add routines to prepare instructions Anoob Joseph
2018-10-09 9:07 ` [dpdk-dev] [PATCH v4 20/23] crypto/octeontx: add enqueue burst op Anoob Joseph
2018-10-09 9:07 ` [dpdk-dev] [PATCH v4 21/23] crypto/octeontx: add dequeue " Anoob Joseph
2018-10-09 9:07 ` [dpdk-dev] [PATCH v4 22/23] test/crypto: add OCTEON TX unit tests Anoob Joseph
2018-10-09 9:07 ` [dpdk-dev] [PATCH v4 23/23] doc: add documentation for OCTEON TX crypto Anoob Joseph
2018-10-09 9:56 ` [dpdk-dev] [PATCH v4 00/23] Adding Cavium's OCTEON TX crypto PMD Thomas Monjalon
2018-10-09 10:29 ` Akhil Goyal
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1528476325-15585-7-git-send-email-anoob.joseph@caviumnetworks.com \
--to=anoob.joseph@caviumnetworks.com \
--cc=Nidadavolu.Murthy@cavium.com \
--cc=Ragothaman.Jayaraman@cavium.com \
--cc=Srisivasubramanian.Srinivasan@cavium.com \
--cc=akhil.goyal@nxp.com \
--cc=ankur.dwivedi@cavium.com \
--cc=dev@dpdk.org \
--cc=jerin.jacob@caviumnetworks.com \
--cc=narayanaprasad.athreya@caviumnetworks.com \
--cc=nithin.dabilpuram@cavium.com \
--cc=pablo.de.lara.guarch@intel.com \
--cc=thomas@monjalon.net \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).