From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by dpdk.org (Postfix) with ESMTP id 91B051D682; Fri, 15 Jun 2018 05:31:45 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 14 Jun 2018 20:31:43 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.51,225,1526367600"; d="scan'208";a="64276529" Received: from dpdk6.bj.intel.com ([172.16.182.94]) by fmsmga001.fm.intel.com with ESMTP; 14 Jun 2018 20:31:42 -0700 From: Wei Zhao To: dev@dpdk.org Cc: wenzhuo.lu@intel.com, stable@dpdk.org, Wei Zhao Date: Fri, 15 Jun 2018 11:10:59 +0800 Message-Id: <1529032259-9718-1-git-send-email-wei.zhao1@intel.com> X-Mailer: git-send-email 2.7.5 In-Reply-To: <1529029850-56080-1-git-send-email-wei.zhao1@intel.com> References: <1529029850-56080-1-git-send-email-wei.zhao1@intel.com> Subject: [dpdk-dev] [PATCH v4] net/ixgbe: fix mask bits register set error for FDIR X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 15 Jun 2018 03:31:48 -0000 MAC address bits in mask registers should be set to zero when the is mac mask is 0xFF, otherwise if it is 0x0 these bits should be to 0x3F. Fixes: 82fb702077f6 ("ixgbe: support new flow director modes for X550") Signed-off-by: Wei Zhao --- v2: -change mask bits set method to support more mac mask. v3: -change mask and with 0x3F to macro definition. v4: -fix mask bits bug in v3. --- drivers/net/ixgbe/ixgbe_fdir.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/net/ixgbe/ixgbe_fdir.c b/drivers/net/ixgbe/ixgbe_fdir.c index 6baf825..6ac806c 100644 --- a/drivers/net/ixgbe/ixgbe_fdir.c +++ b/drivers/net/ixgbe/ixgbe_fdir.c @@ -388,15 +388,17 @@ fdir_set_input_mask_x550(struct rte_eth_dev *dev) IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm); fdiripv6m = ((u32)0xFFFFU << IXGBE_FDIRIP6M_DIPM_SHIFT); - fdiripv6m |= IXGBE_FDIRIP6M_ALWAYS_MASK; + fdiripv6m |= IXGBE_FDIRIP6M_ALWAYS_MASK | IXGBE_FDIRIP6M_INNER_MAC; if (mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) fdiripv6m |= IXGBE_FDIRIP6M_TUNNEL_TYPE | IXGBE_FDIRIP6M_TNI_VNI; if (mode == RTE_FDIR_MODE_PERFECT_TUNNEL) { - mac_mask = info->mask.mac_addr_byte_mask; - fdiripv6m |= (mac_mask << IXGBE_FDIRIP6M_INNER_MAC_SHIFT) - & IXGBE_FDIRIP6M_INNER_MAC; + mac_mask = info->mask.mac_addr_byte_mask & + (IXGBE_FDIRIP6M_INNER_MAC >> + IXGBE_FDIRIP6M_INNER_MAC_SHIFT); + fdiripv6m &= ~((mac_mask << IXGBE_FDIRIP6M_INNER_MAC_SHIFT) & + IXGBE_FDIRIP6M_INNER_MAC); switch (info->mask.tunnel_type_mask) { case 0: -- 2.7.5