From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from NAM02-CY1-obe.outbound.protection.outlook.com (mail-cys01nam02on0060.outbound.protection.outlook.com [104.47.37.60]) by dpdk.org (Postfix) with ESMTP id 4CC442BF3 for ; Tue, 4 Sep 2018 06:03:07 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=CAVIUMNETWORKS.onmicrosoft.com; s=selector1-cavium-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=9z+sKPLJodDkrHx//9yAphJS73sa+cUED/nVtdGqVhc=; b=drSKH0g/PXM79nbqqTxKgGTTM7/nNX6F8Wbg43RtKWsA91F3r4mC6Tmj/nf7ju9en5pSaXiZEThdRta82NQPuJQjGFew+O9gn++eMJ64vd1jC9ott6CuFI+fNn5Q+wmIPF5XnfT4aL5sZlp49LtvUxwu9NSE+rl/RoTPGrbmYRg= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Anoob.Joseph@cavium.com; Received: from ajoseph83.caveonetworks.com.com (115.113.156.2) by BYAPR07MB4902.namprd07.prod.outlook.com (2603:10b6:a02:ef::25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1101.15; Tue, 4 Sep 2018 04:02:07 +0000 From: Anoob Joseph To: Akhil Goyal , Pablo de Lara , Thomas Monjalon Cc: Anoob Joseph , Jerin Jacob , Narayana Prasad , dev@dpdk.org, Ankur Dwivedi , Murthy NSSR , Nithin Dabilpuram , Ragothaman Jayaraman , Srisivasubramanian S , Tejasree Kondoj Date: Tue, 4 Sep 2018 09:28:53 +0530 Message-Id: <1536033560-21541-7-git-send-email-ajoseph@caviumnetworks.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1536033560-21541-1-git-send-email-ajoseph@caviumnetworks.com> References: <1528476325-15585-1-git-send-email-anoob.joseph@caviumnetworks.com> <1536033560-21541-1-git-send-email-ajoseph@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [115.113.156.2] X-ClientProxiedBy: BMXPR01CA0023.INDPRD01.PROD.OUTLOOK.COM (2603:1096:b00:d::33) To BYAPR07MB4902.namprd07.prod.outlook.com (2603:10b6:a02:ef::25) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 64425456-80cc-4ec2-6626-08d6121b3135 X-Microsoft-Antispam: BCL:0; PCL:0; RULEID:(7020095)(4652040)(8989137)(4534165)(4627221)(201703031133081)(201702281549075)(8990107)(5600074)(711020)(2017052603328)(7153060)(7193020); SRVR:BYAPR07MB4902; X-Microsoft-Exchange-Diagnostics: 1; BYAPR07MB4902; 3:CgeH2w7kGlxBV3b6mjQg42cQDs7RL0fG10q4A1hWhhUJu09G41yhfQEshNLA/PXW/zPbCNDGxJZ9F5rUMjipy2a4+oozM2WNNbKqv2S2GsTLyS1ZzA84nLizMq6btpoMqUwfcCeKAiSXV8GbUdG5EbhE1dAb8KQVq4M7Zvu+UtfXpNS0zhKLOgtutn5aarn92cuiY32jOb8ECqGePhrRWZHmbAkzQFPMDFhVgbvr6hSgCosavz3xYSPPSolg5SAa; 25:7W8fkKXizAfBUIbWRFWESqcBqX8QyswsZF7ULzehK0AEAhXkwWq7IuNb7LukS8yq/iqkzEK9UuxOr9dYvXMX3S5Id+MbNigRi71PVGo5EnLgvJEgelvO5m+Q5bD4LcAtHC962pf/g6ZzuI6DRO8VKYzF+/r9ASB5QTjMXDUEfJBh4BlsuAE9ipQkO2VWoF2f1p3j5bImrxy9FmabD+4ON5rBlvebv6uqB6TKRPn0tdXXiTrN7hXfH+hgUCS69F5nj39X6PMhitIxb1xevb8gsAFg7cKRrpg3i5IRJWyKhLVLyOC8MVjXD5EXhMBCYZMyhOPbOEUxvdu4kP3brra4RA==; 31:M/gvXzI83GDEcJN1/co8C5r+a258Up6VfsWq1lD0p/C0RD28LxYm19JvB0SXlomHCOaQw3CfG+M3SvvqZeUINy1HtT1QlJrg/0a6fAM2tBdf2vl4tRhG2bwZSepqdjS7xU0z2I+r+XrGaRacDKbP7J+wAvx9QOUyiUG2lhaeXcgPXCv0FQxdNaDstqZAfOiHwj8KbI8wqT1z4WUoildQgrHUOGAbBWmndYAU79Kp85o= X-MS-TrafficTypeDiagnostic: BYAPR07MB4902: X-Microsoft-Exchange-Diagnostics: 1; BYAPR07MB4902; 20:dJNmkUaDOPz9UwZKuJLHgGr8V1E4E9Z6CVMw9hemPCllQDdxAlW+Imn9VRziywk30CaVxsmhFlLwXyEGErfE4fKlQDWYaUcf3AfbQY84YftV71hqaVY8WSi1B9XL3U3alrzjGaRzyzfPGEPR7kZpoNR9xobXCzV3rFeRZHLgeLk+pRPklajVU6V2yx4t3X18xup3gMS6yR930AwSHFsZg8uxHG1ViWnhIPgGGa5SsuzGpRLFAPWcU65A0FEgOz3yfx82KJgEb6m2+evE2w8kb9IrMborxqpL4RlGWBBNq4CLySAb0j5EVg4Qspv3oXxnKsOLcSuoQxpJSI7cf+gA6JSxBfqI8ID6tt8rqOIKk870616Z25bUbpJKdC+ig4NB7fp6mlaabXBH7Xzia3G4OMB/abWlVdvpeEa/mcitbBgbzCUvg+QJsiZMWujVqcdeuZ6VBY4s3CSc5RyRpw+uTzC+spbfhFHrxToauYdlJawI6hZaMIUn4UyIxF0929kuY9O80WXWDJ7XxETGxAav/OaX+PHcymTKGvAkOi5Q/ReG8KfOE+9lzr/VHwPBr7wppJ+fMVr5CW3+J1KDfnqNVVCwHl1X9MrUkhWIFe/y9kU=; 4:Zx4Cnj/OfhJ/QTVa2dw6N7wyRlI5glx46JW0auM3DeMiU4UhVRVmDbDjCvrs/4qcEtD5NuLvUetSSA7DQY2woOiBuEoj5YAValymWZo/i7hKr8e3Iy0UO5H6BPm0NbgfZN0/PnxCjzEaLH+WpKKL5g7gObFoNsOEQxlKGneBhTpZihXLoNMxWjeo6SdPkKGc92qThxOw5d/c0N/lhR8nhLuXYj+vjAAq+GqsGYVir2f0j57ASf4bxjGVbzf1Xogdmw6r5JWwxXeYbF/p8PeBsA== X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-MS-Exchange-SenderADCheck: 1 X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(8211001083)(6040522)(2401047)(8121501046)(5005006)(10201501046)(93006095)(3231311)(944501410)(52105095)(3002001)(149027)(150027)(6041310)(20161123562045)(20161123564045)(20161123560045)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123558120)(201708071742011)(7699016); SRVR:BYAPR07MB4902; BCL:0; PCL:0; RULEID:; SRVR:BYAPR07MB4902; X-Forefront-PRVS: 0785459C39 X-Forefront-Antispam-Report: SFV:NSPM; SFS:(10009020)(366004)(396003)(136003)(346002)(376002)(39860400002)(199004)(189003)(26005)(51416003)(52116002)(76176011)(81166006)(305945005)(81156014)(7736002)(105586002)(316002)(6506007)(106356001)(6512007)(8936002)(446003)(54906003)(25786009)(6666003)(68736007)(50226002)(110136005)(53936002)(16586007)(42882007)(386003)(5660300001)(2906002)(72206003)(50466002)(6486002)(36756003)(6116002)(107886003)(2616005)(14444005)(186003)(3846002)(478600001)(66066001)(476003)(8676002)(47776003)(486006)(956004)(48376002)(11346002)(4326008)(97736004)(16526019); DIR:OUT; SFP:1101; SCL:1; SRVR:BYAPR07MB4902; H:ajoseph83.caveonetworks.com.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; Received-SPF: None (protection.outlook.com: cavium.com does not designate permitted sender hosts) X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; BYAPR07MB4902; 23:9P9XG4zeObS/P/KdGK+dnUbpZzNlfmCJBPOeWkVDu?= =?us-ascii?Q?FozglLiD68OuPOzEPVvsgUhm5pchPMiD7n8D7E/leiB4P5JKq47LP3zL0rBf?= =?us-ascii?Q?o/W4YPDtIOdS65nr+56CsOnNSA11CcMgJuvhzypDPF5OLmrMwMQHp4FBI/cN?= =?us-ascii?Q?UZF2JyZDKoNP3j+VTXb+rbhYFARV3mVfsYnvVPQV4x3W/s6REPKojmZLrSwM?= =?us-ascii?Q?tSjdsOSm32dnhRRacsqvUNYjbHhBwK+DJ6IX06Ae3a9HAGAiR0Suykuc2FVn?= =?us-ascii?Q?iwIjstfIj0rRQtXLyQ8FY5kle0UzwnqQFt9sehnuOEte2y+qf2YS8+xTcSlv?= =?us-ascii?Q?qS/220EUTacTcArNlZ9uwhCDzeLN58NH/82oQrfQyLucVP1sk/HoyVfxVSYM?= =?us-ascii?Q?6rjN68v1/T6wbrQEyigohY+++c/ROliFZ4wo9opgV0kfX1WNAZUw+/bJWoDU?= =?us-ascii?Q?5nE53zJSGaZf0J4kQgNDfrzLvEt49NG0kV0tGbjdn/aGQi4HaUSP25rxoAis?= =?us-ascii?Q?0uk81zxazUJBEH0RMwDIMFGb+oTIBXVqqZpvrcNHMrc7ZbxBe9ar8YLDMgfN?= =?us-ascii?Q?odE7EQxhAVwnx66P2T7lABCOKAHeS9q9Mu7xsLyv1E+qB5vAgiWakW8Z6C3G?= =?us-ascii?Q?QeNhtPMHf0rre52da49iLNUGM0IOgVSSPim9Ql7uxZTUFTSRhRIAw+t6NcI3?= =?us-ascii?Q?TS3Np9nmkX+42bEbDUbw5LB0xznkQkfV69Ty1Y4GDkVQclzVbBTs5QvqdvPr?= =?us-ascii?Q?8RaUQRTqVLN+GxBc+TOhURyePsAU1vBlP8QBzTfoDtWGZpJmR+zw44FbV1qK?= =?us-ascii?Q?NGbXYweY1OBwv3x5mnKneDKtauI8cTBnpM9GjHLLqM4lW4ssLYw36+fM31tu?= =?us-ascii?Q?hCspm7CSWhf5H6djPLtJAWeXC28O5GMvTPlAqOasM/w8YTdXdgGw7nhCeFi2?= =?us-ascii?Q?B0Q7etUul/FJ+Zlz2o/dzMz/InLufJLbI0sQ8WBk8/uxywONzqsxM8nF8oZt?= =?us-ascii?Q?nUaR++2oy3vsZrcLaMljdICBIL/pfwrfvLBxNrohdmgY/VvYaH2fqFWNGt6h?= =?us-ascii?Q?RP/Equg2vK6G79VnZJCMNKGdsxiAgHGrQyULtW/lgB0MqakcCQE2B/ZJNpgx?= =?us-ascii?Q?Uw1uEWP+nar4x/mWZ3avw98OFNhrPev0lz66a5SmCvMaCVS8q6oWpSdbmRKG?= =?us-ascii?Q?n+VIDozIhV9X5QuASL3zK6OHFxxcEAsVWsFhRGBQVlAbRpzN75MvjMap28dy?= =?us-ascii?Q?Wkby8py3Pu3ZGhKVD8=3D?= X-Microsoft-Antispam-Message-Info: 7Ue5KCNAnSvFOd06uMlDi9mUvEgHdI5amFq2uo6q7sUHv5R1BpRAa2djaYmVzXXvYqa0DtqjiOqx+64eGCO70/uLCCrhFir+3m+LEU0HIroB+AWriP77mnMVK4LB0p+o4oEANOGRaXnuolhJq+ndUz5V2rTVY5vKsV7MQqz2dqnrgNqPb7Q/MhUKcpKyWmspMIzjGTdkgOnuvIjcG3WbArR1Pn334GRAUBnsRNLcJd8AladtY2ctQbX55dsRhlA6LiXEMKJQNvFzqp1rx52jGjAoH7c71swfnAhjVSDjRO1oQ8rVCT616Vd2CmgE0egTGEDU5C66Me5Tp8bYQYo9REeCKVnAX2R5TZPOOiRRUV8= X-Microsoft-Exchange-Diagnostics: 1; BYAPR07MB4902; 6:xRoLzERA/KT/brHFGQi+flhIQby/nBt2R57Ll0jRsu7wyzAvBou8QFGwzvYs+eb1EiyYEWs0NLuduFw21H/vhB1DJpYIiPgL3ufRx/ig/ICwHC29SkV0r62u4dP3ENlpON5cZ4CfaNm78hdbrqAVGXfF7mHN+sFh/xBwixmM7YQGm0SSsI4OOmgXZCO+fCeuVVyKme7NAUwF55Reh3/hN4DyQ+X0xxxoXaXi2rA173Nbmh6eBiiumhDqSY6FWC/B7gINUmE6CocukoY1KXx/iUebehivM/l1jUhqquCX07z1WMqPJwNZQ3tMO/IzSkhPdNtgD7kIvTHwI63PHuaoEeE6dQ4o3pjDg/yXsnjqIDz2H8afOthc18+MP8NKl3OzUc3Cwg0xy6k61/Fi3p278iWyY8EesXa7XJ3WYstYlyXYF0DCxLd/IdPf14+dEGCasx7TEJVwuuf4/mcC+MYlbA==; 5:orGaXTaVvXiz58JkinDQqPT8H1gWQ2yEExLXe1yycY8frECsbfGQAKNBbI4R/hyxxAfnhdE2lOvbuR2P844symJSJqj23MK0NkeZYhZjzXlCWb0x349vmW/8L2Vs//nj3FpVotC4fk4Ea9vPMKKTnWOpmqmr9yIK5ECdceYfNgc=; 7:+HkNjfb9KNRGAp1WIc6+urAp+2O1FNp0lvpCDtNcSCmsukJG6NIW/XrDB2BNypf+7ImP/1sEGbcnXNPmyT9vygxhtrgZGhmc0eDdWdhCOCIh0hiVUYFF2td4Zlqo0MwepLic7xh/83dccczyAlrYisIQeOmC8Ovfb8c8bfTr8RPLYKyElRcMMi6Zw0yKiIfmagKuzft7XTtT/DKxMjlxzMiPiZYvO0FpZ5TFozN7p2stxZSIoHJx8LvsalrpHT8Z SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: caviumnetworks.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Sep 2018 04:02:07.8035 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 64425456-80cc-4ec2-6626-08d6121b3135 X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 711e4ccf-2e9b-4bcf-a551-4094005b6194 X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR07MB4902 Subject: [dpdk-dev] [PATCH v2 06/33] crypto/octeontx: add hardware init routine X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 04 Sep 2018 04:03:08 -0000 From: Anoob Joseph Adding hardware init routine for OcteonTX crypto device. A place holder is added for misc polling routine. That will be added in the further patches. Signed-off-by: Ankur Dwivedi Signed-off-by: Anoob Joseph Signed-off-by: Murthy NSSR Signed-off-by: Nithin Dabilpuram Signed-off-by: Ragothaman Jayaraman Signed-off-by: Srisivasubramanian S Signed-off-by: Tejasree Kondoj --- drivers/crypto/octeontx/Makefile | 1 + drivers/crypto/octeontx/meson.build | 1 + drivers/crypto/octeontx/otx_cryptodev_hw_access.c | 53 +++++++++++++ drivers/crypto/octeontx/otx_cryptodev_hw_access.h | 92 +++++++++++++++++++++++ drivers/crypto/octeontx/otx_cryptodev_ops.c | 89 +++++++++++++++++++++- 5 files changed, 235 insertions(+), 1 deletion(-) create mode 100644 drivers/crypto/octeontx/otx_cryptodev_hw_access.c diff --git a/drivers/crypto/octeontx/Makefile b/drivers/crypto/octeontx/Makefile index 12fec75..4582540 100644 --- a/drivers/crypto/octeontx/Makefile +++ b/drivers/crypto/octeontx/Makefile @@ -24,6 +24,7 @@ CFLAGS += -I$(RTE_SDK)/drivers/common/cpt # PMD code SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += otx_cryptodev.c +SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += otx_cryptodev_hw_access.c SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += otx_cryptodev_ops.c # export include files diff --git a/drivers/crypto/octeontx/meson.build b/drivers/crypto/octeontx/meson.build index 6564090..eca1cf1 100644 --- a/drivers/crypto/octeontx/meson.build +++ b/drivers/crypto/octeontx/meson.build @@ -8,6 +8,7 @@ deps += ['bus_pci'] name = 'octeontx_crypto' sources = files('otx_cryptodev.c', + 'otx_cryptodev_hw_access.c', 'otx_cryptodev_ops.c') cflags += '-DCPT_MODEL=CRYPTO_OCTEONTX' diff --git a/drivers/crypto/octeontx/otx_cryptodev_hw_access.c b/drivers/crypto/octeontx/otx_cryptodev_hw_access.c new file mode 100644 index 0000000..211b6ee --- /dev/null +++ b/drivers/crypto/octeontx/otx_cryptodev_hw_access.c @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2018 Cavium, Inc + */ +#include + +#include + +#include "otx_cryptodev_hw_access.h" + +#include "cpt_pmd_logs.h" + +static int +otx_cpt_vf_init(struct cpt_vf *cptvf) +{ + int ret = 0; + + /* Mark as VF driver */ + cptvf->flags |= CPT_FLAG_VF_DRIVER; + + CPT_LOG_DP_DEBUG("%s: %s done", cptvf->dev_name, __func__); + + return ret; +} + +void +otx_cpt_poll_misc(struct cpt_vf *cptvf) +{ + RTE_SET_USED(cptvf); +} + +int +otx_cpt_hw_init(struct cpt_vf *cptvf, void *pdev, void *reg_base, char *name) +{ + memset(cptvf, 0, sizeof(struct cpt_vf)); + + /* Bar0 base address */ + cptvf->reg_base = reg_base; + strncpy(cptvf->dev_name, name, 32); + + cptvf->nr_queues = 1; + cptvf->max_queues = 1; + cptvf->pdev = pdev; + + /* To clear if there are any pending mbox msgs */ + otx_cpt_poll_misc(cptvf); + + if (otx_cpt_vf_init(cptvf)) { + CPT_LOG_ERR("Failed to initialize CPT VF device"); + return -1; + } + + return 0; +} diff --git a/drivers/crypto/octeontx/otx_cryptodev_hw_access.h b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h index 288ee41..40db69c 100644 --- a/drivers/crypto/octeontx/otx_cryptodev_hw_access.h +++ b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h @@ -5,6 +5,90 @@ #ifndef _OTX_CRYPTODEV_HW_ACCESS_H_ #define _OTX_CRYPTODEV_HW_ACCESS_H_ +#include + +#include + +#include "cpt_common.h" + +/* Flags to indicate the features supported */ +#define CPT_FLAG_VF_DRIVER (uint16_t)(1 << 3) + +#define CPT_INTR_POLL_INTERVAL_MS (50) + +/* Default command queue length */ +#define DEFAULT_CMD_QCHUNKS 2 + +struct command_chunk { + uint8_t *head; + /**< 128-byte aligned real_vaddr */ + phys_addr_t dma_addr; + /**< 128-byte aligned real_dma_addr */ +}; + +/** + * Command queue structure + */ +struct command_queue { + uint32_t idx; + /**< Command queue host write idx */ + uint32_t cchunk; + uint8_t *qhead; + /**< Command queue head; instructions are inserted here */ + struct command_chunk chead[DEFAULT_CMD_QCHUNKS]; + /**< Command chunk list head */ +}; + +/** + * CPT VF device structure + */ +struct cpt_vf { + struct cpt_instance instance; + + uint8_t *reg_base; + /**< Register start address */ + struct command_queue cqueue; + /**< Command queue information */ + struct pending_queue pqueue; + /**< Pending queue information */ + struct cptvf_meta_info meta_info; + /**< Meta information per vf */ + + /* Below fields are accessed only in control path */ + + void *pdev; + /**< Env specific pdev representing the pci dev */ + uint32_t qlen; + /**< Qsize * CPT_INST_SIZE + alignment size(CPT_INST_SIZE + + * next chunk pointer size (8) + */ + uint32_t qsize; + /**< Calculated queue size */ + uint32_t nr_queues; + uint32_t max_queues; + + uint32_t chip_id; + /**< CPT device ID */ + uint16_t flags; + /**< Flags to hold device status bits */ + uint8_t vfid; + /**< Device index (0...CPT_MAX_VQ_NUM)*/ + uint8_t vftype; + /**< VF type of cpt_vf_type_t (SE_TYPE(2) or AE_TYPE(1) */ + uint8_t vfgrp; + /**< VF group (0 - 8) */ + uint8_t node; + /**< Operating node: Bits (46:44) in BAR0 address */ + + /* VF-PF mailbox communication */ + + bool pf_acked; + bool pf_nacked; + + char dev_name[32]; + /**< Device name */ +} __rte_cache_aligned; + /* * CPT Registers map for 81xx */ @@ -44,4 +128,12 @@ ((a) & 0x1) + 0x100000ll * (b) + \ 8ll * ((c) & 0x1)) +/* VF HAL functions */ + +void +otx_cpt_poll_misc(struct cpt_vf *cptvf); + +int +otx_cpt_hw_init(struct cpt_vf *cptvf, void *pdev, void *reg_base, char *name); + #endif /* _OTX_CRYPTODEV_HW_ACCESS_H_ */ diff --git a/drivers/crypto/octeontx/otx_cryptodev_ops.c b/drivers/crypto/octeontx/otx_cryptodev_ops.c index 1b5f108..d25f9c1 100644 --- a/drivers/crypto/octeontx/otx_cryptodev_ops.c +++ b/drivers/crypto/octeontx/otx_cryptodev_ops.c @@ -2,14 +2,101 @@ * Copyright(c) 2018 Cavium, Inc */ +#include +#include #include +#include + +#include "cpt_pmd_logs.h" #include "otx_cryptodev.h" +#include "otx_cryptodev_hw_access.h" #include "otx_cryptodev_ops.h" +/* Alarm routines */ + +static void +otx_cpt_alarm_cb(void *arg) +{ + struct cpt_vf *cptvf = arg; + otx_cpt_poll_misc(cptvf); + rte_eal_alarm_set(CPT_INTR_POLL_INTERVAL_MS * 1000, + otx_cpt_alarm_cb, cptvf); +} + +static int +otx_cpt_periodic_alarm_start(void *arg) +{ + return rte_eal_alarm_set(CPT_INTR_POLL_INTERVAL_MS * 1000, + otx_cpt_alarm_cb, arg); +} + int otx_cpt_dev_create(struct rte_cryptodev *c_dev) { - RTE_SET_USED(c_dev); + struct rte_pci_device *pdev = RTE_DEV_TO_PCI(c_dev->device); + struct cpt_vf *cptvf = NULL; + void *reg_base; + char dev_name[32]; + int ret; + + if (pdev->mem_resource[0].phys_addr == 0ULL) + return -EIO; + + /* for secondary processes, we don't initialise any further as primary + * has already done this work. + */ + if (rte_eal_process_type() != RTE_PROC_PRIMARY) + return 0; + + cptvf = rte_zmalloc_socket("otx_cryptodev_private_mem", + sizeof(struct cpt_vf), RTE_CACHE_LINE_SIZE, + rte_socket_id()); + + if (cptvf == NULL) { + CPT_LOG_ERR("Cannot allocate memory for device private data"); + return -ENOMEM; + } + + snprintf(dev_name, 32, "%02x:%02x.%x", + pdev->addr.bus, pdev->addr.devid, pdev->addr.function); + + reg_base = pdev->mem_resource[0].addr; + if (!reg_base) { + CPT_LOG_ERR("Failed to map BAR0 of %s", dev_name); + ret = -ENODEV; + goto fail; + } + + ret = otx_cpt_hw_init(cptvf, pdev, reg_base, dev_name); + if (ret) { + CPT_LOG_ERR("Failed to init cptvf %s", dev_name); + ret = -EIO; + goto fail; + } + + /* Start off timer for mailbox interrupts */ + otx_cpt_periodic_alarm_start(cptvf); + + c_dev->dev_ops = NULL; + + c_dev->enqueue_burst = NULL; + c_dev->dequeue_burst = NULL; + + c_dev->feature_flags = RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO | + RTE_CRYPTODEV_FF_HW_ACCELERATED | + RTE_CRYPTODEV_FF_SYM_OPERATION_CHAINING; + + /* Save dev private data */ + c_dev->data->dev_private = cptvf; + return 0; + +fail: + if (cptvf) { + /* Free private data allocated */ + rte_free(cptvf); + } + + return ret; } -- 2.7.4