From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from NAM01-BN3-obe.outbound.protection.outlook.com (mail-bn3nam01on0042.outbound.protection.outlook.com [104.47.33.42]) by dpdk.org (Postfix) with ESMTP id D6DF51B1CF for ; Fri, 5 Oct 2018 15:02:11 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=CAVIUMNETWORKS.onmicrosoft.com; s=selector1-cavium-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=szilEeRoXaEBvq5V6qEUVHHmGTUY2ZkkiD+lXcfmbqo=; b=dI5EpFCbPyzTHf4/bHVB9NSIMyhgp2ZlfLtpwHe6CiW3vRctd9Z8miOkn2FzqQIDqqmNUqhSN4nCVN7o87Z9dhszB+xsqtjN/2jJK2ij4kinVAy4ji8p4hBybcpnN3BphKDIobgEQeG89zIN2UghBEFqaCt2r66ab4dALXQtVYA= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Anoob.Joseph@cavium.com; Received: from ajoseph83.caveonetworks.com.com (115.113.156.2) by SN6PR07MB4910.namprd07.prod.outlook.com (2603:10b6:805:39::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1207.21; Fri, 5 Oct 2018 13:02:06 +0000 From: Anoob Joseph To: Akhil Goyal , Pablo de Lara , Thomas Monjalon Cc: Srisivasubramanian S , Jerin Jacob , Narayana Prasad , dev@dpdk.org, Ankur Dwivedi , Anoob Joseph , Murthy NSSR , Nithin Dabilpuram , Ragothaman Jayaraman , Tejasree Kondoj Date: Fri, 5 Oct 2018 18:29:15 +0530 Message-Id: <1538744363-30340-25-git-send-email-anoob.joseph@caviumnetworks.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1538744363-30340-1-git-send-email-anoob.joseph@caviumnetworks.com> References: <1536033560-21541-1-git-send-email-ajoseph@caviumnetworks.com> <1538744363-30340-1-git-send-email-anoob.joseph@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [115.113.156.2] X-ClientProxiedBy: MA1PR0101CA0036.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:22::22) To SN6PR07MB4910.namprd07.prod.outlook.com (2603:10b6:805:39::16) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 27c49869-81d4-4298-63cc-08d62ac2c326 X-Microsoft-Antispam: BCL:0; PCL:0; RULEID:(7020095)(4652040)(8989299)(4534185)(7168020)(4627221)(201703031133081)(201702281549075)(8990200)(5600074)(711020)(2017052603328)(7153060)(7193020); SRVR:SN6PR07MB4910; X-Microsoft-Exchange-Diagnostics: 1; SN6PR07MB4910; 3:Xc3QpLal7ldHd+VyT/kNsMfbx9GWVfV/QO1HZtTXvqHKa3WdtKBMX2nH70Xp7a41h17BLkm4QDcCZ0JKMF5oLe3gJV8aUR2FGPQwhUEulszAoXE8alHkArViMn9N5piztN/lmVPLeDVVf6ntC3Pw2PAuQsrDYEU/QbsEnKuC4QctyRx9tHwuatVbQYShP4Jvq76xJ/X1FrOYcTuZHbQjYcDN/+6pghLpsgJda2kLY4nYb12+fNfun1Qm8SUkXUFQ; 25:XlcqwAQGOxqwOuKpEOst9MsDJAUfZlbRmjKIOMu7SSutZFImBC9UxmyoEeoP1LknP7peiGrec9DaDnDHdz6SnhLA/W07Q5vmJsW8ExiYbnEALYGuV1mgVcFBRcHNQBaVjX1S9BL8pp0lE3xX07fRukFIadarHp871G3eKLz0ZGhgsaZNJfbfA9ta1QN5V3e2KhEv5McADza2cUXOaoxHjIDzXo5bu3q10qOxIkYlHiliWg/DVXkc6iC4ACQYFNegmyE4lxFgbKRKWocCWwfXs4LLOz5aBCjZbWR2AG2lJs90x+IPwHC2oPdcCT8J4qmK2qIjLnLTHRIowqMp1T3/4w==; 31:tPvnyFVlxZsJi6qKJwGg+we9Qm/4HG+gQRC+tm3nznKQZAr0QOts/b3bhJm7Zk4nVSK7G9VpbFUAYKzilufwAFPfUQ2ZcL78eAe1+A1BtOzlOJGPlAjJ4CpEia36treTJyeVpjdQAy1oRP/dlxMWojsjFcVPGMn3WEtbtmfxs9OT/PUsrhJbYIz8L7O3e0cxCDgxRmWGMyBa3Y8xkxp9sD+zY9/JN51ijfrXRfLZWjI= X-MS-TrafficTypeDiagnostic: SN6PR07MB4910: X-Microsoft-Exchange-Diagnostics: 1; SN6PR07MB4910; 20:kDReSPOAO4FyB+m7LhYvGM/qt1US5UrHY2LnP0kP6bcTlAjte1HYULvKrJ0mG3ivBZyxdzFvfBXn66PFb3aLWWvjSyduyiL2eASwBKU/TqhloVjUyRc3s0/Q1BAMN6Ls6sY+IhBbM2czux+he58HVsnVI2RlTapxLHDdfunM7CXo+3GRUVeZL3HawicFa388BT9wjPZO5xVJkyPhjxkKFuRyZi0q46w7aROQtXV4+KWI7/onGUul76acH/Rec8b9iHVkeerMWyF9Eoezbd+m+Kr7OpfzA0r7mZkpXWywci0x82zQtGl/nED0ePekkyTG8MRDzpAEAVJu21VBgNzcPVf3CJzhuK51Hjm7JpaBgf7EfL1wfmlp0mMpN6cxyXCaIOcls3JiKwUxxsw2/0vjP/zB3jXjCqS5FVJ8HUeMTtOsM+ztWXef0KAcX2RijlYHjbvBkDRbcyB4CFrBIChasNQYD6QnLyzr2r5xQMHycQ6kn9tg8If4ZJtEmLC4V66STFHefKHvLOF/puyLKWqdEIVSujdnxmcYiRa2TIpSuYJQMlHeePtiWtodCCxNJ3xNokWtUz7QMz0R8F04ol205tDT/OyCNs8jLwfDTpecLHY=; 4:zUJgHbUNr7oQmAUoLXFFwt5q0LfFBrmeELYMmQOJlNn1kMQ+2Vx9OdAMrSngSJ9kqhFR9FfzouSyLjoa88NGLGqIlXyMD6dURPtXP8Zd/DDP0XRaojIyzjNuButAIHCpPQVCsU03Av/bgGsWgMmXQTgdOCe5ge/N5uBd86dOdWn8iVaFh8LkHBUF8i8GgZJ/tRw4qqNckgajj618aegJ/sXI6rnbVY3LrBf11msAuM9KkM2NLRVUBcfPf0EEy+uV+lhFD3a6yUkXgnrEvyhPNg== X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-MS-Exchange-SenderADCheck: 1 X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(8211001083)(6040522)(2401047)(8121501046)(5005006)(3002001)(3231355)(944501410)(52105095)(10201501046)(93006095)(149066)(150057)(6041310)(20161123564045)(20161123558120)(20161123560045)(20161123562045)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(201708071742011)(7699051); SRVR:SN6PR07MB4910; BCL:0; PCL:0; RULEID:; SRVR:SN6PR07MB4910; X-Forefront-PRVS: 0816F1D86E X-Forefront-Antispam-Report: SFV:NSPM; SFS:(10009020)(376002)(39860400002)(346002)(136003)(396003)(366004)(199004)(189003)(51416003)(76176011)(11346002)(50226002)(25786009)(8936002)(48376002)(305945005)(186003)(16526019)(110136005)(6486002)(3846002)(446003)(52116002)(6116002)(81156014)(8676002)(97736004)(5660300001)(50466002)(4326008)(956004)(42882007)(2616005)(68736007)(478600001)(54906003)(7736002)(81166006)(6666003)(16586007)(107886003)(26005)(55236004)(66066001)(386003)(47776003)(6512007)(72206003)(44832011)(476003)(316002)(14444005)(36756003)(4744004)(105586002)(106356001)(486006)(6506007)(2906002)(53936002); DIR:OUT; SFP:1101; SCL:1; SRVR:SN6PR07MB4910; H:ajoseph83.caveonetworks.com.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; Received-SPF: None (protection.outlook.com: cavium.com does not designate permitted sender hosts) X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; SN6PR07MB4910; 23:td2wbdEXYlCv+5EIts/WTdlftqMwacBPQ0v0/E3N2?= =?us-ascii?Q?w7tdUiYYtok1iOvM+IJ2x5FkbGoscjVuZ2Ak37Lfu9G74/A6Rsil0sO7x58T?= =?us-ascii?Q?3oW0JoTAwdg3/2KmbSweAC02A98BCdj3LzwsSsdE9lNQ7ATYUhIxWfhpuexq?= =?us-ascii?Q?voZzbFAHMXgUK1mG+ok9d18+j4FztYm27Mt/0Jd4R/VuMizuOWlvqU+tnDsQ?= =?us-ascii?Q?lub5MXM/KO5NWt/MZYycKzRPB02wPmFZAX6WzA3QFqlRrCvRQxys8On4X7C0?= =?us-ascii?Q?7pO202S9L120TozH3XBG1Exx3UYo3pmbJMZTAyYn4CP7bQBN90yVJ2RuPa32?= =?us-ascii?Q?aAKZPlzS2LJC1A3oXFLursOj6xvsvCwP6t7uA8PxfG9PfABpHRFSDoHfSLzm?= =?us-ascii?Q?fJAv5g1jGh4iq8C/GMvA49ej/IOZFF2WCRZXpl+f0smgMnYazMoO8Kw4OvJ7?= =?us-ascii?Q?NTEA97Fyy8IKbtFycvCXi+y5Ts1CsHglq7N42V0X9KPYR3OmIgt27rkOWF4q?= =?us-ascii?Q?EVN57INai5QqozZ7TUNOophVDi4hzeuJP0nLF0ne4estTe40RsxpTiSroNK6?= =?us-ascii?Q?UNZsYm0wThZ+z80LPknK3qLAS3qIzX9S+a5UGfavLf6mcLTe6Ty06nV8nTfs?= =?us-ascii?Q?xLQaugyAXS60MUKiGT++b+aMpaSuS6YXEX0uQkkq7ZBVcf8jCLQk0Jbi60/g?= =?us-ascii?Q?T6OQIsWSeWeAIddzUjeYS0ARe+77Nw6uzpwjWawPfBkTTYQZCg1Uh9NWsQkN?= =?us-ascii?Q?/6j8A98bJh5tGAplK0UQhXrf2U8nrqrfGrxiNkx+GUAeh762OU7xI2ZE2Pmo?= =?us-ascii?Q?DABmRjuZz5mys623mfZyNZSFHyvVRewpT82zsbO/KJ9t3VuONGtkEiCagitm?= =?us-ascii?Q?AxH3YvepVMMQxDd7q76rW50acq8p68Boqjm7tFDrgKr36/wU6RrvpM4p6a3j?= =?us-ascii?Q?59+SqpLVlu/dF59Fow23j7O4sFLnMhJ1suEYzDgmSxi2ruQWpv5FSiaHu5pf?= =?us-ascii?Q?OnFjE1a9IwTfybn0Ox3jbM7xWMqu4jufbEYbU6WaLFShz5yn3xHAoHxXzWSQ?= =?us-ascii?Q?gUBDwo7nPt8piwh0cTGoFmPnCjXo/kVhpMR7cbxfeG+as7qLjlsGl5/15CnF?= =?us-ascii?Q?FtbHo8njfjo2YSBtlvlaiTz5N1gfQbrzWE3GxkfekNtl4OTZqZQR6xIblkrX?= =?us-ascii?Q?dmtav8oir9VL5XEOd0xs9YAb3wYW2dcPsOPXNTWcgJSls1E0VRnIklvyksXd?= =?us-ascii?Q?92yqSnZD/L192lRkbBkDOuxd8XWmndLyGHg0jHSEOFM+MRNU0jLBousMXthO?= =?us-ascii?Q?K2XHbpuWowfqPWHjxHRxbc=3D?= X-Microsoft-Antispam-Message-Info: pAC1pctTdXcMv1aFhVEX0F64W77vJnB8CqBoFVVxYtOONl8Was8OLJvHcjls/Ord/MKbnmM98ADhAWnjGysBDJj3uRuDn12T0UJdF7uWfO9OyzqhZiwyTJRq0C6sIAe33+2uRcYLHckiGzA/GkNKluaXz+v6QxvwrGedg2DkxZ8rT3H0ALnEy6pkBeivM++VVatAJCLSgg3EHPiCfpgCV5Wa+SKb42VzcsjWfKDHqX0mb72x/a4JA+zwmHoi40nOrBc/uAJD6jie8xOIEzN9hj3/bslV16z0FS1Uhtt3XBos6exIhigp9kC5kg81iB1YlSwfpv/7HiI4TE5hkC55NvFdnUQtXxu+gWQOm4aCYt0= X-Microsoft-Exchange-Diagnostics: 1; SN6PR07MB4910; 6:gRNOIw5hzYu5xKsJosZDVUFO7S7FN6H6C6KTxJzzWY/sbT/ct5Q58b7n8exVRbrJOwNkZzgQWB0mDBemkxjz4AC/PFt6AndceAn11AeEmSgbTluGyZXmcz7NfBv37pUikEFYr2rOZLqbD6ywijzH65kgOGlN36apP7/lLc1xVya3bq3jSA/MjPSDvam16p3mFiZtBwnamck5ktfCd5KHsyYArxLR6yXAyR0dKXrGU78hD72n+TG4RacbbdKEWRspmVcJZROTKnsBmF2/iEBNN8fUIV69iI4yNApxHMvZAtwH5VFENXnx8q67rIWse56idNyWstEUIQtUfJzuMTkbn8ViB94NUrE8Xj7M7wtmu9D4wn3H9KS4ml+cq5aSVK8J0q1Jpqt+/T7YT7DObe6tlVDYV7SvFPpWpoVZfqIl+uLAhVw3cAblvE3FFalLGyxI/jdksBWbL6X3w00Iek1sUA==; 5:LeOu5U5xwH0zRgUveXXSzW1w/w4tCElcnm9uDVie2lkB47HUWsd0yvwkVBvn2tD9DtxeyaVK9mKmTFJH3e+YGvfZdV2XcBXjeruUVh1UYwrZCJC9RQR3QmHSnm6u3VSNe8FLiTj1alLqdoe1CTNL475Lg3dR/ZUVNtD/b2GMApA=; 7:RyDJpE1WmWtZNN0GAOlOBSwHADD0w1Yu4jyShjIE35uOfZymHGoDMUqWeJnKwLK2KVFawGcUkWlFwkUBbpdf4+HAqcFJt9agMJp937Q6Byy3UNsnBFdyj4MkM4NrwSVu2za/EBwOuqarr6jEde8WKEj9hS8zH3RhTcrnx9QoGg1UDhDwYShMl/MMOSqVcpjMGhjEt3NMVtJRkgAAGp5JmFN3hq+eLAVrygz1xlLx0sJ/qjOsVbBJiU4JaRgYKWz5 SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: caviumnetworks.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Oct 2018 13:02:06.7161 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 27c49869-81d4-4298-63cc-08d62ac2c326 X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 711e4ccf-2e9b-4bcf-a551-4094005b6194 X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR07MB4910 Subject: [dpdk-dev] [PATCH v3 24/32] common/cpt: add support for kasumi X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 05 Oct 2018 13:02:12 -0000 From: Srisivasubramanian S Adding microcode interface for supporting kasumi. Signed-off-by: Ankur Dwivedi Signed-off-by: Anoob Joseph Signed-off-by: Murthy NSSR Signed-off-by: Nithin Dabilpuram Signed-off-by: Ragothaman Jayaraman Signed-off-by: Srisivasubramanian S Signed-off-by: Tejasree Kondoj --- drivers/common/cpt/cpt_ucode.h | 450 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 450 insertions(+) diff --git a/drivers/common/cpt/cpt_ucode.h b/drivers/common/cpt/cpt_ucode.h index 5d7743c..05cf95c 100644 --- a/drivers/common/cpt/cpt_ucode.h +++ b/drivers/common/cpt/cpt_ucode.h @@ -1816,6 +1816,450 @@ cpt_zuc_snow3g_dec_prep(uint32_t req_flags, return 0; } +static __rte_always_inline int +cpt_kasumi_enc_prep(uint32_t req_flags, + uint64_t d_offs, + uint64_t d_lens, + fc_params_t *params, + void *op, + void **prep_req) +{ + uint32_t size; + int32_t inputlen = 0, outputlen = 0; + struct cpt_ctx *cpt_ctx; + uint32_t mac_len = 0; + uint8_t i = 0; + struct cpt_request_info *req; + buf_ptr_t *buf_p; + uint32_t encr_offset, auth_offset; + uint32_t encr_data_len, auth_data_len; + int flags, m_size; + uint8_t *iv_s, *iv_d, iv_len = 8; + uint8_t dir = 0; + void *m_vaddr, *c_vaddr; + uint64_t m_dma, c_dma; + uint64_t *offset_vaddr, offset_dma; + vq_cmd_word0_t vq_cmd_w0; + vq_cmd_word3_t vq_cmd_w3; + opcode_info_t opcode; + uint8_t *in_buffer; + uint32_t g_size_bytes, s_size_bytes; + uint64_t dptr_dma, rptr_dma; + sg_comp_t *gather_comp; + sg_comp_t *scatter_comp; + + buf_p = ¶ms->meta_buf; + m_vaddr = buf_p->vaddr; + m_dma = buf_p->dma_addr; + m_size = buf_p->size; + + encr_offset = ENCR_OFFSET(d_offs) / 8; + auth_offset = AUTH_OFFSET(d_offs) / 8; + encr_data_len = ENCR_DLEN(d_lens); + auth_data_len = AUTH_DLEN(d_lens); + + cpt_ctx = params->ctx_buf.vaddr; + flags = cpt_ctx->zsk_flags; + mac_len = cpt_ctx->mac_len; + + if (flags == 0x0) + iv_s = params->iv_buf; + else + iv_s = params->auth_iv_buf; + + dir = iv_s[8] & 0x1; + + /* + * Save initial space that followed app data for completion code & + * alternate completion code to fall in same cache line as app data + */ + m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE; + m_dma += COMPLETION_CODE_SIZE; + size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) - + (uint8_t *)m_vaddr; + + c_vaddr = (uint8_t *)m_vaddr + size; + c_dma = m_dma + size; + size += sizeof(cpt_res_s_t); + + m_vaddr = (uint8_t *)m_vaddr + size; + m_dma += size; + m_size -= size; + + /* Reserve memory for cpt request info */ + req = m_vaddr; + + size = sizeof(struct cpt_request_info); + m_vaddr = (uint8_t *)m_vaddr + size; + m_dma += size; + m_size -= size; + + opcode.s.major = CPT_MAJOR_OP_KASUMI | CPT_DMA_MODE; + + /* indicates ECB/CBC, direction, ctx from cptr, iv from dptr */ + opcode.s.minor = ((1 << 6) | (cpt_ctx->k_ecb << 5) | + (dir << 4) | (0 << 3) | (flags & 0x7)); + + /* + * GP op header, lengths are expected in bits. + */ + vq_cmd_w0.u64 = 0; + vq_cmd_w0.s.param1 = rte_cpu_to_be_16(encr_data_len); + vq_cmd_w0.s.param2 = rte_cpu_to_be_16(auth_data_len); + vq_cmd_w0.s.opcode = rte_cpu_to_be_16(opcode.flags); + + /* consider iv len */ + if (flags == 0x0) { + encr_offset += iv_len; + auth_offset += iv_len; + } + + /* save space for offset ctrl and iv */ + offset_vaddr = m_vaddr; + offset_dma = m_dma; + + m_vaddr = (uint8_t *)m_vaddr + OFF_CTRL_LEN + iv_len; + m_dma += OFF_CTRL_LEN + iv_len; + m_size -= OFF_CTRL_LEN + iv_len; + + /* DPTR has SG list */ + in_buffer = m_vaddr; + dptr_dma = m_dma; + + ((uint16_t *)in_buffer)[0] = 0; + ((uint16_t *)in_buffer)[1] = 0; + + /* TODO Add error check if space will be sufficient */ + gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8); + + /* + * Input Gather List + */ + i = 0; + + /* Offset control word followed by iv */ + + if (flags == 0x0) { + inputlen = encr_offset + (RTE_ALIGN(encr_data_len, 8) / 8); + outputlen = inputlen; + /* iv offset is 0 */ + *offset_vaddr = rte_cpu_to_be_64((uint64_t)encr_offset << 16); + } else { + inputlen = auth_offset + (RTE_ALIGN(auth_data_len, 8) / 8); + outputlen = mac_len; + /* iv offset is 0 */ + *offset_vaddr = rte_cpu_to_be_64((uint64_t)auth_offset); + } + + i = fill_sg_comp(gather_comp, i, offset_dma, OFF_CTRL_LEN + iv_len); + + /* IV */ + iv_d = (uint8_t *)offset_vaddr + OFF_CTRL_LEN; + memcpy(iv_d, iv_s, iv_len); + + /* input data */ + size = inputlen - iv_len; + if (size) { + i = fill_sg_comp_from_iov(gather_comp, i, + params->src_iov, 0, + &size, NULL, 0); + + if (size) + return ERR_BAD_INPUT_ARG; + } + ((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i); + g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t); + + /* + * Output Scatter List + */ + + i = 0; + scatter_comp = (sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes); + + if (flags == 0x1) { + /* IV in SLIST only for F8 */ + iv_len = 0; + } + + /* IV */ + if (iv_len) { + i = fill_sg_comp(scatter_comp, i, + offset_dma + OFF_CTRL_LEN, + iv_len); + } + + /* Add output data */ + if (req_flags & VALID_MAC_BUF) { + size = outputlen - iv_len - mac_len; + if (size) { + i = fill_sg_comp_from_iov(scatter_comp, i, + params->dst_iov, 0, + &size, NULL, 0); + + if (size) + return ERR_BAD_INPUT_ARG; + } + + /* mac data */ + if (mac_len) { + i = fill_sg_comp_from_buf(scatter_comp, i, + ¶ms->mac_buf); + } + } else { + /* Output including mac */ + size = outputlen - iv_len; + if (size) { + i = fill_sg_comp_from_iov(scatter_comp, i, + params->dst_iov, 0, + &size, NULL, 0); + + if (size) + return ERR_BAD_INPUT_ARG; + } + } + ((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i); + s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t); + + size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE; + + /* This is DPTR len incase of SG mode */ + vq_cmd_w0.s.dlen = rte_cpu_to_be_16(size); + + m_vaddr = (uint8_t *)m_vaddr + size; + m_dma += size; + m_size -= size; + + /* cpt alternate completion address saved earlier */ + req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8); + *req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT); + rptr_dma = c_dma - 8; + + req->ist.ei1 = dptr_dma; + req->ist.ei2 = rptr_dma; + + /* First 16-bit swap then 64-bit swap */ + /* TODO: HACK: Reverse the vq_cmd and cpt_req bit field definitions + * to eliminate all the swapping + */ + vq_cmd_w0.u64 = rte_cpu_to_be_64(vq_cmd_w0.u64); + + /* vq command w3 */ + vq_cmd_w3.u64 = 0; + vq_cmd_w3.s.grp = 0; + vq_cmd_w3.s.cptr = params->ctx_buf.dma_addr + + offsetof(struct cpt_ctx, k_ctx); + + /* 16 byte aligned cpt res address */ + req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr); + *req->completion_addr = COMPLETION_CODE_INIT; + req->comp_baddr = c_dma; + + /* Fill microcode part of instruction */ + req->ist.ei0 = vq_cmd_w0.u64; + req->ist.ei3 = vq_cmd_w3.u64; + + req->op = op; + + *prep_req = req; + return 0; +} + +static __rte_always_inline int +cpt_kasumi_dec_prep(uint64_t d_offs, + uint64_t d_lens, + fc_params_t *params, + void *op, + void **prep_req) +{ + uint32_t size; + int32_t inputlen = 0, outputlen; + struct cpt_ctx *cpt_ctx; + uint8_t i = 0, iv_len = 8; + struct cpt_request_info *req; + buf_ptr_t *buf_p; + uint32_t encr_offset; + uint32_t encr_data_len; + int flags, m_size; + uint8_t dir = 0; + void *m_vaddr, *c_vaddr; + uint64_t m_dma, c_dma; + uint64_t *offset_vaddr, offset_dma; + vq_cmd_word0_t vq_cmd_w0; + vq_cmd_word3_t vq_cmd_w3; + opcode_info_t opcode; + uint8_t *in_buffer; + uint32_t g_size_bytes, s_size_bytes; + uint64_t dptr_dma, rptr_dma; + sg_comp_t *gather_comp; + sg_comp_t *scatter_comp; + + buf_p = ¶ms->meta_buf; + m_vaddr = buf_p->vaddr; + m_dma = buf_p->dma_addr; + m_size = buf_p->size; + + encr_offset = ENCR_OFFSET(d_offs) / 8; + encr_data_len = ENCR_DLEN(d_lens); + + cpt_ctx = params->ctx_buf.vaddr; + flags = cpt_ctx->zsk_flags; + /* + * Save initial space that followed app data for completion code & + * alternate completion code to fall in same cache line as app data + */ + m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE; + m_dma += COMPLETION_CODE_SIZE; + size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) - + (uint8_t *)m_vaddr; + + c_vaddr = (uint8_t *)m_vaddr + size; + c_dma = m_dma + size; + size += sizeof(cpt_res_s_t); + + m_vaddr = (uint8_t *)m_vaddr + size; + m_dma += size; + m_size -= size; + + /* Reserve memory for cpt request info */ + req = m_vaddr; + + size = sizeof(struct cpt_request_info); + m_vaddr = (uint8_t *)m_vaddr + size; + m_dma += size; + m_size -= size; + + opcode.s.major = CPT_MAJOR_OP_KASUMI | CPT_DMA_MODE; + + /* indicates ECB/CBC, direction, ctx from cptr, iv from dptr */ + opcode.s.minor = ((1 << 6) | (cpt_ctx->k_ecb << 5) | + (dir << 4) | (0 << 3) | (flags & 0x7)); + + /* + * GP op header, lengths are expected in bits. + */ + vq_cmd_w0.u64 = 0; + vq_cmd_w0.s.param1 = rte_cpu_to_be_16(encr_data_len); + vq_cmd_w0.s.opcode = rte_cpu_to_be_16(opcode.flags); + + /* consider iv len */ + encr_offset += iv_len; + + inputlen = iv_len + (RTE_ALIGN(encr_data_len, 8) / 8); + outputlen = inputlen; + + /* save space for offset ctrl & iv */ + offset_vaddr = m_vaddr; + offset_dma = m_dma; + + m_vaddr = (uint8_t *)m_vaddr + OFF_CTRL_LEN + iv_len; + m_dma += OFF_CTRL_LEN + iv_len; + m_size -= OFF_CTRL_LEN + iv_len; + + /* DPTR has SG list */ + in_buffer = m_vaddr; + dptr_dma = m_dma; + + ((uint16_t *)in_buffer)[0] = 0; + ((uint16_t *)in_buffer)[1] = 0; + + /* TODO Add error check if space will be sufficient */ + gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8); + + /* + * Input Gather List + */ + i = 0; + + /* Offset control word followed by iv */ + *offset_vaddr = rte_cpu_to_be_64((uint64_t)encr_offset << 16); + + i = fill_sg_comp(gather_comp, i, offset_dma, OFF_CTRL_LEN + iv_len); + + /* IV */ + memcpy((uint8_t *)offset_vaddr + OFF_CTRL_LEN, + params->iv_buf, iv_len); + + /* Add input data */ + size = inputlen - iv_len; + if (size) { + i = fill_sg_comp_from_iov(gather_comp, i, + params->src_iov, + 0, &size, NULL, 0); + if (size) + return ERR_BAD_INPUT_ARG; + } + ((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i); + g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t); + + /* + * Output Scatter List + */ + + i = 0; + scatter_comp = (sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes); + + /* IV */ + i = fill_sg_comp(scatter_comp, i, + offset_dma + OFF_CTRL_LEN, + iv_len); + + /* Add output data */ + size = outputlen - iv_len; + if (size) { + i = fill_sg_comp_from_iov(scatter_comp, i, + params->dst_iov, 0, + &size, NULL, 0); + if (size) + return ERR_BAD_INPUT_ARG; + } + ((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i); + s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t); + + size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE; + + /* This is DPTR len incase of SG mode */ + vq_cmd_w0.s.dlen = rte_cpu_to_be_16(size); + + m_vaddr = (uint8_t *)m_vaddr + size; + m_dma += size; + m_size -= size; + + /* cpt alternate completion address saved earlier */ + req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8); + *req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT); + rptr_dma = c_dma - 8; + + req->ist.ei1 = dptr_dma; + req->ist.ei2 = rptr_dma; + + /* First 16-bit swap then 64-bit swap */ + /* TODO: HACK: Reverse the vq_cmd and cpt_req bit field definitions + * to eliminate all the swapping + */ + vq_cmd_w0.u64 = rte_cpu_to_be_64(vq_cmd_w0.u64); + + /* vq command w3 */ + vq_cmd_w3.u64 = 0; + vq_cmd_w3.s.grp = 0; + vq_cmd_w3.s.cptr = params->ctx_buf.dma_addr + + offsetof(struct cpt_ctx, k_ctx); + + /* 16 byte aligned cpt res address */ + req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr); + *req->completion_addr = COMPLETION_CODE_INIT; + req->comp_baddr = c_dma; + + /* Fill microcode part of instruction */ + req->ist.ei0 = vq_cmd_w0.u64; + req->ist.ei3 = vq_cmd_w3.u64; + + req->op = op; + + *prep_req = req; + return 0; +} + static __rte_always_inline void * cpt_fc_dec_hmac_prep(uint32_t flags, uint64_t d_offs, @@ -1836,6 +2280,9 @@ cpt_fc_dec_hmac_prep(uint32_t flags, } else if (fc_type == ZUC_SNOW3G) { ret = cpt_zuc_snow3g_dec_prep(flags, d_offs, d_lens, fc_params, op, &prep_req); + } else if (fc_type == KASUMI) { + ret = cpt_kasumi_dec_prep(d_offs, d_lens, fc_params, op, + &prep_req); } else { /* * For AUTH_ONLY case, @@ -1869,6 +2316,9 @@ cpt_fc_enc_hmac_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens, } else if (fc_type == ZUC_SNOW3G) { ret = cpt_zuc_snow3g_enc_prep(flags, d_offs, d_lens, fc_params, op, &prep_req); + } else if (fc_type == KASUMI) { + ret = cpt_kasumi_enc_prep(flags, d_offs, d_lens, + fc_params, op, &prep_req); } else { ret = ERR_EIO; } -- 2.7.4