* [dpdk-dev] [PATCH] compress/qat: enable dynamic huffman encoding
@ 2018-07-20 17:46 Fiona Trahe
2018-10-05 16:18 ` [dpdk-dev] [PATCH v2] " Fiona Trahe
0 siblings, 1 reply; 17+ messages in thread
From: Fiona Trahe @ 2018-07-20 17:46 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
Enable dynamic huffman encoding in the QAT comp PMD.
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
---
config/common_base | 1 +
config/rte_config.h | 1 +
doc/guides/compressdevs/features/qat.ini | 1 +
doc/guides/compressdevs/qat_comp.rst | 8 +--
drivers/common/qat/qat_device.c | 3 +
drivers/common/qat/qat_device.h | 6 ++
drivers/compress/qat/qat_comp.c | 39 +++++++----
drivers/compress/qat/qat_comp.h | 13 ++++
drivers/compress/qat/qat_comp_pmd.c | 109 ++++++++++++++++++++++++++++++-
9 files changed, 163 insertions(+), 18 deletions(-)
diff --git a/config/common_base b/config/common_base
index 6d82b91..2f88e34 100644
--- a/config/common_base
+++ b/config/common_base
@@ -500,6 +500,7 @@ CONFIG_RTE_LIBRTE_PMD_QAT_SYM=n
#
CONFIG_RTE_PMD_QAT_MAX_PCI_DEVICES=48
CONFIG_RTE_PMD_QAT_COMP_SGL_MAX_SEGMENTS=16
+CONFIG_RTE_PMD_QAT_COMP_IM_BUFFER_SIZE=65536
#
# Compile PMD for virtio crypto devices
diff --git a/config/rte_config.h b/config/rte_config.h
index a8e4797..c93d508 100644
--- a/config/rte_config.h
+++ b/config/rte_config.h
@@ -90,6 +90,7 @@
/* Max. number of QuickAssist devices which can be attached */
#define RTE_PMD_QAT_MAX_PCI_DEVICES 48
#define RTE_PMD_QAT_COMP_SGL_MAX_SEGMENTS 16
+#define RTE_PMD_QAT_COMP_IM_BUFFER_SIZE 65536
/* virtio crypto defines */
#define RTE_MAX_VIRTIO_CRYPTO 32
diff --git a/doc/guides/compressdevs/features/qat.ini b/doc/guides/compressdevs/features/qat.ini
index 5cd4524..6b1e7f9 100644
--- a/doc/guides/compressdevs/features/qat.ini
+++ b/doc/guides/compressdevs/features/qat.ini
@@ -13,3 +13,4 @@ Adler32 = Y
Crc32 = Y
Adler32&Crc32 = Y
Fixed = Y
+Dynamic = Y
diff --git a/doc/guides/compressdevs/qat_comp.rst b/doc/guides/compressdevs/qat_comp.rst
index 8b1270b..17e2bb4 100644
--- a/doc/guides/compressdevs/qat_comp.rst
+++ b/doc/guides/compressdevs/qat_comp.rst
@@ -18,11 +18,7 @@ QAT compression PMD has support for:
Compression/Decompression algorithm:
- * DEFLATE
-
-Huffman code type:
-
- * FIXED
+ * DEFLATE - using Fixed and Dynamic Huffman encoding
Window size support:
@@ -37,7 +33,7 @@ Limitations
* Compressdev level 0, no compression, is not supported.
-* Dynamic Huffman encoding is not yet supported.
+* Dynamic Huffman encoding is supported up to a maximum payload size of 64Kb.
Installation
------------
diff --git a/drivers/common/qat/qat_device.c b/drivers/common/qat/qat_device.c
index f32d723..cbb5d79 100644
--- a/drivers/common/qat/qat_device.c
+++ b/drivers/common/qat/qat_device.c
@@ -7,6 +7,7 @@
#include "qat_device.h"
#include "adf_transport_access_macros.h"
#include "qat_sym_pmd.h"
+#include "qat_comp_pmd.h"
/* Hardware device information per generation */
__extension__
@@ -14,11 +15,13 @@ struct qat_gen_hw_data qat_gen_config[] = {
[QAT_GEN1] = {
.dev_gen = QAT_GEN1,
.qp_hw_data = qat_gen1_qps,
+ .comp_num_im_bufs_required = QAT_NUM_INTERM_BUFS_GEN1
},
[QAT_GEN2] = {
.dev_gen = QAT_GEN2,
.qp_hw_data = qat_gen1_qps,
/* gen2 has same ring layout as gen1 */
+ .comp_num_im_bufs_required = QAT_NUM_INTERM_BUFS_GEN2
},
};
diff --git a/drivers/common/qat/qat_device.h b/drivers/common/qat/qat_device.h
index 9599fc5..41f874b 100644
--- a/drivers/common/qat/qat_device.h
+++ b/drivers/common/qat/qat_device.h
@@ -16,6 +16,11 @@
#define QAT_DEV_NAME_MAX_LEN 64
+enum qat_comp_num_im_buffers {
+ QAT_NUM_INTERM_BUFS_GEN1 = 12,
+ QAT_NUM_INTERM_BUFS_GEN2 = 20
+};
+
/*
* This struct holds all the data about a QAT pci device
* including data about all services it supports.
@@ -67,6 +72,7 @@ struct qat_pci_device {
struct qat_gen_hw_data {
enum qat_device_gen dev_gen;
const struct qat_qp_hw_data (*qp_hw_data)[ADF_MAX_QPS_ON_ANY_SERVICE];
+ enum qat_comp_num_im_buffers comp_num_im_bufs_required;
};
extern struct qat_gen_hw_data qat_gen_config[];
diff --git a/drivers/compress/qat/qat_comp.c b/drivers/compress/qat/qat_comp.c
index cbf7614..df3180b 100644
--- a/drivers/compress/qat/qat_comp.c
+++ b/drivers/compress/qat/qat_comp.c
@@ -192,7 +192,7 @@ static void qat_comp_create_req_hdr(struct icp_qat_fw_comn_req_hdr *header,
}
static int qat_comp_create_templates(struct qat_comp_xform *qat_xform,
- const struct rte_memzone *interm_buff_mz __rte_unused,
+ const struct rte_memzone *interm_buff_mz,
const struct rte_comp_xform *xform)
{
struct icp_qat_fw_comp_req *comp_req;
@@ -280,10 +280,20 @@ static int qat_comp_create_templates(struct qat_comp_xform *qat_xform,
ICP_QAT_FW_COMN_CURR_ID_SET(&comp_req->comp_cd_ctrl,
ICP_QAT_FW_SLICE_COMP);
} else if (qat_xform->qat_comp_request_type ==
- QAT_COMP_REQUEST_DYNAMIC_COMP_STATELESS) {
+ QAT_COMP_REQUEST_DYNAMIC_COMP_STATELESS) {
- QAT_LOG(ERR, "Dynamic huffman encoding not supported");
- return -EINVAL;
+ ICP_QAT_FW_COMN_NEXT_ID_SET(&comp_req->comp_cd_ctrl,
+ ICP_QAT_FW_SLICE_XLAT);
+ ICP_QAT_FW_COMN_CURR_ID_SET(&comp_req->comp_cd_ctrl,
+ ICP_QAT_FW_SLICE_COMP);
+
+ ICP_QAT_FW_COMN_NEXT_ID_SET(&comp_req->u2.xlt_cd_ctrl,
+ ICP_QAT_FW_SLICE_DRAM_WR);
+ ICP_QAT_FW_COMN_CURR_ID_SET(&comp_req->u2.xlt_cd_ctrl,
+ ICP_QAT_FW_SLICE_XLAT);
+
+ comp_req->u1.xlt_pars.inter_buff_ptr =
+ interm_buff_mz->phys_addr;
}
#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
@@ -334,20 +344,27 @@ qat_comp_private_xform_create(struct rte_compressdev *dev,
(struct qat_comp_xform *)*private_xform;
if (xform->type == RTE_COMP_COMPRESS) {
- if (xform->compress.deflate.huffman ==
- RTE_COMP_HUFFMAN_DYNAMIC) {
- QAT_LOG(ERR,
- "QAT device doesn't support dynamic compression");
- return -ENOTSUP;
- }
if (xform->compress.deflate.huffman == RTE_COMP_HUFFMAN_FIXED ||
((xform->compress.deflate.huffman == RTE_COMP_HUFFMAN_DEFAULT)
- && qat->interm_buff_mz == NULL))
+ && qat->interm_buff_mz == NULL))
qat_xform->qat_comp_request_type =
QAT_COMP_REQUEST_FIXED_COMP_STATELESS;
+ else if ((xform->compress.deflate.huffman ==
+ RTE_COMP_HUFFMAN_DYNAMIC ||
+ xform->compress.deflate.huffman ==
+ RTE_COMP_HUFFMAN_DEFAULT) &&
+ qat->interm_buff_mz != NULL)
+
+ qat_xform->qat_comp_request_type =
+ QAT_COMP_REQUEST_DYNAMIC_COMP_STATELESS;
+ else {
+ QAT_LOG(ERR,
+ "IM buffers needed for dynamic deflate. Set size in config file");
+ return -EINVAL;
+ }
} else {
qat_xform->qat_comp_request_type = QAT_COMP_REQUEST_DECOMPRESS;
diff --git a/drivers/compress/qat/qat_comp.h b/drivers/compress/qat/qat_comp.h
index 8d315ef..99a4462 100644
--- a/drivers/compress/qat/qat_comp.h
+++ b/drivers/compress/qat/qat_comp.h
@@ -15,6 +15,10 @@
#include "icp_qat_fw_comp.h"
#include "icp_qat_fw_la.h"
+#define QAT_64_BYTE_ALIGN_MASK (~0x3f)
+#define QAT_64_BYTE_ALIGN (64)
+#define QAT_NUM_BUFS_IN_IM_SGL 1
+
#define ERR_CODE_QAT_COMP_WRONG_FW -99
enum qat_comp_request_type {
@@ -24,6 +28,15 @@ enum qat_comp_request_type {
REQ_COMP_END
};
+struct array_of_ptrs {
+ phys_addr_t pointer[0];
+};
+
+struct qat_inter_sgl {
+ qat_sgl_hdr;
+ struct qat_flat_buf buffers[QAT_NUM_BUFS_IN_IM_SGL];
+} __rte_packed __rte_cache_aligned;
+
struct qat_comp_sgl {
qat_sgl_hdr;
struct qat_flat_buf buffers[RTE_PMD_QAT_COMP_SGL_MAX_SEGMENTS];
diff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c
index b89975f..76ae1f0 100644
--- a/drivers/compress/qat/qat_comp_pmd.c
+++ b/drivers/compress/qat/qat_comp_pmd.c
@@ -14,6 +14,7 @@ static const struct rte_compressdev_capabilities qat_comp_gen_capabilities[] = {
RTE_COMP_FF_CRC32_ADLER32_CHECKSUM |
RTE_COMP_FF_SHAREABLE_PRIV_XFORM |
RTE_COMP_FF_HUFFMAN_FIXED |
+ RTE_COMP_FF_HUFFMAN_DYNAMIC |
RTE_COMP_FF_OOP_SGL_IN_SGL_OUT |
RTE_COMP_FF_OOP_SGL_IN_LB_OUT |
RTE_COMP_FF_OOP_LB_IN_SGL_OUT,
@@ -112,7 +113,7 @@ qat_comp_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,
/* store a link to the qp in the qat_pci_device */
qat_private->qat_dev->qps_in_use[QAT_SERVICE_COMPRESSION][qp_id]
- = *qp_addr;
+ = *qp_addr;
qp = (struct qat_qp *)*qp_addr;
@@ -135,6 +136,91 @@ qat_comp_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,
return ret;
}
+
+static const struct rte_memzone *
+qat_comp_setup_inter_buffers(struct qat_comp_dev_private *comp_dev,
+ uint32_t buff_size)
+{
+ char inter_buff_mz_name[RTE_MEMZONE_NAMESIZE];
+ const struct rte_memzone *memzone;
+ uint8_t *mz_start = NULL;
+ phys_addr_t mz_start_phys = 0;
+ struct array_of_ptrs *array_of_pointers;
+ int size_of_ptr_array;
+ uint32_t full_size;
+ uint32_t offset_of_sgls, offset_of_flat_buffs = 0;
+ int i;
+ int num_im_sgls = qat_gen_config[
+ comp_dev->qat_dev->qat_dev_gen].comp_num_im_bufs_required;
+
+ QAT_LOG(DEBUG, "QAT COMP device %s needs %d sgls",
+ comp_dev->qat_dev->name, num_im_sgls);
+ snprintf(inter_buff_mz_name, RTE_MEMZONE_NAMESIZE,
+ "%s_inter_buff", comp_dev->qat_dev->name);
+ memzone = rte_memzone_lookup(inter_buff_mz_name);
+ if (memzone != NULL) {
+ QAT_LOG(DEBUG, "QAT COMP im buffer memzone created already");
+ return memzone;
+ }
+
+ /* Create a memzone to hold intermediate buffers and associated
+ * meta-data needed by the firmware. The memzone contains:
+ * - a list of num_im_sgls physical pointers to sgls
+ * - the num_im_sgl sgl structures, each pointing to 2 flat buffers
+ * - the flat buffers: num_im_sgl * 2
+ * where num_im_sgls depends on the hardware generation of the device
+ */
+
+ size_of_ptr_array = num_im_sgls * sizeof(phys_addr_t);
+ offset_of_sgls = (size_of_ptr_array + (~QAT_64_BYTE_ALIGN_MASK))
+ & QAT_64_BYTE_ALIGN_MASK;
+ offset_of_flat_buffs =
+ offset_of_sgls + num_im_sgls * sizeof(struct qat_inter_sgl);
+ full_size = offset_of_flat_buffs +
+ num_im_sgls * buff_size * QAT_NUM_BUFS_IN_IM_SGL;
+
+ memzone = rte_memzone_reserve_aligned(inter_buff_mz_name, full_size,
+ comp_dev->compressdev->data->socket_id,
+ RTE_MEMZONE_2MB, QAT_64_BYTE_ALIGN);
+ if (memzone == NULL) {
+ QAT_LOG(ERR, "Can't allocate intermediate buffers"
+ " for device %s", comp_dev->qat_dev->name);
+ return NULL;
+ }
+
+ mz_start = (uint8_t *)memzone->addr;
+ mz_start_phys = memzone->phys_addr;
+ QAT_LOG(DEBUG, "Memzone %s: addr = %p, phys = %lx, size required %d,"
+ "size created %ld",
+ inter_buff_mz_name, mz_start, mz_start_phys,
+ full_size, memzone->len);
+
+ array_of_pointers = (struct array_of_ptrs *)mz_start;
+ for (i = 0; i < num_im_sgls; i++) {
+ uint32_t curr_sgl_offset =
+ offset_of_sgls + i * sizeof(struct qat_inter_sgl);
+ struct qat_inter_sgl *sgl =
+ (struct qat_inter_sgl *)(mz_start + curr_sgl_offset);
+ array_of_pointers->pointer[i] = mz_start_phys + curr_sgl_offset;
+
+ sgl->num_bufs = QAT_NUM_BUFS_IN_IM_SGL;
+ sgl->num_mapped_bufs = 0;
+ sgl->resrvd = 0;
+ sgl->buffers[0].addr = mz_start_phys + offset_of_flat_buffs +
+ i * buff_size * QAT_NUM_BUFS_IN_IM_SGL;
+ sgl->buffers[0].len = buff_size;
+ sgl->buffers[0].resrvd = 0;
+
+
+ QAT_LOG(DEBUG, " : array_of_pointers->pointer[i]"
+ "= %lx", array_of_pointers->pointer[i]);
+ QAT_LOG(DEBUG, " : sgl[%i] = %p", i, sgl);
+ QAT_LOG(DEBUG, " : sgl->buffers[0].addr = %lx, len=%d",
+ sgl->buffers[0].addr, sgl->buffers[0].len);
+ }
+ return memzone;
+}
+
static struct rte_mempool *
qat_comp_create_xform_pool(struct qat_comp_dev_private *comp_dev,
uint32_t num_elements)
@@ -176,6 +262,12 @@ qat_comp_create_xform_pool(struct qat_comp_dev_private *comp_dev,
static void
_qat_comp_dev_config_clear(struct qat_comp_dev_private *comp_dev)
{
+ /* Free intermediate buffers */
+ if (comp_dev->interm_buff_mz) {
+ rte_memzone_free(comp_dev->interm_buff_mz);
+ comp_dev->interm_buff_mz = NULL;
+ }
+
/* Free private_xform pool */
if (comp_dev->xformpool) {
/* Free internal mempool for private xforms */
@@ -197,6 +289,21 @@ qat_comp_dev_config(struct rte_compressdev *dev,
return -EINVAL;
}
+ if (RTE_PMD_QAT_COMP_IM_BUFFER_SIZE == 0) {
+ QAT_LOG(WARNING,
+ "RTE_PMD_QAT_COMP_IM_BUFFER_SIZE = 0 in config file, so"
+ " QAT device can't be used for Dynamic Deflate. "
+ "Did you really intend to do this?");
+ } else {
+ comp_dev->interm_buff_mz =
+ qat_comp_setup_inter_buffers(comp_dev,
+ RTE_PMD_QAT_COMP_IM_BUFFER_SIZE);
+ if (comp_dev->interm_buff_mz == NULL) {
+ ret = -ENOMEM;
+ goto error_out;
+ }
+ }
+
comp_dev->xformpool = qat_comp_create_xform_pool(comp_dev,
config->max_nb_priv_xforms);
if (comp_dev->xformpool == NULL) {
--
2.7.4
^ permalink raw reply [flat|nested] 17+ messages in thread
* [dpdk-dev] [PATCH v2] compress/qat: enable dynamic huffman encoding
2018-07-20 17:46 [dpdk-dev] [PATCH] compress/qat: enable dynamic huffman encoding Fiona Trahe
@ 2018-10-05 16:18 ` Fiona Trahe
2018-10-09 11:01 ` Akhil Goyal
2018-10-11 17:03 ` [dpdk-dev] [PATCH v3] " Fiona Trahe
0 siblings, 2 replies; 17+ messages in thread
From: Fiona Trahe @ 2018-10-05 16:18 UTC (permalink / raw)
To: dev; +Cc: akhil.goyal, tomaszx.jozwiak, Fiona Trahe
Enable dynamic huffman encoding in the QAT comp PMD.
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
---
v2 changes:
- allocate 2 buffers per intermediate buffer sgl
- Compile out trace for debugging intermediate buffers
Depends on:
https://patches.dpdk.org/patch/45794/
config/common_base | 1 +
config/rte_config.h | 1 +
doc/guides/compressdevs/features/qat.ini | 1 +
doc/guides/compressdevs/qat_comp.rst | 7 +-
drivers/common/qat/qat_device.c | 4 +
drivers/common/qat/qat_device.h | 7 ++
drivers/compress/qat/qat_comp.c | 39 +++++++---
drivers/compress/qat/qat_comp.h | 13 ++++
drivers/compress/qat/qat_comp_pmd.c | 123 ++++++++++++++++++++++++++++++-
9 files changed, 179 insertions(+), 17 deletions(-)
diff --git a/config/common_base b/config/common_base
index 43c7e9a..d292a61 100644
--- a/config/common_base
+++ b/config/common_base
@@ -500,6 +500,7 @@ CONFIG_RTE_LIBRTE_PMD_QAT_SYM=n
#
CONFIG_RTE_PMD_QAT_MAX_PCI_DEVICES=48
CONFIG_RTE_PMD_QAT_COMP_SGL_MAX_SEGMENTS=16
+CONFIG_RTE_PMD_QAT_COMP_IM_BUFFER_SIZE=65536
#
# Compile PMD for virtio crypto devices
diff --git a/config/rte_config.h b/config/rte_config.h
index 20c58df..4e501b3 100644
--- a/config/rte_config.h
+++ b/config/rte_config.h
@@ -94,6 +94,7 @@
/* Max. number of QuickAssist devices which can be attached */
#define RTE_PMD_QAT_MAX_PCI_DEVICES 48
#define RTE_PMD_QAT_COMP_SGL_MAX_SEGMENTS 16
+#define RTE_PMD_QAT_COMP_IM_BUFFER_SIZE 65536
/* virtio crypto defines */
#define RTE_MAX_VIRTIO_CRYPTO 32
diff --git a/doc/guides/compressdevs/features/qat.ini b/doc/guides/compressdevs/features/qat.ini
index 5cd4524..6b1e7f9 100644
--- a/doc/guides/compressdevs/features/qat.ini
+++ b/doc/guides/compressdevs/features/qat.ini
@@ -13,3 +13,4 @@ Adler32 = Y
Crc32 = Y
Adler32&Crc32 = Y
Fixed = Y
+Dynamic = Y
diff --git a/doc/guides/compressdevs/qat_comp.rst b/doc/guides/compressdevs/qat_comp.rst
index 7bffbe6..aee3b99 100644
--- a/doc/guides/compressdevs/qat_comp.rst
+++ b/doc/guides/compressdevs/qat_comp.rst
@@ -18,11 +18,7 @@ QAT compression PMD has support for:
Compression/Decompression algorithm:
- * DEFLATE
-
-Huffman code type:
-
- * FIXED
+ * DEFLATE - using Fixed and Dynamic Huffman encoding
Window size support:
@@ -36,7 +32,6 @@ Limitations
-----------
* Compressdev level 0, no compression, is not supported.
-* Dynamic Huffman encoding is not yet supported.
* Queue pairs are not thread-safe (that is, within a single queue pair, RX and TX from different lcores is not supported).
* No BSD support as BSD QAT kernel driver not available.
diff --git a/drivers/common/qat/qat_device.c b/drivers/common/qat/qat_device.c
index b158fb9..b2db8b0 100644
--- a/drivers/common/qat/qat_device.c
+++ b/drivers/common/qat/qat_device.c
@@ -7,6 +7,7 @@
#include "qat_device.h"
#include "adf_transport_access_macros.h"
#include "qat_sym_pmd.h"
+#include "qat_comp_pmd.h"
/* Hardware device information per generation */
__extension__
@@ -14,15 +15,18 @@ struct qat_gen_hw_data qat_gen_config[] = {
[QAT_GEN1] = {
.dev_gen = QAT_GEN1,
.qp_hw_data = qat_gen1_qps,
+ .comp_num_im_bufs_required = QAT_NUM_INTERM_BUFS_GEN1
},
[QAT_GEN2] = {
.dev_gen = QAT_GEN2,
.qp_hw_data = qat_gen1_qps,
/* gen2 has same ring layout as gen1 */
+ .comp_num_im_bufs_required = QAT_NUM_INTERM_BUFS_GEN2
},
[QAT_GEN3] = {
.dev_gen = QAT_GEN3,
.qp_hw_data = qat_gen3_qps,
+ .comp_num_im_bufs_required = QAT_NUM_INTERM_BUFS_GEN3
},
};
diff --git a/drivers/common/qat/qat_device.h b/drivers/common/qat/qat_device.h
index 3a71cd4..eb81c78 100644
--- a/drivers/common/qat/qat_device.h
+++ b/drivers/common/qat/qat_device.h
@@ -16,6 +16,12 @@
#define QAT_DEV_NAME_MAX_LEN 64
+enum qat_comp_num_im_buffers {
+ QAT_NUM_INTERM_BUFS_GEN1 = 12,
+ QAT_NUM_INTERM_BUFS_GEN2 = 20,
+ QAT_NUM_INTERM_BUFS_GEN3 = 20
+};
+
/*
* This struct holds all the data about a QAT pci device
* including data about all services it supports.
@@ -72,6 +78,7 @@ struct qat_pci_device {
struct qat_gen_hw_data {
enum qat_device_gen dev_gen;
const struct qat_qp_hw_data (*qp_hw_data)[ADF_MAX_QPS_ON_ANY_SERVICE];
+ enum qat_comp_num_im_buffers comp_num_im_bufs_required;
};
extern struct qat_gen_hw_data qat_gen_config[];
diff --git a/drivers/compress/qat/qat_comp.c b/drivers/compress/qat/qat_comp.c
index b9336f3..d70c594 100644
--- a/drivers/compress/qat/qat_comp.c
+++ b/drivers/compress/qat/qat_comp.c
@@ -192,7 +192,7 @@ static void qat_comp_create_req_hdr(struct icp_qat_fw_comn_req_hdr *header,
}
static int qat_comp_create_templates(struct qat_comp_xform *qat_xform,
- const struct rte_memzone *interm_buff_mz __rte_unused,
+ const struct rte_memzone *interm_buff_mz,
const struct rte_comp_xform *xform)
{
struct icp_qat_fw_comp_req *comp_req;
@@ -280,10 +280,20 @@ static int qat_comp_create_templates(struct qat_comp_xform *qat_xform,
ICP_QAT_FW_COMN_CURR_ID_SET(&comp_req->comp_cd_ctrl,
ICP_QAT_FW_SLICE_COMP);
} else if (qat_xform->qat_comp_request_type ==
- QAT_COMP_REQUEST_DYNAMIC_COMP_STATELESS) {
+ QAT_COMP_REQUEST_DYNAMIC_COMP_STATELESS) {
- QAT_LOG(ERR, "Dynamic huffman encoding not supported");
- return -EINVAL;
+ ICP_QAT_FW_COMN_NEXT_ID_SET(&comp_req->comp_cd_ctrl,
+ ICP_QAT_FW_SLICE_XLAT);
+ ICP_QAT_FW_COMN_CURR_ID_SET(&comp_req->comp_cd_ctrl,
+ ICP_QAT_FW_SLICE_COMP);
+
+ ICP_QAT_FW_COMN_NEXT_ID_SET(&comp_req->u2.xlt_cd_ctrl,
+ ICP_QAT_FW_SLICE_DRAM_WR);
+ ICP_QAT_FW_COMN_CURR_ID_SET(&comp_req->u2.xlt_cd_ctrl,
+ ICP_QAT_FW_SLICE_XLAT);
+
+ comp_req->u1.xlt_pars.inter_buff_ptr =
+ interm_buff_mz->phys_addr;
}
#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
@@ -334,12 +344,6 @@ qat_comp_private_xform_create(struct rte_compressdev *dev,
(struct qat_comp_xform *)*private_xform;
if (xform->type == RTE_COMP_COMPRESS) {
- if (xform->compress.deflate.huffman ==
- RTE_COMP_HUFFMAN_DYNAMIC) {
- QAT_LOG(ERR,
- "QAT device doesn't support dynamic compression");
- return -ENOTSUP;
- }
if (xform->compress.deflate.huffman == RTE_COMP_HUFFMAN_FIXED ||
((xform->compress.deflate.huffman == RTE_COMP_HUFFMAN_DEFAULT)
@@ -347,6 +351,21 @@ qat_comp_private_xform_create(struct rte_compressdev *dev,
qat_xform->qat_comp_request_type =
QAT_COMP_REQUEST_FIXED_COMP_STATELESS;
+ else if ((xform->compress.deflate.huffman ==
+ RTE_COMP_HUFFMAN_DYNAMIC ||
+ xform->compress.deflate.huffman ==
+ RTE_COMP_HUFFMAN_DEFAULT) &&
+ qat->interm_buff_mz != NULL)
+
+ qat_xform->qat_comp_request_type =
+ QAT_COMP_REQUEST_DYNAMIC_COMP_STATELESS;
+
+ else {
+ QAT_LOG(ERR,
+ "IM buffers needed for dynamic deflate. Set size in config file");
+ return -EINVAL;
+ }
+
qat_xform->checksum_type = xform->compress.chksum;
} else {
diff --git a/drivers/compress/qat/qat_comp.h b/drivers/compress/qat/qat_comp.h
index 8d315ef..24d0d9c 100644
--- a/drivers/compress/qat/qat_comp.h
+++ b/drivers/compress/qat/qat_comp.h
@@ -15,6 +15,10 @@
#include "icp_qat_fw_comp.h"
#include "icp_qat_fw_la.h"
+#define QAT_64_BYTE_ALIGN_MASK (~0x3f)
+#define QAT_64_BYTE_ALIGN (64)
+#define QAT_NUM_BUFS_IN_IM_SGL 2
+
#define ERR_CODE_QAT_COMP_WRONG_FW -99
enum qat_comp_request_type {
@@ -24,6 +28,15 @@ enum qat_comp_request_type {
REQ_COMP_END
};
+struct array_of_ptrs {
+ phys_addr_t pointer[0];
+};
+
+struct qat_inter_sgl {
+ qat_sgl_hdr;
+ struct qat_flat_buf buffers[QAT_NUM_BUFS_IN_IM_SGL];
+} __rte_packed __rte_cache_aligned;
+
struct qat_comp_sgl {
qat_sgl_hdr;
struct qat_flat_buf buffers[RTE_PMD_QAT_COMP_SGL_MAX_SEGMENTS];
diff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c
index 6510cca..05ffe79 100644
--- a/drivers/compress/qat/qat_comp_pmd.c
+++ b/drivers/compress/qat/qat_comp_pmd.c
@@ -14,6 +14,7 @@ static const struct rte_compressdev_capabilities qat_comp_gen_capabilities[] = {
RTE_COMP_FF_CRC32_ADLER32_CHECKSUM |
RTE_COMP_FF_SHAREABLE_PRIV_XFORM |
RTE_COMP_FF_HUFFMAN_FIXED |
+ RTE_COMP_FF_HUFFMAN_DYNAMIC |
RTE_COMP_FF_OOP_SGL_IN_SGL_OUT |
RTE_COMP_FF_OOP_SGL_IN_LB_OUT |
RTE_COMP_FF_OOP_LB_IN_SGL_OUT,
@@ -112,7 +113,7 @@ qat_comp_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,
/* store a link to the qp in the qat_pci_device */
qat_private->qat_dev->qps_in_use[QAT_SERVICE_COMPRESSION][qp_id]
- = *qp_addr;
+ = *qp_addr;
qp = (struct qat_qp *)*qp_addr;
@@ -135,6 +136,101 @@ qat_comp_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,
return ret;
}
+
+static const struct rte_memzone *
+qat_comp_setup_inter_buffers(struct qat_comp_dev_private *comp_dev,
+ uint32_t buff_size)
+{
+ char inter_buff_mz_name[RTE_MEMZONE_NAMESIZE];
+ const struct rte_memzone *memzone;
+ uint8_t *mz_start = NULL;
+ phys_addr_t mz_start_phys = 0;
+ struct array_of_ptrs *array_of_pointers;
+ int size_of_ptr_array;
+ uint32_t full_size;
+ uint32_t offset_of_sgls, offset_of_flat_buffs = 0;
+ int i;
+ int num_im_sgls = qat_gen_config[
+ comp_dev->qat_dev->qat_dev_gen].comp_num_im_bufs_required;
+
+ QAT_LOG(DEBUG, "QAT COMP device %s needs %d sgls",
+ comp_dev->qat_dev->name, num_im_sgls);
+ snprintf(inter_buff_mz_name, RTE_MEMZONE_NAMESIZE,
+ "%s_inter_buff", comp_dev->qat_dev->name);
+ memzone = rte_memzone_lookup(inter_buff_mz_name);
+ if (memzone != NULL) {
+ QAT_LOG(DEBUG, "QAT COMP im buffer memzone created already");
+ return memzone;
+ }
+
+ /* Create a memzone to hold intermediate buffers and associated
+ * meta-data needed by the firmware. The memzone contains:
+ * - a list of num_im_sgls physical pointers to sgls
+ * - the num_im_sgl sgl structures, each pointing to 2 flat buffers
+ * - the flat buffers: num_im_sgl * 2
+ * where num_im_sgls depends on the hardware generation of the device
+ */
+
+ size_of_ptr_array = num_im_sgls * sizeof(phys_addr_t);
+ offset_of_sgls = (size_of_ptr_array + (~QAT_64_BYTE_ALIGN_MASK))
+ & QAT_64_BYTE_ALIGN_MASK;
+ offset_of_flat_buffs =
+ offset_of_sgls + num_im_sgls * sizeof(struct qat_inter_sgl);
+ full_size = offset_of_flat_buffs +
+ num_im_sgls * buff_size * QAT_NUM_BUFS_IN_IM_SGL;
+
+ memzone = rte_memzone_reserve_aligned(inter_buff_mz_name, full_size,
+ comp_dev->compressdev->data->socket_id,
+ RTE_MEMZONE_2MB, QAT_64_BYTE_ALIGN);
+ if (memzone == NULL) {
+ QAT_LOG(ERR, "Can't allocate intermediate buffers"
+ " for device %s", comp_dev->qat_dev->name);
+ return NULL;
+ }
+
+ mz_start = (uint8_t *)memzone->addr;
+ mz_start_phys = memzone->phys_addr;
+ QAT_LOG(DEBUG, "Memzone %s: addr = %p, phys = %lx, size required %d,"
+ "size created %ld",
+ inter_buff_mz_name, mz_start, mz_start_phys,
+ full_size, memzone->len);
+
+ array_of_pointers = (struct array_of_ptrs *)mz_start;
+ for (i = 0; i < num_im_sgls; i++) {
+ uint32_t curr_sgl_offset =
+ offset_of_sgls + i * sizeof(struct qat_inter_sgl);
+ struct qat_inter_sgl *sgl =
+ (struct qat_inter_sgl *)(mz_start + curr_sgl_offset);
+ array_of_pointers->pointer[i] = mz_start_phys + curr_sgl_offset;
+
+ sgl->num_bufs = QAT_NUM_BUFS_IN_IM_SGL;
+ sgl->num_mapped_bufs = 0;
+ sgl->resrvd = 0;
+ sgl->buffers[0].addr = mz_start_phys + offset_of_flat_buffs +
+ ((i * QAT_NUM_BUFS_IN_IM_SGL) * buff_size);
+ sgl->buffers[0].len = buff_size;
+ sgl->buffers[0].resrvd = 0;
+ sgl->buffers[1].addr = mz_start_phys + offset_of_flat_buffs +
+ (((i * QAT_NUM_BUFS_IN_IM_SGL) + 1) * buff_size);
+ sgl->buffers[1].len = buff_size;
+ sgl->buffers[1].resrvd = 0;
+
+#if 1
+ QAT_LOG(DEBUG, " : phys addr of sgl[%i] in array_of_pointers"
+ "= %lx", i, array_of_pointers->pointer[i]);
+ QAT_LOG(DEBUG, " : virt address of sgl[%i] = %p", i, sgl);
+ QAT_LOG(DEBUG, " : sgl->buffers[0].addr = %lx, len=%d",
+ sgl->buffers[0].addr, sgl->buffers[0].len);
+ QAT_LOG(DEBUG, " : sgl->buffers[1].addr = %lx, len=%d",
+ sgl->buffers[1].addr, sgl->buffers[1].len);
+#endif
+ }
+#if 0
+ QAT_DP_HEXDUMP_LOG(DEBUG, "IM buffer memzone:", mz_start, 1504);
+#endif
+ return memzone;
+}
+
static struct rte_mempool *
qat_comp_create_xform_pool(struct qat_comp_dev_private *comp_dev,
uint32_t num_elements)
@@ -176,6 +272,12 @@ qat_comp_create_xform_pool(struct qat_comp_dev_private *comp_dev,
static void
_qat_comp_dev_config_clear(struct qat_comp_dev_private *comp_dev)
{
+ /* Free intermediate buffers */
+ if (comp_dev->interm_buff_mz) {
+ rte_memzone_free(comp_dev->interm_buff_mz);
+ comp_dev->interm_buff_mz = NULL;
+ }
+
/* Free private_xform pool */
if (comp_dev->xformpool) {
/* Free internal mempool for private xforms */
@@ -197,6 +299,21 @@ qat_comp_dev_config(struct rte_compressdev *dev,
return -EINVAL;
}
+ if (RTE_PMD_QAT_COMP_IM_BUFFER_SIZE == 0) {
+ QAT_LOG(WARNING,
+ "RTE_PMD_QAT_COMP_IM_BUFFER_SIZE = 0 in config file, so"
+ " QAT device can't be used for Dynamic Deflate. "
+ "Did you really intend to do this?");
+ } else {
+ comp_dev->interm_buff_mz =
+ qat_comp_setup_inter_buffers(comp_dev,
+ RTE_PMD_QAT_COMP_IM_BUFFER_SIZE);
+ if (comp_dev->interm_buff_mz == NULL) {
+ ret = -ENOMEM;
+ goto error_out;
+ }
+ }
+
comp_dev->xformpool = qat_comp_create_xform_pool(comp_dev,
config->max_nb_priv_xforms);
if (comp_dev->xformpool == NULL) {
@@ -365,6 +482,10 @@ qat_comp_dev_create(struct qat_pci_device *qat_pci_dev)
QAT_LOG(ERR, "Compression PMD not supported on QAT dh895xcc");
return 0;
}
+ if (qat_pci_dev->qat_dev_gen == QAT_GEN3) {
+ QAT_LOG(ERR, "Compression PMD not supported on QAT c4xxx");
+ return 0;
+ }
struct rte_compressdev_pmd_init_params init_params = {
.name = "",
--
2.7.4
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [dpdk-dev] [PATCH v2] compress/qat: enable dynamic huffman encoding
2018-10-05 16:18 ` [dpdk-dev] [PATCH v2] " Fiona Trahe
@ 2018-10-09 11:01 ` Akhil Goyal
2018-10-09 14:09 ` Trahe, Fiona
2018-10-11 17:03 ` [dpdk-dev] [PATCH v3] " Fiona Trahe
1 sibling, 1 reply; 17+ messages in thread
From: Akhil Goyal @ 2018-10-09 11:01 UTC (permalink / raw)
To: Fiona Trahe, dev; +Cc: tomaszx.jozwiak
On 10/5/2018 9:48 PM, Fiona Trahe wrote:
> Enable dynamic huffman encoding in the QAT comp PMD.
>
> Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
> Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
> ---
> v2 changes:
> - allocate 2 buffers per intermediate buffer sgl
> - Compile out trace for debugging intermediate buffers
>
> Depends on:
> https://patches.dpdk.org/patch/45794/
>
//snip
> +#if 1
> + QAT_LOG(DEBUG, " : phys addr of sgl[%i] in array_of_pointers"
> + "= %lx", i, array_of_pointers->pointer[i]);
> + QAT_LOG(DEBUG, " : virt address of sgl[%i] = %p", i, sgl);
> + QAT_LOG(DEBUG, " : sgl->buffers[0].addr = %lx, len=%d",
> + sgl->buffers[0].addr, sgl->buffers[0].len);
> + QAT_LOG(DEBUG, " : sgl->buffers[1].addr = %lx, len=%d",
> + sgl->buffers[1].addr, sgl->buffers[1].len);
> +#endif
> + }
> +#if 0
> + QAT_DP_HEXDUMP_LOG(DEBUG, "IM buffer memzone:", mz_start, 1504);
> +#endif
I believe #if 0 and #if 1 should be replaced with some debug macros, or
else dynamic logging shall take care of that.
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [dpdk-dev] [PATCH v2] compress/qat: enable dynamic huffman encoding
2018-10-09 11:01 ` Akhil Goyal
@ 2018-10-09 14:09 ` Trahe, Fiona
2018-10-12 11:39 ` Akhil Goyal
0 siblings, 1 reply; 17+ messages in thread
From: Trahe, Fiona @ 2018-10-09 14:09 UTC (permalink / raw)
To: Akhil Goyal, dev; +Cc: Jozwiak, TomaszX, Trahe, Fiona
Hi Akhil,
> -----Original Message-----
> From: Akhil Goyal [mailto:akhil.goyal@nxp.com]
> Sent: Tuesday, October 9, 2018 12:02 PM
> To: Trahe, Fiona <fiona.trahe@intel.com>; dev@dpdk.org
> Cc: Jozwiak, TomaszX <tomaszx.jozwiak@intel.com>
> Subject: Re: [dpdk-dev] [PATCH v2] compress/qat: enable dynamic huffman encoding
>
>
>
> On 10/5/2018 9:48 PM, Fiona Trahe wrote:
> > Enable dynamic huffman encoding in the QAT comp PMD.
> >
> > Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
> > Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
> > ---
> > v2 changes:
> > - allocate 2 buffers per intermediate buffer sgl
> > - Compile out trace for debugging intermediate buffers
> >
> > Depends on:
> > https://patches.dpdk.org/patch/45794/
> >
> //snip
> > +#if 1
> > + QAT_LOG(DEBUG, " : phys addr of sgl[%i] in array_of_pointers"
> > + "= %lx", i, array_of_pointers->pointer[i]);
> > + QAT_LOG(DEBUG, " : virt address of sgl[%i] = %p", i, sgl);
> > + QAT_LOG(DEBUG, " : sgl->buffers[0].addr = %lx, len=%d",
> > + sgl->buffers[0].addr, sgl->buffers[0].len);
> > + QAT_LOG(DEBUG, " : sgl->buffers[1].addr = %lx, len=%d",
> > + sgl->buffers[1].addr, sgl->buffers[1].len);
> > +#endif
> > + }
> > +#if 0
> > + QAT_DP_HEXDUMP_LOG(DEBUG, "IM buffer memzone:", mz_start, 1504);
> > +#endif
>
> I believe #if 0 and #if 1 should be replaced with some debug macros, or
> else dynamic logging shall take care of that.
[Fiona] These are not on the data path, so I didn't think it appropriate to wrap with the DP log level compile option.
And they generate a lot of trace, so make it impossible to see the other debug trace enabled with
dynamic logging using level 8/DEBUG. Really a level 9 would be useful here, but I think this is overkill.
I could have removed this code, but it's handy for debugging.
How about if I add a local QAT define for it?
#define QAT_IM_BUFFER_DEBUG 0
#if QAT_IM_BUFFER_DEBUG
...
#endif
^ permalink raw reply [flat|nested] 17+ messages in thread
* [dpdk-dev] [PATCH v3] compress/qat: enable dynamic huffman encoding
2018-10-05 16:18 ` [dpdk-dev] [PATCH v2] " Fiona Trahe
2018-10-09 11:01 ` Akhil Goyal
@ 2018-10-11 17:03 ` Fiona Trahe
2018-10-15 23:16 ` [dpdk-dev] [PATCH v4] " Fiona Trahe
1 sibling, 1 reply; 17+ messages in thread
From: Fiona Trahe @ 2018-10-11 17:03 UTC (permalink / raw)
To: dev; +Cc: akhil.goyal, tomaszx.jozwiak, arkadiuszx.kusztal, Fiona Trahe
Enable dynamic huffman encoding in the QAT comp PMD.
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
---
v3 changes:
- reverted to 1 buffer per intermediate buffer sgl
v2 changes:
- allocate 2 buffers per intermediate buffer sgl
- Compile out trace for debugging intermediate buffers
config/common_base | 1 +
config/rte_config.h | 1 +
doc/guides/compressdevs/features/qat.ini | 1 +
doc/guides/compressdevs/qat_comp.rst | 7 +-
drivers/common/qat/qat_device.c | 4 +
drivers/common/qat/qat_device.h | 7 ++
drivers/compress/qat/qat_comp.c | 39 +++++++---
drivers/compress/qat/qat_comp.h | 13 ++++
drivers/compress/qat/qat_comp_pmd.c | 123 ++++++++++++++++++++++++++++++-
9 files changed, 179 insertions(+), 17 deletions(-)
diff --git a/config/common_base b/config/common_base
index 85fad0c..9bbce31 100644
--- a/config/common_base
+++ b/config/common_base
@@ -500,6 +500,7 @@ CONFIG_RTE_LIBRTE_PMD_QAT_SYM=n
#
CONFIG_RTE_PMD_QAT_MAX_PCI_DEVICES=48
CONFIG_RTE_PMD_QAT_COMP_SGL_MAX_SEGMENTS=16
+CONFIG_RTE_PMD_QAT_COMP_IM_BUFFER_SIZE=65536
#
# Compile PMD for virtio crypto devices
diff --git a/config/rte_config.h b/config/rte_config.h
index 20c58df..4e501b3 100644
--- a/config/rte_config.h
+++ b/config/rte_config.h
@@ -94,6 +94,7 @@
/* Max. number of QuickAssist devices which can be attached */
#define RTE_PMD_QAT_MAX_PCI_DEVICES 48
#define RTE_PMD_QAT_COMP_SGL_MAX_SEGMENTS 16
+#define RTE_PMD_QAT_COMP_IM_BUFFER_SIZE 65536
/* virtio crypto defines */
#define RTE_MAX_VIRTIO_CRYPTO 32
diff --git a/doc/guides/compressdevs/features/qat.ini b/doc/guides/compressdevs/features/qat.ini
index 5cd4524..6b1e7f9 100644
--- a/doc/guides/compressdevs/features/qat.ini
+++ b/doc/guides/compressdevs/features/qat.ini
@@ -13,3 +13,4 @@ Adler32 = Y
Crc32 = Y
Adler32&Crc32 = Y
Fixed = Y
+Dynamic = Y
diff --git a/doc/guides/compressdevs/qat_comp.rst b/doc/guides/compressdevs/qat_comp.rst
index 7bffbe6..aee3b99 100644
--- a/doc/guides/compressdevs/qat_comp.rst
+++ b/doc/guides/compressdevs/qat_comp.rst
@@ -18,11 +18,7 @@ QAT compression PMD has support for:
Compression/Decompression algorithm:
- * DEFLATE
-
-Huffman code type:
-
- * FIXED
+ * DEFLATE - using Fixed and Dynamic Huffman encoding
Window size support:
@@ -36,7 +32,6 @@ Limitations
-----------
* Compressdev level 0, no compression, is not supported.
-* Dynamic Huffman encoding is not yet supported.
* Queue pairs are not thread-safe (that is, within a single queue pair, RX and TX from different lcores is not supported).
* No BSD support as BSD QAT kernel driver not available.
diff --git a/drivers/common/qat/qat_device.c b/drivers/common/qat/qat_device.c
index 6e64e22..e662e43 100644
--- a/drivers/common/qat/qat_device.c
+++ b/drivers/common/qat/qat_device.c
@@ -7,6 +7,7 @@
#include "qat_device.h"
#include "adf_transport_access_macros.h"
#include "qat_sym_pmd.h"
+#include "qat_comp_pmd.h"
/* Hardware device information per generation */
__extension__
@@ -14,15 +15,18 @@ struct qat_gen_hw_data qat_gen_config[] = {
[QAT_GEN1] = {
.dev_gen = QAT_GEN1,
.qp_hw_data = qat_gen1_qps,
+ .comp_num_im_bufs_required = QAT_NUM_INTERM_BUFS_GEN1
},
[QAT_GEN2] = {
.dev_gen = QAT_GEN2,
.qp_hw_data = qat_gen1_qps,
/* gen2 has same ring layout as gen1 */
+ .comp_num_im_bufs_required = QAT_NUM_INTERM_BUFS_GEN2
},
[QAT_GEN3] = {
.dev_gen = QAT_GEN3,
.qp_hw_data = qat_gen3_qps,
+ .comp_num_im_bufs_required = QAT_NUM_INTERM_BUFS_GEN3
},
};
diff --git a/drivers/common/qat/qat_device.h b/drivers/common/qat/qat_device.h
index 3a71cd4..eb81c78 100644
--- a/drivers/common/qat/qat_device.h
+++ b/drivers/common/qat/qat_device.h
@@ -16,6 +16,12 @@
#define QAT_DEV_NAME_MAX_LEN 64
+enum qat_comp_num_im_buffers {
+ QAT_NUM_INTERM_BUFS_GEN1 = 12,
+ QAT_NUM_INTERM_BUFS_GEN2 = 20,
+ QAT_NUM_INTERM_BUFS_GEN3 = 20
+};
+
/*
* This struct holds all the data about a QAT pci device
* including data about all services it supports.
@@ -72,6 +78,7 @@ struct qat_pci_device {
struct qat_gen_hw_data {
enum qat_device_gen dev_gen;
const struct qat_qp_hw_data (*qp_hw_data)[ADF_MAX_QPS_ON_ANY_SERVICE];
+ enum qat_comp_num_im_buffers comp_num_im_bufs_required;
};
extern struct qat_gen_hw_data qat_gen_config[];
diff --git a/drivers/compress/qat/qat_comp.c b/drivers/compress/qat/qat_comp.c
index b9336f3..d70c594 100644
--- a/drivers/compress/qat/qat_comp.c
+++ b/drivers/compress/qat/qat_comp.c
@@ -192,7 +192,7 @@ static void qat_comp_create_req_hdr(struct icp_qat_fw_comn_req_hdr *header,
}
static int qat_comp_create_templates(struct qat_comp_xform *qat_xform,
- const struct rte_memzone *interm_buff_mz __rte_unused,
+ const struct rte_memzone *interm_buff_mz,
const struct rte_comp_xform *xform)
{
struct icp_qat_fw_comp_req *comp_req;
@@ -280,10 +280,20 @@ static int qat_comp_create_templates(struct qat_comp_xform *qat_xform,
ICP_QAT_FW_COMN_CURR_ID_SET(&comp_req->comp_cd_ctrl,
ICP_QAT_FW_SLICE_COMP);
} else if (qat_xform->qat_comp_request_type ==
- QAT_COMP_REQUEST_DYNAMIC_COMP_STATELESS) {
+ QAT_COMP_REQUEST_DYNAMIC_COMP_STATELESS) {
- QAT_LOG(ERR, "Dynamic huffman encoding not supported");
- return -EINVAL;
+ ICP_QAT_FW_COMN_NEXT_ID_SET(&comp_req->comp_cd_ctrl,
+ ICP_QAT_FW_SLICE_XLAT);
+ ICP_QAT_FW_COMN_CURR_ID_SET(&comp_req->comp_cd_ctrl,
+ ICP_QAT_FW_SLICE_COMP);
+
+ ICP_QAT_FW_COMN_NEXT_ID_SET(&comp_req->u2.xlt_cd_ctrl,
+ ICP_QAT_FW_SLICE_DRAM_WR);
+ ICP_QAT_FW_COMN_CURR_ID_SET(&comp_req->u2.xlt_cd_ctrl,
+ ICP_QAT_FW_SLICE_XLAT);
+
+ comp_req->u1.xlt_pars.inter_buff_ptr =
+ interm_buff_mz->phys_addr;
}
#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
@@ -334,12 +344,6 @@ qat_comp_private_xform_create(struct rte_compressdev *dev,
(struct qat_comp_xform *)*private_xform;
if (xform->type == RTE_COMP_COMPRESS) {
- if (xform->compress.deflate.huffman ==
- RTE_COMP_HUFFMAN_DYNAMIC) {
- QAT_LOG(ERR,
- "QAT device doesn't support dynamic compression");
- return -ENOTSUP;
- }
if (xform->compress.deflate.huffman == RTE_COMP_HUFFMAN_FIXED ||
((xform->compress.deflate.huffman == RTE_COMP_HUFFMAN_DEFAULT)
@@ -347,6 +351,21 @@ qat_comp_private_xform_create(struct rte_compressdev *dev,
qat_xform->qat_comp_request_type =
QAT_COMP_REQUEST_FIXED_COMP_STATELESS;
+ else if ((xform->compress.deflate.huffman ==
+ RTE_COMP_HUFFMAN_DYNAMIC ||
+ xform->compress.deflate.huffman ==
+ RTE_COMP_HUFFMAN_DEFAULT) &&
+ qat->interm_buff_mz != NULL)
+
+ qat_xform->qat_comp_request_type =
+ QAT_COMP_REQUEST_DYNAMIC_COMP_STATELESS;
+
+ else {
+ QAT_LOG(ERR,
+ "IM buffers needed for dynamic deflate. Set size in config file");
+ return -EINVAL;
+ }
+
qat_xform->checksum_type = xform->compress.chksum;
} else {
diff --git a/drivers/compress/qat/qat_comp.h b/drivers/compress/qat/qat_comp.h
index 8d315ef..99a4462 100644
--- a/drivers/compress/qat/qat_comp.h
+++ b/drivers/compress/qat/qat_comp.h
@@ -15,6 +15,10 @@
#include "icp_qat_fw_comp.h"
#include "icp_qat_fw_la.h"
+#define QAT_64_BYTE_ALIGN_MASK (~0x3f)
+#define QAT_64_BYTE_ALIGN (64)
+#define QAT_NUM_BUFS_IN_IM_SGL 1
+
#define ERR_CODE_QAT_COMP_WRONG_FW -99
enum qat_comp_request_type {
@@ -24,6 +28,15 @@ enum qat_comp_request_type {
REQ_COMP_END
};
+struct array_of_ptrs {
+ phys_addr_t pointer[0];
+};
+
+struct qat_inter_sgl {
+ qat_sgl_hdr;
+ struct qat_flat_buf buffers[QAT_NUM_BUFS_IN_IM_SGL];
+} __rte_packed __rte_cache_aligned;
+
struct qat_comp_sgl {
qat_sgl_hdr;
struct qat_flat_buf buffers[RTE_PMD_QAT_COMP_SGL_MAX_SEGMENTS];
diff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c
index 63af23a..8f34682 100644
--- a/drivers/compress/qat/qat_comp_pmd.c
+++ b/drivers/compress/qat/qat_comp_pmd.c
@@ -14,6 +14,7 @@ static const struct rte_compressdev_capabilities qat_comp_gen_capabilities[] = {
RTE_COMP_FF_CRC32_ADLER32_CHECKSUM |
RTE_COMP_FF_SHAREABLE_PRIV_XFORM |
RTE_COMP_FF_HUFFMAN_FIXED |
+ RTE_COMP_FF_HUFFMAN_DYNAMIC |
RTE_COMP_FF_OOP_SGL_IN_SGL_OUT |
RTE_COMP_FF_OOP_SGL_IN_LB_OUT |
RTE_COMP_FF_OOP_LB_IN_SGL_OUT,
@@ -112,7 +113,7 @@ qat_comp_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,
/* store a link to the qp in the qat_pci_device */
qat_private->qat_dev->qps_in_use[QAT_SERVICE_COMPRESSION][qp_id]
- = *qp_addr;
+ = *qp_addr;
qp = (struct qat_qp *)*qp_addr;
@@ -135,6 +136,101 @@ qat_comp_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,
return ret;
}
+
+static const struct rte_memzone *
+qat_comp_setup_inter_buffers(struct qat_comp_dev_private *comp_dev,
+ uint32_t buff_size)
+{
+ char inter_buff_mz_name[RTE_MEMZONE_NAMESIZE];
+ const struct rte_memzone *memzone;
+ uint8_t *mz_start = NULL;
+ phys_addr_t mz_start_phys = 0;
+ struct array_of_ptrs *array_of_pointers;
+ int size_of_ptr_array;
+ uint32_t full_size;
+ uint32_t offset_of_sgls, offset_of_flat_buffs = 0;
+ int i;
+ int num_im_sgls = qat_gen_config[
+ comp_dev->qat_dev->qat_dev_gen].comp_num_im_bufs_required;
+
+ QAT_LOG(DEBUG, "QAT COMP device %s needs %d sgls",
+ comp_dev->qat_dev->name, num_im_sgls);
+ snprintf(inter_buff_mz_name, RTE_MEMZONE_NAMESIZE,
+ "%s_inter_buff", comp_dev->qat_dev->name);
+ memzone = rte_memzone_lookup(inter_buff_mz_name);
+ if (memzone != NULL) {
+ QAT_LOG(DEBUG, "QAT COMP im buffer memzone created already");
+ return memzone;
+ }
+
+ /* Create a memzone to hold intermediate buffers and associated
+ * meta-data needed by the firmware. The memzone contains:
+ * - a list of num_im_sgls physical pointers to sgls
+ * - the num_im_sgl sgl structures, each pointing to 2 flat buffers
+ * - the flat buffers: num_im_sgl * 2
+ * where num_im_sgls depends on the hardware generation of the device
+ */
+
+ size_of_ptr_array = num_im_sgls * sizeof(phys_addr_t);
+ offset_of_sgls = (size_of_ptr_array + (~QAT_64_BYTE_ALIGN_MASK))
+ & QAT_64_BYTE_ALIGN_MASK;
+ offset_of_flat_buffs =
+ offset_of_sgls + num_im_sgls * sizeof(struct qat_inter_sgl);
+ full_size = offset_of_flat_buffs +
+ num_im_sgls * buff_size * QAT_NUM_BUFS_IN_IM_SGL;
+
+ memzone = rte_memzone_reserve_aligned(inter_buff_mz_name, full_size,
+ comp_dev->compressdev->data->socket_id,
+ RTE_MEMZONE_2MB, QAT_64_BYTE_ALIGN);
+ if (memzone == NULL) {
+ QAT_LOG(ERR, "Can't allocate intermediate buffers"
+ " for device %s", comp_dev->qat_dev->name);
+ return NULL;
+ }
+
+ mz_start = (uint8_t *)memzone->addr;
+ mz_start_phys = memzone->phys_addr;
+ QAT_LOG(DEBUG, "Memzone %s: addr = %p, phys = %lx, size required %d,"
+ "size created %ld",
+ inter_buff_mz_name, mz_start, mz_start_phys,
+ full_size, memzone->len);
+
+ array_of_pointers = (struct array_of_ptrs *)mz_start;
+ for (i = 0; i < num_im_sgls; i++) {
+ uint32_t curr_sgl_offset =
+ offset_of_sgls + i * sizeof(struct qat_inter_sgl);
+ struct qat_inter_sgl *sgl =
+ (struct qat_inter_sgl *)(mz_start + curr_sgl_offset);
+ array_of_pointers->pointer[i] = mz_start_phys + curr_sgl_offset;
+
+ sgl->num_bufs = QAT_NUM_BUFS_IN_IM_SGL;
+ sgl->num_mapped_bufs = 0;
+ sgl->resrvd = 0;
+ sgl->buffers[0].addr = mz_start_phys + offset_of_flat_buffs +
+ ((i * QAT_NUM_BUFS_IN_IM_SGL) * buff_size);
+ sgl->buffers[0].len = buff_size;
+ sgl->buffers[0].resrvd = 0;
+ sgl->buffers[1].addr = mz_start_phys + offset_of_flat_buffs +
+ (((i * QAT_NUM_BUFS_IN_IM_SGL) + 1) * buff_size);
+ sgl->buffers[1].len = buff_size;
+ sgl->buffers[1].resrvd = 0;
+
+#if 1
+ QAT_LOG(DEBUG, " : phys addr of sgl[%i] in array_of_pointers"
+ "= %lx", i, array_of_pointers->pointer[i]);
+ QAT_LOG(DEBUG, " : virt address of sgl[%i] = %p", i, sgl);
+ QAT_LOG(DEBUG, " : sgl->buffers[0].addr = %lx, len=%d",
+ sgl->buffers[0].addr, sgl->buffers[0].len);
+ QAT_LOG(DEBUG, " : sgl->buffers[1].addr = %lx, len=%d",
+ sgl->buffers[1].addr, sgl->buffers[1].len);
+#endif
+ }
+#if 0
+ QAT_DP_HEXDUMP_LOG(DEBUG, "IM buffer memzone:", mz_start, 1504);
+#endif
+ return memzone;
+}
+
static struct rte_mempool *
qat_comp_create_xform_pool(struct qat_comp_dev_private *comp_dev,
uint32_t num_elements)
@@ -176,6 +272,12 @@ qat_comp_create_xform_pool(struct qat_comp_dev_private *comp_dev,
static void
_qat_comp_dev_config_clear(struct qat_comp_dev_private *comp_dev)
{
+ /* Free intermediate buffers */
+ if (comp_dev->interm_buff_mz) {
+ rte_memzone_free(comp_dev->interm_buff_mz);
+ comp_dev->interm_buff_mz = NULL;
+ }
+
/* Free private_xform pool */
if (comp_dev->xformpool) {
/* Free internal mempool for private xforms */
@@ -197,6 +299,21 @@ qat_comp_dev_config(struct rte_compressdev *dev,
return -EINVAL;
}
+ if (RTE_PMD_QAT_COMP_IM_BUFFER_SIZE == 0) {
+ QAT_LOG(WARNING,
+ "RTE_PMD_QAT_COMP_IM_BUFFER_SIZE = 0 in config file, so"
+ " QAT device can't be used for Dynamic Deflate. "
+ "Did you really intend to do this?");
+ } else {
+ comp_dev->interm_buff_mz =
+ qat_comp_setup_inter_buffers(comp_dev,
+ RTE_PMD_QAT_COMP_IM_BUFFER_SIZE);
+ if (comp_dev->interm_buff_mz == NULL) {
+ ret = -ENOMEM;
+ goto error_out;
+ }
+ }
+
comp_dev->xformpool = qat_comp_create_xform_pool(comp_dev,
config->max_nb_priv_xforms);
if (comp_dev->xformpool == NULL) {
@@ -365,6 +482,10 @@ qat_comp_dev_create(struct qat_pci_device *qat_pci_dev)
QAT_LOG(ERR, "Compression PMD not supported on QAT dh895xcc");
return 0;
}
+ if (qat_pci_dev->qat_dev_gen == QAT_GEN3) {
+ QAT_LOG(ERR, "Compression PMD not supported on QAT c4xxx");
+ return 0;
+ }
struct rte_compressdev_pmd_init_params init_params = {
.name = "",
--
2.7.4
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [dpdk-dev] [PATCH v2] compress/qat: enable dynamic huffman encoding
2018-10-09 14:09 ` Trahe, Fiona
@ 2018-10-12 11:39 ` Akhil Goyal
0 siblings, 0 replies; 17+ messages in thread
From: Akhil Goyal @ 2018-10-12 11:39 UTC (permalink / raw)
To: Trahe, Fiona, dev; +Cc: Jozwiak, TomaszX
On 10/9/2018 7:39 PM, Trahe, Fiona wrote:
> Hi Akhil,
>
>> -----Original Message-----
>> From: Akhil Goyal [mailto:akhil.goyal@nxp.com]
>> Sent: Tuesday, October 9, 2018 12:02 PM
>> To: Trahe, Fiona <fiona.trahe@intel.com>; dev@dpdk.org
>> Cc: Jozwiak, TomaszX <tomaszx.jozwiak@intel.com>
>> Subject: Re: [dpdk-dev] [PATCH v2] compress/qat: enable dynamic huffman encoding
>>
>>
>>
>> On 10/5/2018 9:48 PM, Fiona Trahe wrote:
>>> Enable dynamic huffman encoding in the QAT comp PMD.
>>>
>>> Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
>>> Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
>>> ---
>>> v2 changes:
>>> - allocate 2 buffers per intermediate buffer sgl
>>> - Compile out trace for debugging intermediate buffers
>>>
>>> Depends on:
>>> https://patches.dpdk.org/patch/45794/
>>>
>> //snip
>>> +#if 1
>>> + QAT_LOG(DEBUG, " : phys addr of sgl[%i] in array_of_pointers"
>>> + "= %lx", i, array_of_pointers->pointer[i]);
>>> + QAT_LOG(DEBUG, " : virt address of sgl[%i] = %p", i, sgl);
>>> + QAT_LOG(DEBUG, " : sgl->buffers[0].addr = %lx, len=%d",
>>> + sgl->buffers[0].addr, sgl->buffers[0].len);
>>> + QAT_LOG(DEBUG, " : sgl->buffers[1].addr = %lx, len=%d",
>>> + sgl->buffers[1].addr, sgl->buffers[1].len);
>>> +#endif
>>> + }
>>> +#if 0
>>> + QAT_DP_HEXDUMP_LOG(DEBUG, "IM buffer memzone:", mz_start, 1504);
>>> +#endif
>> I believe #if 0 and #if 1 should be replaced with some debug macros, or
>> else dynamic logging shall take care of that.
> [Fiona] These are not on the data path, so I didn't think it appropriate to wrap with the DP log level compile option.
> And they generate a lot of trace, so make it impossible to see the other debug trace enabled with
> dynamic logging using level 8/DEBUG. Really a level 9 would be useful here, but I think this is overkill.
> I could have removed this code, but it's handy for debugging.
> How about if I add a local QAT define for it?
> #define QAT_IM_BUFFER_DEBUG 0
> #if QAT_IM_BUFFER_DEBUG
> ...
> #endif
I think local define would be better.
^ permalink raw reply [flat|nested] 17+ messages in thread
* [dpdk-dev] [PATCH v4] compress/qat: enable dynamic huffman encoding
2018-10-11 17:03 ` [dpdk-dev] [PATCH v3] " Fiona Trahe
@ 2018-10-15 23:16 ` Fiona Trahe
2018-10-17 10:29 ` Kusztal, ArkadiuszX
2018-10-17 20:48 ` [dpdk-dev] [PATCH v5] " Fiona Trahe
0 siblings, 2 replies; 17+ messages in thread
From: Fiona Trahe @ 2018-10-15 23:16 UTC (permalink / raw)
To: dev; +Cc: akhil.goyal, tomaszx.jozwiak, arkadiuszx.kusztal, Fiona Trahe
Enable dynamic huffman encoding in the QAT comp PMD.
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
---
v4 changes:
- use #define for IM buffer logs, disable all by default
and use param for clearer hexdump length.
v3 changes:
- reverted to 1 buffer per intermediate buffer sgl
v2 changes:
- allocate 2 buffers per intermediate buffer sgl
- Compile out trace for debugging intermediate buffers
config/common_base | 1 +
config/rte_config.h | 1 +
doc/guides/compressdevs/features/qat.ini | 1 +
doc/guides/compressdevs/qat_comp.rst | 7 +-
drivers/common/qat/qat_device.c | 4 +
drivers/common/qat/qat_device.h | 7 ++
drivers/compress/qat/qat_comp.c | 39 +++++++---
drivers/compress/qat/qat_comp.h | 13 ++++
drivers/compress/qat/qat_comp_pmd.c | 125 ++++++++++++++++++++++++++++++-
9 files changed, 181 insertions(+), 17 deletions(-)
diff --git a/config/common_base b/config/common_base
index 5519d71..29c71b1 100644
--- a/config/common_base
+++ b/config/common_base
@@ -511,6 +511,7 @@ CONFIG_RTE_LIBRTE_PMD_QAT_SYM=n
#
CONFIG_RTE_PMD_QAT_MAX_PCI_DEVICES=48
CONFIG_RTE_PMD_QAT_COMP_SGL_MAX_SEGMENTS=16
+CONFIG_RTE_PMD_QAT_COMP_IM_BUFFER_SIZE=65536
#
# Compile PMD for virtio crypto devices
diff --git a/config/rte_config.h b/config/rte_config.h
index 816e6f8..333fb0b 100644
--- a/config/rte_config.h
+++ b/config/rte_config.h
@@ -95,6 +95,7 @@
/* Max. number of QuickAssist devices which can be attached */
#define RTE_PMD_QAT_MAX_PCI_DEVICES 48
#define RTE_PMD_QAT_COMP_SGL_MAX_SEGMENTS 16
+#define RTE_PMD_QAT_COMP_IM_BUFFER_SIZE 65536
/* virtio crypto defines */
#define RTE_MAX_VIRTIO_CRYPTO 32
diff --git a/doc/guides/compressdevs/features/qat.ini b/doc/guides/compressdevs/features/qat.ini
index 5cd4524..6b1e7f9 100644
--- a/doc/guides/compressdevs/features/qat.ini
+++ b/doc/guides/compressdevs/features/qat.ini
@@ -13,3 +13,4 @@ Adler32 = Y
Crc32 = Y
Adler32&Crc32 = Y
Fixed = Y
+Dynamic = Y
diff --git a/doc/guides/compressdevs/qat_comp.rst b/doc/guides/compressdevs/qat_comp.rst
index 7bffbe6..aee3b99 100644
--- a/doc/guides/compressdevs/qat_comp.rst
+++ b/doc/guides/compressdevs/qat_comp.rst
@@ -18,11 +18,7 @@ QAT compression PMD has support for:
Compression/Decompression algorithm:
- * DEFLATE
-
-Huffman code type:
-
- * FIXED
+ * DEFLATE - using Fixed and Dynamic Huffman encoding
Window size support:
@@ -36,7 +32,6 @@ Limitations
-----------
* Compressdev level 0, no compression, is not supported.
-* Dynamic Huffman encoding is not yet supported.
* Queue pairs are not thread-safe (that is, within a single queue pair, RX and TX from different lcores is not supported).
* No BSD support as BSD QAT kernel driver not available.
diff --git a/drivers/common/qat/qat_device.c b/drivers/common/qat/qat_device.c
index b158fb9..b2db8b0 100644
--- a/drivers/common/qat/qat_device.c
+++ b/drivers/common/qat/qat_device.c
@@ -7,6 +7,7 @@
#include "qat_device.h"
#include "adf_transport_access_macros.h"
#include "qat_sym_pmd.h"
+#include "qat_comp_pmd.h"
/* Hardware device information per generation */
__extension__
@@ -14,15 +15,18 @@ struct qat_gen_hw_data qat_gen_config[] = {
[QAT_GEN1] = {
.dev_gen = QAT_GEN1,
.qp_hw_data = qat_gen1_qps,
+ .comp_num_im_bufs_required = QAT_NUM_INTERM_BUFS_GEN1
},
[QAT_GEN2] = {
.dev_gen = QAT_GEN2,
.qp_hw_data = qat_gen1_qps,
/* gen2 has same ring layout as gen1 */
+ .comp_num_im_bufs_required = QAT_NUM_INTERM_BUFS_GEN2
},
[QAT_GEN3] = {
.dev_gen = QAT_GEN3,
.qp_hw_data = qat_gen3_qps,
+ .comp_num_im_bufs_required = QAT_NUM_INTERM_BUFS_GEN3
},
};
diff --git a/drivers/common/qat/qat_device.h b/drivers/common/qat/qat_device.h
index 3a71cd4..eb81c78 100644
--- a/drivers/common/qat/qat_device.h
+++ b/drivers/common/qat/qat_device.h
@@ -16,6 +16,12 @@
#define QAT_DEV_NAME_MAX_LEN 64
+enum qat_comp_num_im_buffers {
+ QAT_NUM_INTERM_BUFS_GEN1 = 12,
+ QAT_NUM_INTERM_BUFS_GEN2 = 20,
+ QAT_NUM_INTERM_BUFS_GEN3 = 20
+};
+
/*
* This struct holds all the data about a QAT pci device
* including data about all services it supports.
@@ -72,6 +78,7 @@ struct qat_pci_device {
struct qat_gen_hw_data {
enum qat_device_gen dev_gen;
const struct qat_qp_hw_data (*qp_hw_data)[ADF_MAX_QPS_ON_ANY_SERVICE];
+ enum qat_comp_num_im_buffers comp_num_im_bufs_required;
};
extern struct qat_gen_hw_data qat_gen_config[];
diff --git a/drivers/compress/qat/qat_comp.c b/drivers/compress/qat/qat_comp.c
index b9336f3..d70c594 100644
--- a/drivers/compress/qat/qat_comp.c
+++ b/drivers/compress/qat/qat_comp.c
@@ -192,7 +192,7 @@ static void qat_comp_create_req_hdr(struct icp_qat_fw_comn_req_hdr *header,
}
static int qat_comp_create_templates(struct qat_comp_xform *qat_xform,
- const struct rte_memzone *interm_buff_mz __rte_unused,
+ const struct rte_memzone *interm_buff_mz,
const struct rte_comp_xform *xform)
{
struct icp_qat_fw_comp_req *comp_req;
@@ -280,10 +280,20 @@ static int qat_comp_create_templates(struct qat_comp_xform *qat_xform,
ICP_QAT_FW_COMN_CURR_ID_SET(&comp_req->comp_cd_ctrl,
ICP_QAT_FW_SLICE_COMP);
} else if (qat_xform->qat_comp_request_type ==
- QAT_COMP_REQUEST_DYNAMIC_COMP_STATELESS) {
+ QAT_COMP_REQUEST_DYNAMIC_COMP_STATELESS) {
- QAT_LOG(ERR, "Dynamic huffman encoding not supported");
- return -EINVAL;
+ ICP_QAT_FW_COMN_NEXT_ID_SET(&comp_req->comp_cd_ctrl,
+ ICP_QAT_FW_SLICE_XLAT);
+ ICP_QAT_FW_COMN_CURR_ID_SET(&comp_req->comp_cd_ctrl,
+ ICP_QAT_FW_SLICE_COMP);
+
+ ICP_QAT_FW_COMN_NEXT_ID_SET(&comp_req->u2.xlt_cd_ctrl,
+ ICP_QAT_FW_SLICE_DRAM_WR);
+ ICP_QAT_FW_COMN_CURR_ID_SET(&comp_req->u2.xlt_cd_ctrl,
+ ICP_QAT_FW_SLICE_XLAT);
+
+ comp_req->u1.xlt_pars.inter_buff_ptr =
+ interm_buff_mz->phys_addr;
}
#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
@@ -334,12 +344,6 @@ qat_comp_private_xform_create(struct rte_compressdev *dev,
(struct qat_comp_xform *)*private_xform;
if (xform->type == RTE_COMP_COMPRESS) {
- if (xform->compress.deflate.huffman ==
- RTE_COMP_HUFFMAN_DYNAMIC) {
- QAT_LOG(ERR,
- "QAT device doesn't support dynamic compression");
- return -ENOTSUP;
- }
if (xform->compress.deflate.huffman == RTE_COMP_HUFFMAN_FIXED ||
((xform->compress.deflate.huffman == RTE_COMP_HUFFMAN_DEFAULT)
@@ -347,6 +351,21 @@ qat_comp_private_xform_create(struct rte_compressdev *dev,
qat_xform->qat_comp_request_type =
QAT_COMP_REQUEST_FIXED_COMP_STATELESS;
+ else if ((xform->compress.deflate.huffman ==
+ RTE_COMP_HUFFMAN_DYNAMIC ||
+ xform->compress.deflate.huffman ==
+ RTE_COMP_HUFFMAN_DEFAULT) &&
+ qat->interm_buff_mz != NULL)
+
+ qat_xform->qat_comp_request_type =
+ QAT_COMP_REQUEST_DYNAMIC_COMP_STATELESS;
+
+ else {
+ QAT_LOG(ERR,
+ "IM buffers needed for dynamic deflate. Set size in config file");
+ return -EINVAL;
+ }
+
qat_xform->checksum_type = xform->compress.chksum;
} else {
diff --git a/drivers/compress/qat/qat_comp.h b/drivers/compress/qat/qat_comp.h
index 8d315ef..99a4462 100644
--- a/drivers/compress/qat/qat_comp.h
+++ b/drivers/compress/qat/qat_comp.h
@@ -15,6 +15,10 @@
#include "icp_qat_fw_comp.h"
#include "icp_qat_fw_la.h"
+#define QAT_64_BYTE_ALIGN_MASK (~0x3f)
+#define QAT_64_BYTE_ALIGN (64)
+#define QAT_NUM_BUFS_IN_IM_SGL 1
+
#define ERR_CODE_QAT_COMP_WRONG_FW -99
enum qat_comp_request_type {
@@ -24,6 +28,15 @@ enum qat_comp_request_type {
REQ_COMP_END
};
+struct array_of_ptrs {
+ phys_addr_t pointer[0];
+};
+
+struct qat_inter_sgl {
+ qat_sgl_hdr;
+ struct qat_flat_buf buffers[QAT_NUM_BUFS_IN_IM_SGL];
+} __rte_packed __rte_cache_aligned;
+
struct qat_comp_sgl {
qat_sgl_hdr;
struct qat_flat_buf buffers[RTE_PMD_QAT_COMP_SGL_MAX_SEGMENTS];
diff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c
index 63af23a..8ea634e 100644
--- a/drivers/compress/qat/qat_comp_pmd.c
+++ b/drivers/compress/qat/qat_comp_pmd.c
@@ -14,6 +14,7 @@ static const struct rte_compressdev_capabilities qat_comp_gen_capabilities[] = {
RTE_COMP_FF_CRC32_ADLER32_CHECKSUM |
RTE_COMP_FF_SHAREABLE_PRIV_XFORM |
RTE_COMP_FF_HUFFMAN_FIXED |
+ RTE_COMP_FF_HUFFMAN_DYNAMIC |
RTE_COMP_FF_OOP_SGL_IN_SGL_OUT |
RTE_COMP_FF_OOP_SGL_IN_LB_OUT |
RTE_COMP_FF_OOP_LB_IN_SGL_OUT,
@@ -112,7 +113,7 @@ qat_comp_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,
/* store a link to the qp in the qat_pci_device */
qat_private->qat_dev->qps_in_use[QAT_SERVICE_COMPRESSION][qp_id]
- = *qp_addr;
+ = *qp_addr;
qp = (struct qat_qp *)*qp_addr;
@@ -135,6 +136,103 @@ qat_comp_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,
return ret;
}
+
+#define QAT_IM_BUFFER_DEBUG 0
+static const struct rte_memzone *
+qat_comp_setup_inter_buffers(struct qat_comp_dev_private *comp_dev,
+ uint32_t buff_size)
+{
+ char inter_buff_mz_name[RTE_MEMZONE_NAMESIZE];
+ const struct rte_memzone *memzone;
+ uint8_t *mz_start = NULL;
+ phys_addr_t mz_start_phys = 0;
+ struct array_of_ptrs *array_of_pointers;
+ int size_of_ptr_array;
+ uint32_t full_size;
+ uint32_t offset_of_sgls, offset_of_flat_buffs = 0;
+ int i;
+ int num_im_sgls = qat_gen_config[
+ comp_dev->qat_dev->qat_dev_gen].comp_num_im_bufs_required;
+
+ QAT_LOG(DEBUG, "QAT COMP device %s needs %d sgls",
+ comp_dev->qat_dev->name, num_im_sgls);
+ snprintf(inter_buff_mz_name, RTE_MEMZONE_NAMESIZE,
+ "%s_inter_buff", comp_dev->qat_dev->name);
+ memzone = rte_memzone_lookup(inter_buff_mz_name);
+ if (memzone != NULL) {
+ QAT_LOG(DEBUG, "QAT COMP im buffer memzone created already");
+ return memzone;
+ }
+
+ /* Create a memzone to hold intermediate buffers and associated
+ * meta-data needed by the firmware. The memzone contains:
+ * - a list of num_im_sgls physical pointers to sgls
+ * - the num_im_sgl sgl structures, each pointing to 2 flat buffers
+ * - the flat buffers: num_im_sgl * 2
+ * where num_im_sgls depends on the hardware generation of the device
+ */
+
+ size_of_ptr_array = num_im_sgls * sizeof(phys_addr_t);
+ offset_of_sgls = (size_of_ptr_array + (~QAT_64_BYTE_ALIGN_MASK))
+ & QAT_64_BYTE_ALIGN_MASK;
+ offset_of_flat_buffs =
+ offset_of_sgls + num_im_sgls * sizeof(struct qat_inter_sgl);
+ full_size = offset_of_flat_buffs +
+ num_im_sgls * buff_size * QAT_NUM_BUFS_IN_IM_SGL;
+
+ memzone = rte_memzone_reserve_aligned(inter_buff_mz_name, full_size,
+ comp_dev->compressdev->data->socket_id,
+ RTE_MEMZONE_2MB, QAT_64_BYTE_ALIGN);
+ if (memzone == NULL) {
+ QAT_LOG(ERR, "Can't allocate intermediate buffers"
+ " for device %s", comp_dev->qat_dev->name);
+ return NULL;
+ }
+
+ mz_start = (uint8_t *)memzone->addr;
+ mz_start_phys = memzone->phys_addr;
+ QAT_LOG(DEBUG, "Memzone %s: addr = %p, phys = %lx, size required %d,"
+ "size created %ld",
+ inter_buff_mz_name, mz_start, mz_start_phys,
+ full_size, memzone->len);
+
+ array_of_pointers = (struct array_of_ptrs *)mz_start;
+ for (i = 0; i < num_im_sgls; i++) {
+ uint32_t curr_sgl_offset =
+ offset_of_sgls + i * sizeof(struct qat_inter_sgl);
+ struct qat_inter_sgl *sgl =
+ (struct qat_inter_sgl *)(mz_start + curr_sgl_offset);
+ array_of_pointers->pointer[i] = mz_start_phys + curr_sgl_offset;
+
+ sgl->num_bufs = QAT_NUM_BUFS_IN_IM_SGL;
+ sgl->num_mapped_bufs = 0;
+ sgl->resrvd = 0;
+ sgl->buffers[0].addr = mz_start_phys + offset_of_flat_buffs +
+ ((i * QAT_NUM_BUFS_IN_IM_SGL) * buff_size);
+ sgl->buffers[0].len = buff_size;
+ sgl->buffers[0].resrvd = 0;
+ sgl->buffers[1].addr = mz_start_phys + offset_of_flat_buffs +
+ (((i * QAT_NUM_BUFS_IN_IM_SGL) + 1) * buff_size);
+ sgl->buffers[1].len = buff_size;
+ sgl->buffers[1].resrvd = 0;
+
+#if QAT_IM_BUFFER_DEBUG
+ QAT_LOG(DEBUG, " : phys addr of sgl[%i] in array_of_pointers"
+ "= %lx", i, array_of_pointers->pointer[i]);
+ QAT_LOG(DEBUG, " : virt address of sgl[%i] = %p", i, sgl);
+ QAT_LOG(DEBUG, " : sgl->buffers[0].addr = %lx, len=%d",
+ sgl->buffers[0].addr, sgl->buffers[0].len);
+ QAT_LOG(DEBUG, " : sgl->buffers[1].addr = %lx, len=%d",
+ sgl->buffers[1].addr, sgl->buffers[1].len);
+#endif
+ }
+#if QAT_IM_BUFFER_DEBUG
+ QAT_DP_HEXDUMP_LOG(DEBUG, "IM buffer memzone start:",
+ mz_start, offset_of_flat_buffs + 32);
+#endif
+ return memzone;
+}
+
static struct rte_mempool *
qat_comp_create_xform_pool(struct qat_comp_dev_private *comp_dev,
uint32_t num_elements)
@@ -176,6 +274,12 @@ qat_comp_create_xform_pool(struct qat_comp_dev_private *comp_dev,
static void
_qat_comp_dev_config_clear(struct qat_comp_dev_private *comp_dev)
{
+ /* Free intermediate buffers */
+ if (comp_dev->interm_buff_mz) {
+ rte_memzone_free(comp_dev->interm_buff_mz);
+ comp_dev->interm_buff_mz = NULL;
+ }
+
/* Free private_xform pool */
if (comp_dev->xformpool) {
/* Free internal mempool for private xforms */
@@ -197,6 +301,21 @@ qat_comp_dev_config(struct rte_compressdev *dev,
return -EINVAL;
}
+ if (RTE_PMD_QAT_COMP_IM_BUFFER_SIZE == 0) {
+ QAT_LOG(WARNING,
+ "RTE_PMD_QAT_COMP_IM_BUFFER_SIZE = 0 in config file, so"
+ " QAT device can't be used for Dynamic Deflate. "
+ "Did you really intend to do this?");
+ } else {
+ comp_dev->interm_buff_mz =
+ qat_comp_setup_inter_buffers(comp_dev,
+ RTE_PMD_QAT_COMP_IM_BUFFER_SIZE);
+ if (comp_dev->interm_buff_mz == NULL) {
+ ret = -ENOMEM;
+ goto error_out;
+ }
+ }
+
comp_dev->xformpool = qat_comp_create_xform_pool(comp_dev,
config->max_nb_priv_xforms);
if (comp_dev->xformpool == NULL) {
@@ -365,6 +484,10 @@ qat_comp_dev_create(struct qat_pci_device *qat_pci_dev)
QAT_LOG(ERR, "Compression PMD not supported on QAT dh895xcc");
return 0;
}
+ if (qat_pci_dev->qat_dev_gen == QAT_GEN3) {
+ QAT_LOG(ERR, "Compression PMD not supported on QAT c4xxx");
+ return 0;
+ }
struct rte_compressdev_pmd_init_params init_params = {
.name = "",
--
2.7.4
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [dpdk-dev] [PATCH v4] compress/qat: enable dynamic huffman encoding
2018-10-15 23:16 ` [dpdk-dev] [PATCH v4] " Fiona Trahe
@ 2018-10-17 10:29 ` Kusztal, ArkadiuszX
2018-10-17 20:48 ` [dpdk-dev] [PATCH v5] " Fiona Trahe
1 sibling, 0 replies; 17+ messages in thread
From: Kusztal, ArkadiuszX @ 2018-10-17 10:29 UTC (permalink / raw)
To: Trahe, Fiona, dev; +Cc: akhil.goyal, Jozwiak, TomaszX
> -----Original Message-----
> From: Trahe, Fiona
> Sent: Tuesday, October 16, 2018 1:16 AM
> To: dev@dpdk.org
> Cc: akhil.goyal@nxp.com; Jozwiak, TomaszX <tomaszx.jozwiak@intel.com>;
> Kusztal, ArkadiuszX <arkadiuszx.kusztal@intel.com>; Trahe, Fiona
> <fiona.trahe@intel.com>
> Subject: [PATCH v4] compress/qat: enable dynamic huffman encoding
>
> Enable dynamic huffman encoding in the QAT comp PMD.
>
> Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
> Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
> ---
> v4 changes:
> - use #define for IM buffer logs, disable all by default
> and use param for clearer hexdump length.
>
> v3 changes:
> - reverted to 1 buffer per intermediate buffer sgl
>
> v2 changes:
> - allocate 2 buffers per intermediate buffer sgl
> - Compile out trace for debugging intermediate buffers
>
> config/common_base | 1 +
> config/rte_config.h | 1 +
> doc/guides/compressdevs/features/qat.ini | 1 +
> doc/guides/compressdevs/qat_comp.rst | 7 +-
> drivers/common/qat/qat_device.c | 4 +
> drivers/common/qat/qat_device.h | 7 ++
> drivers/compress/qat/qat_comp.c | 39 +++++++---
> drivers/compress/qat/qat_comp.h | 13 ++++
> drivers/compress/qat/qat_comp_pmd.c | 125
> ++++++++++++++++++++++++++++++-
> 9 files changed, 181 insertions(+), 17 deletions(-)
>
> diff --git a/config/common_base b/config/common_base index
> 5519d71..29c71b1 100644
> --- a/config/common_base
> +++ b/config/common_base
> 2.7.4
Acked-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
^ permalink raw reply [flat|nested] 17+ messages in thread
* [dpdk-dev] [PATCH v5] compress/qat: enable dynamic huffman encoding
2018-10-15 23:16 ` [dpdk-dev] [PATCH v4] " Fiona Trahe
2018-10-17 10:29 ` Kusztal, ArkadiuszX
@ 2018-10-17 20:48 ` Fiona Trahe
2018-10-24 14:15 ` Akhil Goyal
2018-10-25 1:30 ` [dpdk-dev] [PATCH v6] " Fiona Trahe
1 sibling, 2 replies; 17+ messages in thread
From: Fiona Trahe @ 2018-10-17 20:48 UTC (permalink / raw)
To: dev; +Cc: akhil.goyal, tomaszx.jozwiak, arkadiuszx.kusztal, Fiona Trahe
Enable dynamic huffman encoding in the QAT comp PMD.
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Acked-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
---
v5 changes:
- update release note
v4 changes:
- use #define for IM buffer logs, disable all by default
and use param for clearer hexdump length.
v3 changes:
- reverted to 1 buffer per intermediate buffer sgl
v2 changes:
- allocate 2 buffers per intermediate buffer sgl
- Compile out trace for debugging intermediate buffers
config/common_base | 1 +
config/rte_config.h | 1 +
doc/guides/compressdevs/features/qat.ini | 1 +
doc/guides/compressdevs/qat_comp.rst | 7 +-
doc/guides/rel_notes/release_18_11.rst | 5 ++
drivers/common/qat/qat_device.c | 4 +
drivers/common/qat/qat_device.h | 7 ++
drivers/compress/qat/qat_comp.c | 39 +++++++---
drivers/compress/qat/qat_comp.h | 13 ++++
drivers/compress/qat/qat_comp_pmd.c | 125 ++++++++++++++++++++++++++++++-
10 files changed, 186 insertions(+), 17 deletions(-)
diff --git a/config/common_base b/config/common_base
index 9f45d9e..7ccf11b 100644
--- a/config/common_base
+++ b/config/common_base
@@ -522,6 +522,7 @@ CONFIG_RTE_LIBRTE_PMD_QAT_SYM=n
#
CONFIG_RTE_PMD_QAT_MAX_PCI_DEVICES=48
CONFIG_RTE_PMD_QAT_COMP_SGL_MAX_SEGMENTS=16
+CONFIG_RTE_PMD_QAT_COMP_IM_BUFFER_SIZE=65536
#
# Compile PMD for virtio crypto devices
diff --git a/config/rte_config.h b/config/rte_config.h
index 816e6f8..333fb0b 100644
--- a/config/rte_config.h
+++ b/config/rte_config.h
@@ -95,6 +95,7 @@
/* Max. number of QuickAssist devices which can be attached */
#define RTE_PMD_QAT_MAX_PCI_DEVICES 48
#define RTE_PMD_QAT_COMP_SGL_MAX_SEGMENTS 16
+#define RTE_PMD_QAT_COMP_IM_BUFFER_SIZE 65536
/* virtio crypto defines */
#define RTE_MAX_VIRTIO_CRYPTO 32
diff --git a/doc/guides/compressdevs/features/qat.ini b/doc/guides/compressdevs/features/qat.ini
index 5cd4524..6b1e7f9 100644
--- a/doc/guides/compressdevs/features/qat.ini
+++ b/doc/guides/compressdevs/features/qat.ini
@@ -13,3 +13,4 @@ Adler32 = Y
Crc32 = Y
Adler32&Crc32 = Y
Fixed = Y
+Dynamic = Y
diff --git a/doc/guides/compressdevs/qat_comp.rst b/doc/guides/compressdevs/qat_comp.rst
index 7bffbe6..aee3b99 100644
--- a/doc/guides/compressdevs/qat_comp.rst
+++ b/doc/guides/compressdevs/qat_comp.rst
@@ -18,11 +18,7 @@ QAT compression PMD has support for:
Compression/Decompression algorithm:
- * DEFLATE
-
-Huffman code type:
-
- * FIXED
+ * DEFLATE - using Fixed and Dynamic Huffman encoding
Window size support:
@@ -36,7 +32,6 @@ Limitations
-----------
* Compressdev level 0, no compression, is not supported.
-* Dynamic Huffman encoding is not yet supported.
* Queue pairs are not thread-safe (that is, within a single queue pair, RX and TX from different lcores is not supported).
* No BSD support as BSD QAT kernel driver not available.
diff --git a/doc/guides/rel_notes/release_18_11.rst b/doc/guides/rel_notes/release_18_11.rst
index af9a6f8..3031e4f 100644
--- a/doc/guides/rel_notes/release_18_11.rst
+++ b/doc/guides/rel_notes/release_18_11.rst
@@ -191,6 +191,11 @@ New Features
Added the new caam job ring driver for NXP platforms. See the
"NXP CAAM JOB RING (caam_jr)" document for more details on this new driver.
+* **Added support for Dynamic Huffman Encoding to Intel QAT comp PMD.**
+
+ The Intel QuickAssist (QAT) compression PMD has been updated with support
+ for Dynamic Huffman Encoding for the Deflate algorithm.
+
API Changes
-----------
diff --git a/drivers/common/qat/qat_device.c b/drivers/common/qat/qat_device.c
index 8d4df92..5df831f 100644
--- a/drivers/common/qat/qat_device.c
+++ b/drivers/common/qat/qat_device.c
@@ -7,6 +7,7 @@
#include "qat_device.h"
#include "adf_transport_access_macros.h"
#include "qat_sym_pmd.h"
+#include "qat_comp_pmd.h"
/* Hardware device information per generation */
__extension__
@@ -14,15 +15,18 @@ struct qat_gen_hw_data qat_gen_config[] = {
[QAT_GEN1] = {
.dev_gen = QAT_GEN1,
.qp_hw_data = qat_gen1_qps,
+ .comp_num_im_bufs_required = QAT_NUM_INTERM_BUFS_GEN1
},
[QAT_GEN2] = {
.dev_gen = QAT_GEN2,
.qp_hw_data = qat_gen1_qps,
/* gen2 has same ring layout as gen1 */
+ .comp_num_im_bufs_required = QAT_NUM_INTERM_BUFS_GEN2
},
[QAT_GEN3] = {
.dev_gen = QAT_GEN3,
.qp_hw_data = qat_gen3_qps,
+ .comp_num_im_bufs_required = QAT_NUM_INTERM_BUFS_GEN3
},
};
diff --git a/drivers/common/qat/qat_device.h b/drivers/common/qat/qat_device.h
index 3a71cd4..eb81c78 100644
--- a/drivers/common/qat/qat_device.h
+++ b/drivers/common/qat/qat_device.h
@@ -16,6 +16,12 @@
#define QAT_DEV_NAME_MAX_LEN 64
+enum qat_comp_num_im_buffers {
+ QAT_NUM_INTERM_BUFS_GEN1 = 12,
+ QAT_NUM_INTERM_BUFS_GEN2 = 20,
+ QAT_NUM_INTERM_BUFS_GEN3 = 20
+};
+
/*
* This struct holds all the data about a QAT pci device
* including data about all services it supports.
@@ -72,6 +78,7 @@ struct qat_pci_device {
struct qat_gen_hw_data {
enum qat_device_gen dev_gen;
const struct qat_qp_hw_data (*qp_hw_data)[ADF_MAX_QPS_ON_ANY_SERVICE];
+ enum qat_comp_num_im_buffers comp_num_im_bufs_required;
};
extern struct qat_gen_hw_data qat_gen_config[];
diff --git a/drivers/compress/qat/qat_comp.c b/drivers/compress/qat/qat_comp.c
index b9336f3..d70c594 100644
--- a/drivers/compress/qat/qat_comp.c
+++ b/drivers/compress/qat/qat_comp.c
@@ -192,7 +192,7 @@ static void qat_comp_create_req_hdr(struct icp_qat_fw_comn_req_hdr *header,
}
static int qat_comp_create_templates(struct qat_comp_xform *qat_xform,
- const struct rte_memzone *interm_buff_mz __rte_unused,
+ const struct rte_memzone *interm_buff_mz,
const struct rte_comp_xform *xform)
{
struct icp_qat_fw_comp_req *comp_req;
@@ -280,10 +280,20 @@ static int qat_comp_create_templates(struct qat_comp_xform *qat_xform,
ICP_QAT_FW_COMN_CURR_ID_SET(&comp_req->comp_cd_ctrl,
ICP_QAT_FW_SLICE_COMP);
} else if (qat_xform->qat_comp_request_type ==
- QAT_COMP_REQUEST_DYNAMIC_COMP_STATELESS) {
+ QAT_COMP_REQUEST_DYNAMIC_COMP_STATELESS) {
- QAT_LOG(ERR, "Dynamic huffman encoding not supported");
- return -EINVAL;
+ ICP_QAT_FW_COMN_NEXT_ID_SET(&comp_req->comp_cd_ctrl,
+ ICP_QAT_FW_SLICE_XLAT);
+ ICP_QAT_FW_COMN_CURR_ID_SET(&comp_req->comp_cd_ctrl,
+ ICP_QAT_FW_SLICE_COMP);
+
+ ICP_QAT_FW_COMN_NEXT_ID_SET(&comp_req->u2.xlt_cd_ctrl,
+ ICP_QAT_FW_SLICE_DRAM_WR);
+ ICP_QAT_FW_COMN_CURR_ID_SET(&comp_req->u2.xlt_cd_ctrl,
+ ICP_QAT_FW_SLICE_XLAT);
+
+ comp_req->u1.xlt_pars.inter_buff_ptr =
+ interm_buff_mz->phys_addr;
}
#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
@@ -334,12 +344,6 @@ qat_comp_private_xform_create(struct rte_compressdev *dev,
(struct qat_comp_xform *)*private_xform;
if (xform->type == RTE_COMP_COMPRESS) {
- if (xform->compress.deflate.huffman ==
- RTE_COMP_HUFFMAN_DYNAMIC) {
- QAT_LOG(ERR,
- "QAT device doesn't support dynamic compression");
- return -ENOTSUP;
- }
if (xform->compress.deflate.huffman == RTE_COMP_HUFFMAN_FIXED ||
((xform->compress.deflate.huffman == RTE_COMP_HUFFMAN_DEFAULT)
@@ -347,6 +351,21 @@ qat_comp_private_xform_create(struct rte_compressdev *dev,
qat_xform->qat_comp_request_type =
QAT_COMP_REQUEST_FIXED_COMP_STATELESS;
+ else if ((xform->compress.deflate.huffman ==
+ RTE_COMP_HUFFMAN_DYNAMIC ||
+ xform->compress.deflate.huffman ==
+ RTE_COMP_HUFFMAN_DEFAULT) &&
+ qat->interm_buff_mz != NULL)
+
+ qat_xform->qat_comp_request_type =
+ QAT_COMP_REQUEST_DYNAMIC_COMP_STATELESS;
+
+ else {
+ QAT_LOG(ERR,
+ "IM buffers needed for dynamic deflate. Set size in config file");
+ return -EINVAL;
+ }
+
qat_xform->checksum_type = xform->compress.chksum;
} else {
diff --git a/drivers/compress/qat/qat_comp.h b/drivers/compress/qat/qat_comp.h
index 8d315ef..99a4462 100644
--- a/drivers/compress/qat/qat_comp.h
+++ b/drivers/compress/qat/qat_comp.h
@@ -15,6 +15,10 @@
#include "icp_qat_fw_comp.h"
#include "icp_qat_fw_la.h"
+#define QAT_64_BYTE_ALIGN_MASK (~0x3f)
+#define QAT_64_BYTE_ALIGN (64)
+#define QAT_NUM_BUFS_IN_IM_SGL 1
+
#define ERR_CODE_QAT_COMP_WRONG_FW -99
enum qat_comp_request_type {
@@ -24,6 +28,15 @@ enum qat_comp_request_type {
REQ_COMP_END
};
+struct array_of_ptrs {
+ phys_addr_t pointer[0];
+};
+
+struct qat_inter_sgl {
+ qat_sgl_hdr;
+ struct qat_flat_buf buffers[QAT_NUM_BUFS_IN_IM_SGL];
+} __rte_packed __rte_cache_aligned;
+
struct qat_comp_sgl {
qat_sgl_hdr;
struct qat_flat_buf buffers[RTE_PMD_QAT_COMP_SGL_MAX_SEGMENTS];
diff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c
index 63af23a..8ea634e 100644
--- a/drivers/compress/qat/qat_comp_pmd.c
+++ b/drivers/compress/qat/qat_comp_pmd.c
@@ -14,6 +14,7 @@ static const struct rte_compressdev_capabilities qat_comp_gen_capabilities[] = {
RTE_COMP_FF_CRC32_ADLER32_CHECKSUM |
RTE_COMP_FF_SHAREABLE_PRIV_XFORM |
RTE_COMP_FF_HUFFMAN_FIXED |
+ RTE_COMP_FF_HUFFMAN_DYNAMIC |
RTE_COMP_FF_OOP_SGL_IN_SGL_OUT |
RTE_COMP_FF_OOP_SGL_IN_LB_OUT |
RTE_COMP_FF_OOP_LB_IN_SGL_OUT,
@@ -112,7 +113,7 @@ qat_comp_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,
/* store a link to the qp in the qat_pci_device */
qat_private->qat_dev->qps_in_use[QAT_SERVICE_COMPRESSION][qp_id]
- = *qp_addr;
+ = *qp_addr;
qp = (struct qat_qp *)*qp_addr;
@@ -135,6 +136,103 @@ qat_comp_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,
return ret;
}
+
+#define QAT_IM_BUFFER_DEBUG 0
+static const struct rte_memzone *
+qat_comp_setup_inter_buffers(struct qat_comp_dev_private *comp_dev,
+ uint32_t buff_size)
+{
+ char inter_buff_mz_name[RTE_MEMZONE_NAMESIZE];
+ const struct rte_memzone *memzone;
+ uint8_t *mz_start = NULL;
+ phys_addr_t mz_start_phys = 0;
+ struct array_of_ptrs *array_of_pointers;
+ int size_of_ptr_array;
+ uint32_t full_size;
+ uint32_t offset_of_sgls, offset_of_flat_buffs = 0;
+ int i;
+ int num_im_sgls = qat_gen_config[
+ comp_dev->qat_dev->qat_dev_gen].comp_num_im_bufs_required;
+
+ QAT_LOG(DEBUG, "QAT COMP device %s needs %d sgls",
+ comp_dev->qat_dev->name, num_im_sgls);
+ snprintf(inter_buff_mz_name, RTE_MEMZONE_NAMESIZE,
+ "%s_inter_buff", comp_dev->qat_dev->name);
+ memzone = rte_memzone_lookup(inter_buff_mz_name);
+ if (memzone != NULL) {
+ QAT_LOG(DEBUG, "QAT COMP im buffer memzone created already");
+ return memzone;
+ }
+
+ /* Create a memzone to hold intermediate buffers and associated
+ * meta-data needed by the firmware. The memzone contains:
+ * - a list of num_im_sgls physical pointers to sgls
+ * - the num_im_sgl sgl structures, each pointing to 2 flat buffers
+ * - the flat buffers: num_im_sgl * 2
+ * where num_im_sgls depends on the hardware generation of the device
+ */
+
+ size_of_ptr_array = num_im_sgls * sizeof(phys_addr_t);
+ offset_of_sgls = (size_of_ptr_array + (~QAT_64_BYTE_ALIGN_MASK))
+ & QAT_64_BYTE_ALIGN_MASK;
+ offset_of_flat_buffs =
+ offset_of_sgls + num_im_sgls * sizeof(struct qat_inter_sgl);
+ full_size = offset_of_flat_buffs +
+ num_im_sgls * buff_size * QAT_NUM_BUFS_IN_IM_SGL;
+
+ memzone = rte_memzone_reserve_aligned(inter_buff_mz_name, full_size,
+ comp_dev->compressdev->data->socket_id,
+ RTE_MEMZONE_2MB, QAT_64_BYTE_ALIGN);
+ if (memzone == NULL) {
+ QAT_LOG(ERR, "Can't allocate intermediate buffers"
+ " for device %s", comp_dev->qat_dev->name);
+ return NULL;
+ }
+
+ mz_start = (uint8_t *)memzone->addr;
+ mz_start_phys = memzone->phys_addr;
+ QAT_LOG(DEBUG, "Memzone %s: addr = %p, phys = %lx, size required %d,"
+ "size created %ld",
+ inter_buff_mz_name, mz_start, mz_start_phys,
+ full_size, memzone->len);
+
+ array_of_pointers = (struct array_of_ptrs *)mz_start;
+ for (i = 0; i < num_im_sgls; i++) {
+ uint32_t curr_sgl_offset =
+ offset_of_sgls + i * sizeof(struct qat_inter_sgl);
+ struct qat_inter_sgl *sgl =
+ (struct qat_inter_sgl *)(mz_start + curr_sgl_offset);
+ array_of_pointers->pointer[i] = mz_start_phys + curr_sgl_offset;
+
+ sgl->num_bufs = QAT_NUM_BUFS_IN_IM_SGL;
+ sgl->num_mapped_bufs = 0;
+ sgl->resrvd = 0;
+ sgl->buffers[0].addr = mz_start_phys + offset_of_flat_buffs +
+ ((i * QAT_NUM_BUFS_IN_IM_SGL) * buff_size);
+ sgl->buffers[0].len = buff_size;
+ sgl->buffers[0].resrvd = 0;
+ sgl->buffers[1].addr = mz_start_phys + offset_of_flat_buffs +
+ (((i * QAT_NUM_BUFS_IN_IM_SGL) + 1) * buff_size);
+ sgl->buffers[1].len = buff_size;
+ sgl->buffers[1].resrvd = 0;
+
+#if QAT_IM_BUFFER_DEBUG
+ QAT_LOG(DEBUG, " : phys addr of sgl[%i] in array_of_pointers"
+ "= %lx", i, array_of_pointers->pointer[i]);
+ QAT_LOG(DEBUG, " : virt address of sgl[%i] = %p", i, sgl);
+ QAT_LOG(DEBUG, " : sgl->buffers[0].addr = %lx, len=%d",
+ sgl->buffers[0].addr, sgl->buffers[0].len);
+ QAT_LOG(DEBUG, " : sgl->buffers[1].addr = %lx, len=%d",
+ sgl->buffers[1].addr, sgl->buffers[1].len);
+#endif
+ }
+#if QAT_IM_BUFFER_DEBUG
+ QAT_DP_HEXDUMP_LOG(DEBUG, "IM buffer memzone start:",
+ mz_start, offset_of_flat_buffs + 32);
+#endif
+ return memzone;
+}
+
static struct rte_mempool *
qat_comp_create_xform_pool(struct qat_comp_dev_private *comp_dev,
uint32_t num_elements)
@@ -176,6 +274,12 @@ qat_comp_create_xform_pool(struct qat_comp_dev_private *comp_dev,
static void
_qat_comp_dev_config_clear(struct qat_comp_dev_private *comp_dev)
{
+ /* Free intermediate buffers */
+ if (comp_dev->interm_buff_mz) {
+ rte_memzone_free(comp_dev->interm_buff_mz);
+ comp_dev->interm_buff_mz = NULL;
+ }
+
/* Free private_xform pool */
if (comp_dev->xformpool) {
/* Free internal mempool for private xforms */
@@ -197,6 +301,21 @@ qat_comp_dev_config(struct rte_compressdev *dev,
return -EINVAL;
}
+ if (RTE_PMD_QAT_COMP_IM_BUFFER_SIZE == 0) {
+ QAT_LOG(WARNING,
+ "RTE_PMD_QAT_COMP_IM_BUFFER_SIZE = 0 in config file, so"
+ " QAT device can't be used for Dynamic Deflate. "
+ "Did you really intend to do this?");
+ } else {
+ comp_dev->interm_buff_mz =
+ qat_comp_setup_inter_buffers(comp_dev,
+ RTE_PMD_QAT_COMP_IM_BUFFER_SIZE);
+ if (comp_dev->interm_buff_mz == NULL) {
+ ret = -ENOMEM;
+ goto error_out;
+ }
+ }
+
comp_dev->xformpool = qat_comp_create_xform_pool(comp_dev,
config->max_nb_priv_xforms);
if (comp_dev->xformpool == NULL) {
@@ -365,6 +484,10 @@ qat_comp_dev_create(struct qat_pci_device *qat_pci_dev)
QAT_LOG(ERR, "Compression PMD not supported on QAT dh895xcc");
return 0;
}
+ if (qat_pci_dev->qat_dev_gen == QAT_GEN3) {
+ QAT_LOG(ERR, "Compression PMD not supported on QAT c4xxx");
+ return 0;
+ }
struct rte_compressdev_pmd_init_params init_params = {
.name = "",
--
2.7.4
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [dpdk-dev] [PATCH v5] compress/qat: enable dynamic huffman encoding
2018-10-17 20:48 ` [dpdk-dev] [PATCH v5] " Fiona Trahe
@ 2018-10-24 14:15 ` Akhil Goyal
2018-10-24 21:30 ` Thomas Monjalon
2018-10-25 1:30 ` [dpdk-dev] [PATCH v6] " Fiona Trahe
1 sibling, 1 reply; 17+ messages in thread
From: Akhil Goyal @ 2018-10-24 14:15 UTC (permalink / raw)
To: Fiona Trahe, dev; +Cc: tomaszx.jozwiak, arkadiuszx.kusztal
On 10/18/2018 2:18 AM, Fiona Trahe wrote:
> Enable dynamic huffman encoding in the QAT comp PMD.
>
> Signed-off-by: Tomasz Jozwiak<tomaszx.jozwiak@intel.com>
> Signed-off-by: Fiona Trahe<fiona.trahe@intel.com>
> Acked-by: Arek Kusztal<arkadiuszx.kusztal@intel.com>
> ---
Applied to dpdk-next-crypto
Thanks
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [dpdk-dev] [PATCH v5] compress/qat: enable dynamic huffman encoding
2018-10-24 14:15 ` Akhil Goyal
@ 2018-10-24 21:30 ` Thomas Monjalon
2018-10-25 0:40 ` Trahe, Fiona
0 siblings, 1 reply; 17+ messages in thread
From: Thomas Monjalon @ 2018-10-24 21:30 UTC (permalink / raw)
To: Fiona Trahe; +Cc: dev, Akhil Goyal, tomaszx.jozwiak, arkadiuszx.kusztal
24/10/2018 16:15, Akhil Goyal:
>
> On 10/18/2018 2:18 AM, Fiona Trahe wrote:
> > Enable dynamic huffman encoding in the QAT comp PMD.
> >
> > Signed-off-by: Tomasz Jozwiak<tomaszx.jozwiak@intel.com>
> > Signed-off-by: Fiona Trahe<fiona.trahe@intel.com>
> > Acked-by: Arek Kusztal<arkadiuszx.kusztal@intel.com>
> > ---
> Applied to dpdk-next-crypto
error: format ‘%lx’ expects argument of type ‘long unsigned int’, but argument 7 has type ‘phys_addr_t’ {aka ‘long long unsigned int’} [-Werror=format=]
"%s(): " fmt "\n", __func__, ## args)
^~~~~~~~
drivers/compress/qat/qat_comp_pmd.c:194:2: note: in expansion of macro ‘QAT_LOG’
QAT_LOG(DEBUG, "Memzone %s: addr = %p, phys = %lx, size required %d,"
One more comment about the release notes, please try to integrate
compressdev features between cryptodev and eventdev.
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [dpdk-dev] [PATCH v5] compress/qat: enable dynamic huffman encoding
2018-10-24 21:30 ` Thomas Monjalon
@ 2018-10-25 0:40 ` Trahe, Fiona
2018-10-25 6:45 ` Thomas Monjalon
0 siblings, 1 reply; 17+ messages in thread
From: Trahe, Fiona @ 2018-10-25 0:40 UTC (permalink / raw)
To: Thomas Monjalon
Cc: dev, Akhil Goyal, Jozwiak, TomaszX, Kusztal, ArkadiuszX, Trahe, Fiona
I'll send a v6.
On which OS/compiler did this fail to compile?
> -----Original Message-----
> From: Thomas Monjalon [mailto:thomas@monjalon.net]
> Sent: Wednesday, October 24, 2018 2:30 PM
> To: Trahe, Fiona <fiona.trahe@intel.com>
> Cc: dev@dpdk.org; Akhil Goyal <akhil.goyal@nxp.com>; Jozwiak, TomaszX <tomaszx.jozwiak@intel.com>;
> Kusztal, ArkadiuszX <arkadiuszx.kusztal@intel.com>
> Subject: Re: [dpdk-dev] [PATCH v5] compress/qat: enable dynamic huffman encoding
>
> 24/10/2018 16:15, Akhil Goyal:
> >
> > On 10/18/2018 2:18 AM, Fiona Trahe wrote:
> > > Enable dynamic huffman encoding in the QAT comp PMD.
> > >
> > > Signed-off-by: Tomasz Jozwiak<tomaszx.jozwiak@intel.com>
> > > Signed-off-by: Fiona Trahe<fiona.trahe@intel.com>
> > > Acked-by: Arek Kusztal<arkadiuszx.kusztal@intel.com>
> > > ---
> > Applied to dpdk-next-crypto
>
> error: format ‘%lx’ expects argument of type ‘long unsigned int’, but argument 7 has type ‘phys_addr_t’
> {aka ‘long long unsigned int’} [-Werror=format=]
> "%s(): " fmt "\n", __func__, ## args)
> ^~~~~~~~
> drivers/compress/qat/qat_comp_pmd.c:194:2: note: in expansion of macro ‘QAT_LOG’
> QAT_LOG(DEBUG, "Memzone %s: addr = %p, phys = %lx, size required %d,"
>
>
> One more comment about the release notes, please try to integrate
> compressdev features between cryptodev and eventdev.
>
^ permalink raw reply [flat|nested] 17+ messages in thread
* [dpdk-dev] [PATCH v6] compress/qat: enable dynamic huffman encoding
2018-10-17 20:48 ` [dpdk-dev] [PATCH v5] " Fiona Trahe
2018-10-24 14:15 ` Akhil Goyal
@ 2018-10-25 1:30 ` Fiona Trahe
2018-10-25 7:34 ` Akhil Goyal
2018-10-26 18:18 ` [dpdk-dev] [PATCH v7] " Fiona Trahe
1 sibling, 2 replies; 17+ messages in thread
From: Fiona Trahe @ 2018-10-25 1:30 UTC (permalink / raw)
To: dev; +Cc: thomas, akhil.goyal, tomaszx.jozwiak, arkadiuszx.kusztal, Fiona Trahe
Enable dynamic huffman encoding in the QAT comp PMD.
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Acked-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
---
v6 changes:
- replace %lx with PRIx64 to fix compiler issue
- reorder entry in release notes so above eventdev items
v5 changes:
- update release note
v4 changes:
- use #define for IM buffer logs, disable all by default
and use param for clearer hexdump length.
v3 changes:
- reverted to 1 buffer per intermediate buffer sgl
v2 changes:
- allocate 2 buffers per intermediate buffer sgl
- Compile out trace for debugging intermediate buffers
config/common_base | 1 +
config/rte_config.h | 1 +
doc/guides/compressdevs/features/qat.ini | 1 +
doc/guides/compressdevs/qat_comp.rst | 7 +-
doc/guides/rel_notes/release_18_11.rst | 5 ++
drivers/common/qat/qat_device.c | 4 +
drivers/common/qat/qat_device.h | 7 ++
drivers/compress/qat/qat_comp.c | 39 +++++++---
drivers/compress/qat/qat_comp.h | 13 ++++
drivers/compress/qat/qat_comp_pmd.c | 125 ++++++++++++++++++++++++++++++-
10 files changed, 186 insertions(+), 17 deletions(-)
diff --git a/config/common_base b/config/common_base
index be7365e..a40c61f 100644
--- a/config/common_base
+++ b/config/common_base
@@ -532,6 +532,7 @@ CONFIG_RTE_LIBRTE_PMD_QAT_SYM=n
#
CONFIG_RTE_PMD_QAT_MAX_PCI_DEVICES=48
CONFIG_RTE_PMD_QAT_COMP_SGL_MAX_SEGMENTS=16
+CONFIG_RTE_PMD_QAT_COMP_IM_BUFFER_SIZE=65536
#
# Compile PMD for virtio crypto devices
diff --git a/config/rte_config.h b/config/rte_config.h
index 816e6f8..333fb0b 100644
--- a/config/rte_config.h
+++ b/config/rte_config.h
@@ -95,6 +95,7 @@
/* Max. number of QuickAssist devices which can be attached */
#define RTE_PMD_QAT_MAX_PCI_DEVICES 48
#define RTE_PMD_QAT_COMP_SGL_MAX_SEGMENTS 16
+#define RTE_PMD_QAT_COMP_IM_BUFFER_SIZE 65536
/* virtio crypto defines */
#define RTE_MAX_VIRTIO_CRYPTO 32
diff --git a/doc/guides/compressdevs/features/qat.ini b/doc/guides/compressdevs/features/qat.ini
index 5cd4524..6b1e7f9 100644
--- a/doc/guides/compressdevs/features/qat.ini
+++ b/doc/guides/compressdevs/features/qat.ini
@@ -13,3 +13,4 @@ Adler32 = Y
Crc32 = Y
Adler32&Crc32 = Y
Fixed = Y
+Dynamic = Y
diff --git a/doc/guides/compressdevs/qat_comp.rst b/doc/guides/compressdevs/qat_comp.rst
index 7bffbe6..aee3b99 100644
--- a/doc/guides/compressdevs/qat_comp.rst
+++ b/doc/guides/compressdevs/qat_comp.rst
@@ -18,11 +18,7 @@ QAT compression PMD has support for:
Compression/Decompression algorithm:
- * DEFLATE
-
-Huffman code type:
-
- * FIXED
+ * DEFLATE - using Fixed and Dynamic Huffman encoding
Window size support:
@@ -36,7 +32,6 @@ Limitations
-----------
* Compressdev level 0, no compression, is not supported.
-* Dynamic Huffman encoding is not yet supported.
* Queue pairs are not thread-safe (that is, within a single queue pair, RX and TX from different lcores is not supported).
* No BSD support as BSD QAT kernel driver not available.
diff --git a/doc/guides/rel_notes/release_18_11.rst b/doc/guides/rel_notes/release_18_11.rst
index 04f3745..2476cea 100644
--- a/doc/guides/rel_notes/release_18_11.rst
+++ b/doc/guides/rel_notes/release_18_11.rst
@@ -166,6 +166,11 @@ New Features
Added the new caam job ring driver for NXP platforms. See the
"NXP CAAM JOB RING (caam_jr)" document for more details on this new driver.
+* **Added support for Dynamic Huffman Encoding to Intel QAT comp PMD.**
+
+ The Intel QuickAssist (QAT) compression PMD has been updated with support
+ for Dynamic Huffman Encoding for the Deflate algorithm.
+
* **Added Event Ethernet Tx Adapter.**
Added event ethernet Tx adapter library that provides configuration and
diff --git a/drivers/common/qat/qat_device.c b/drivers/common/qat/qat_device.c
index 8d4df92..5df831f 100644
--- a/drivers/common/qat/qat_device.c
+++ b/drivers/common/qat/qat_device.c
@@ -7,6 +7,7 @@
#include "qat_device.h"
#include "adf_transport_access_macros.h"
#include "qat_sym_pmd.h"
+#include "qat_comp_pmd.h"
/* Hardware device information per generation */
__extension__
@@ -14,15 +15,18 @@ struct qat_gen_hw_data qat_gen_config[] = {
[QAT_GEN1] = {
.dev_gen = QAT_GEN1,
.qp_hw_data = qat_gen1_qps,
+ .comp_num_im_bufs_required = QAT_NUM_INTERM_BUFS_GEN1
},
[QAT_GEN2] = {
.dev_gen = QAT_GEN2,
.qp_hw_data = qat_gen1_qps,
/* gen2 has same ring layout as gen1 */
+ .comp_num_im_bufs_required = QAT_NUM_INTERM_BUFS_GEN2
},
[QAT_GEN3] = {
.dev_gen = QAT_GEN3,
.qp_hw_data = qat_gen3_qps,
+ .comp_num_im_bufs_required = QAT_NUM_INTERM_BUFS_GEN3
},
};
diff --git a/drivers/common/qat/qat_device.h b/drivers/common/qat/qat_device.h
index 3a71cd4..eb81c78 100644
--- a/drivers/common/qat/qat_device.h
+++ b/drivers/common/qat/qat_device.h
@@ -16,6 +16,12 @@
#define QAT_DEV_NAME_MAX_LEN 64
+enum qat_comp_num_im_buffers {
+ QAT_NUM_INTERM_BUFS_GEN1 = 12,
+ QAT_NUM_INTERM_BUFS_GEN2 = 20,
+ QAT_NUM_INTERM_BUFS_GEN3 = 20
+};
+
/*
* This struct holds all the data about a QAT pci device
* including data about all services it supports.
@@ -72,6 +78,7 @@ struct qat_pci_device {
struct qat_gen_hw_data {
enum qat_device_gen dev_gen;
const struct qat_qp_hw_data (*qp_hw_data)[ADF_MAX_QPS_ON_ANY_SERVICE];
+ enum qat_comp_num_im_buffers comp_num_im_bufs_required;
};
extern struct qat_gen_hw_data qat_gen_config[];
diff --git a/drivers/compress/qat/qat_comp.c b/drivers/compress/qat/qat_comp.c
index b9336f3..d70c594 100644
--- a/drivers/compress/qat/qat_comp.c
+++ b/drivers/compress/qat/qat_comp.c
@@ -192,7 +192,7 @@ static void qat_comp_create_req_hdr(struct icp_qat_fw_comn_req_hdr *header,
}
static int qat_comp_create_templates(struct qat_comp_xform *qat_xform,
- const struct rte_memzone *interm_buff_mz __rte_unused,
+ const struct rte_memzone *interm_buff_mz,
const struct rte_comp_xform *xform)
{
struct icp_qat_fw_comp_req *comp_req;
@@ -280,10 +280,20 @@ static int qat_comp_create_templates(struct qat_comp_xform *qat_xform,
ICP_QAT_FW_COMN_CURR_ID_SET(&comp_req->comp_cd_ctrl,
ICP_QAT_FW_SLICE_COMP);
} else if (qat_xform->qat_comp_request_type ==
- QAT_COMP_REQUEST_DYNAMIC_COMP_STATELESS) {
+ QAT_COMP_REQUEST_DYNAMIC_COMP_STATELESS) {
- QAT_LOG(ERR, "Dynamic huffman encoding not supported");
- return -EINVAL;
+ ICP_QAT_FW_COMN_NEXT_ID_SET(&comp_req->comp_cd_ctrl,
+ ICP_QAT_FW_SLICE_XLAT);
+ ICP_QAT_FW_COMN_CURR_ID_SET(&comp_req->comp_cd_ctrl,
+ ICP_QAT_FW_SLICE_COMP);
+
+ ICP_QAT_FW_COMN_NEXT_ID_SET(&comp_req->u2.xlt_cd_ctrl,
+ ICP_QAT_FW_SLICE_DRAM_WR);
+ ICP_QAT_FW_COMN_CURR_ID_SET(&comp_req->u2.xlt_cd_ctrl,
+ ICP_QAT_FW_SLICE_XLAT);
+
+ comp_req->u1.xlt_pars.inter_buff_ptr =
+ interm_buff_mz->phys_addr;
}
#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
@@ -334,12 +344,6 @@ qat_comp_private_xform_create(struct rte_compressdev *dev,
(struct qat_comp_xform *)*private_xform;
if (xform->type == RTE_COMP_COMPRESS) {
- if (xform->compress.deflate.huffman ==
- RTE_COMP_HUFFMAN_DYNAMIC) {
- QAT_LOG(ERR,
- "QAT device doesn't support dynamic compression");
- return -ENOTSUP;
- }
if (xform->compress.deflate.huffman == RTE_COMP_HUFFMAN_FIXED ||
((xform->compress.deflate.huffman == RTE_COMP_HUFFMAN_DEFAULT)
@@ -347,6 +351,21 @@ qat_comp_private_xform_create(struct rte_compressdev *dev,
qat_xform->qat_comp_request_type =
QAT_COMP_REQUEST_FIXED_COMP_STATELESS;
+ else if ((xform->compress.deflate.huffman ==
+ RTE_COMP_HUFFMAN_DYNAMIC ||
+ xform->compress.deflate.huffman ==
+ RTE_COMP_HUFFMAN_DEFAULT) &&
+ qat->interm_buff_mz != NULL)
+
+ qat_xform->qat_comp_request_type =
+ QAT_COMP_REQUEST_DYNAMIC_COMP_STATELESS;
+
+ else {
+ QAT_LOG(ERR,
+ "IM buffers needed for dynamic deflate. Set size in config file");
+ return -EINVAL;
+ }
+
qat_xform->checksum_type = xform->compress.chksum;
} else {
diff --git a/drivers/compress/qat/qat_comp.h b/drivers/compress/qat/qat_comp.h
index 8d315ef..99a4462 100644
--- a/drivers/compress/qat/qat_comp.h
+++ b/drivers/compress/qat/qat_comp.h
@@ -15,6 +15,10 @@
#include "icp_qat_fw_comp.h"
#include "icp_qat_fw_la.h"
+#define QAT_64_BYTE_ALIGN_MASK (~0x3f)
+#define QAT_64_BYTE_ALIGN (64)
+#define QAT_NUM_BUFS_IN_IM_SGL 1
+
#define ERR_CODE_QAT_COMP_WRONG_FW -99
enum qat_comp_request_type {
@@ -24,6 +28,15 @@ enum qat_comp_request_type {
REQ_COMP_END
};
+struct array_of_ptrs {
+ phys_addr_t pointer[0];
+};
+
+struct qat_inter_sgl {
+ qat_sgl_hdr;
+ struct qat_flat_buf buffers[QAT_NUM_BUFS_IN_IM_SGL];
+} __rte_packed __rte_cache_aligned;
+
struct qat_comp_sgl {
qat_sgl_hdr;
struct qat_flat_buf buffers[RTE_PMD_QAT_COMP_SGL_MAX_SEGMENTS];
diff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c
index 63af23a..2c6aea5 100644
--- a/drivers/compress/qat/qat_comp_pmd.c
+++ b/drivers/compress/qat/qat_comp_pmd.c
@@ -14,6 +14,7 @@ static const struct rte_compressdev_capabilities qat_comp_gen_capabilities[] = {
RTE_COMP_FF_CRC32_ADLER32_CHECKSUM |
RTE_COMP_FF_SHAREABLE_PRIV_XFORM |
RTE_COMP_FF_HUFFMAN_FIXED |
+ RTE_COMP_FF_HUFFMAN_DYNAMIC |
RTE_COMP_FF_OOP_SGL_IN_SGL_OUT |
RTE_COMP_FF_OOP_SGL_IN_LB_OUT |
RTE_COMP_FF_OOP_LB_IN_SGL_OUT,
@@ -112,7 +113,7 @@ qat_comp_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,
/* store a link to the qp in the qat_pci_device */
qat_private->qat_dev->qps_in_use[QAT_SERVICE_COMPRESSION][qp_id]
- = *qp_addr;
+ = *qp_addr;
qp = (struct qat_qp *)*qp_addr;
@@ -135,6 +136,103 @@ qat_comp_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,
return ret;
}
+
+#define QAT_IM_BUFFER_DEBUG 0
+static const struct rte_memzone *
+qat_comp_setup_inter_buffers(struct qat_comp_dev_private *comp_dev,
+ uint32_t buff_size)
+{
+ char inter_buff_mz_name[RTE_MEMZONE_NAMESIZE];
+ const struct rte_memzone *memzone;
+ uint8_t *mz_start = NULL;
+ phys_addr_t mz_start_phys = 0;
+ struct array_of_ptrs *array_of_pointers;
+ int size_of_ptr_array;
+ uint32_t full_size;
+ uint32_t offset_of_sgls, offset_of_flat_buffs = 0;
+ int i;
+ int num_im_sgls = qat_gen_config[
+ comp_dev->qat_dev->qat_dev_gen].comp_num_im_bufs_required;
+
+ QAT_LOG(DEBUG, "QAT COMP device %s needs %d sgls",
+ comp_dev->qat_dev->name, num_im_sgls);
+ snprintf(inter_buff_mz_name, RTE_MEMZONE_NAMESIZE,
+ "%s_inter_buff", comp_dev->qat_dev->name);
+ memzone = rte_memzone_lookup(inter_buff_mz_name);
+ if (memzone != NULL) {
+ QAT_LOG(DEBUG, "QAT COMP im buffer memzone created already");
+ return memzone;
+ }
+
+ /* Create a memzone to hold intermediate buffers and associated
+ * meta-data needed by the firmware. The memzone contains:
+ * - a list of num_im_sgls physical pointers to sgls
+ * - the num_im_sgl sgl structures, each pointing to 2 flat buffers
+ * - the flat buffers: num_im_sgl * 2
+ * where num_im_sgls depends on the hardware generation of the device
+ */
+
+ size_of_ptr_array = num_im_sgls * sizeof(phys_addr_t);
+ offset_of_sgls = (size_of_ptr_array + (~QAT_64_BYTE_ALIGN_MASK))
+ & QAT_64_BYTE_ALIGN_MASK;
+ offset_of_flat_buffs =
+ offset_of_sgls + num_im_sgls * sizeof(struct qat_inter_sgl);
+ full_size = offset_of_flat_buffs +
+ num_im_sgls * buff_size * QAT_NUM_BUFS_IN_IM_SGL;
+
+ memzone = rte_memzone_reserve_aligned(inter_buff_mz_name, full_size,
+ comp_dev->compressdev->data->socket_id,
+ RTE_MEMZONE_2MB, QAT_64_BYTE_ALIGN);
+ if (memzone == NULL) {
+ QAT_LOG(ERR, "Can't allocate intermediate buffers"
+ " for device %s", comp_dev->qat_dev->name);
+ return NULL;
+ }
+
+ mz_start = (uint8_t *)memzone->addr;
+ mz_start_phys = memzone->phys_addr;
+ QAT_LOG(DEBUG, "Memzone %s: addr = %p, phys = 0x%"PRIx64
+ ", size required %d, size created %ld",
+ inter_buff_mz_name, mz_start, mz_start_phys,
+ full_size, memzone->len);
+
+ array_of_pointers = (struct array_of_ptrs *)mz_start;
+ for (i = 0; i < num_im_sgls; i++) {
+ uint32_t curr_sgl_offset =
+ offset_of_sgls + i * sizeof(struct qat_inter_sgl);
+ struct qat_inter_sgl *sgl =
+ (struct qat_inter_sgl *)(mz_start + curr_sgl_offset);
+ array_of_pointers->pointer[i] = mz_start_phys + curr_sgl_offset;
+
+ sgl->num_bufs = QAT_NUM_BUFS_IN_IM_SGL;
+ sgl->num_mapped_bufs = 0;
+ sgl->resrvd = 0;
+ sgl->buffers[0].addr = mz_start_phys + offset_of_flat_buffs +
+ ((i * QAT_NUM_BUFS_IN_IM_SGL) * buff_size);
+ sgl->buffers[0].len = buff_size;
+ sgl->buffers[0].resrvd = 0;
+ sgl->buffers[1].addr = mz_start_phys + offset_of_flat_buffs +
+ (((i * QAT_NUM_BUFS_IN_IM_SGL) + 1) * buff_size);
+ sgl->buffers[1].len = buff_size;
+ sgl->buffers[1].resrvd = 0;
+
+#if QAT_IM_BUFFER_DEBUG
+ QAT_LOG(DEBUG, " : phys addr of sgl[%i] in array_of_pointers"
+ "= 0x%"PRIx64, i, array_of_pointers->pointer[i]);
+ QAT_LOG(DEBUG, " : virt address of sgl[%i] = %p", i, sgl);
+ QAT_LOG(DEBUG, " : sgl->buffers[0].addr = 0x%"PRIx64", len=%d",
+ sgl->buffers[0].addr, sgl->buffers[0].len);
+ QAT_LOG(DEBUG, " : sgl->buffers[1].addr = 0x%"PRIx64", len=%d",
+ sgl->buffers[1].addr, sgl->buffers[1].len);
+#endif
+ }
+#if QAT_IM_BUFFER_DEBUG
+ QAT_DP_HEXDUMP_LOG(DEBUG, "IM buffer memzone start:",
+ mz_start, offset_of_flat_buffs + 32);
+#endif
+ return memzone;
+}
+
static struct rte_mempool *
qat_comp_create_xform_pool(struct qat_comp_dev_private *comp_dev,
uint32_t num_elements)
@@ -176,6 +274,12 @@ qat_comp_create_xform_pool(struct qat_comp_dev_private *comp_dev,
static void
_qat_comp_dev_config_clear(struct qat_comp_dev_private *comp_dev)
{
+ /* Free intermediate buffers */
+ if (comp_dev->interm_buff_mz) {
+ rte_memzone_free(comp_dev->interm_buff_mz);
+ comp_dev->interm_buff_mz = NULL;
+ }
+
/* Free private_xform pool */
if (comp_dev->xformpool) {
/* Free internal mempool for private xforms */
@@ -197,6 +301,21 @@ qat_comp_dev_config(struct rte_compressdev *dev,
return -EINVAL;
}
+ if (RTE_PMD_QAT_COMP_IM_BUFFER_SIZE == 0) {
+ QAT_LOG(WARNING,
+ "RTE_PMD_QAT_COMP_IM_BUFFER_SIZE = 0 in config file, so"
+ " QAT device can't be used for Dynamic Deflate. "
+ "Did you really intend to do this?");
+ } else {
+ comp_dev->interm_buff_mz =
+ qat_comp_setup_inter_buffers(comp_dev,
+ RTE_PMD_QAT_COMP_IM_BUFFER_SIZE);
+ if (comp_dev->interm_buff_mz == NULL) {
+ ret = -ENOMEM;
+ goto error_out;
+ }
+ }
+
comp_dev->xformpool = qat_comp_create_xform_pool(comp_dev,
config->max_nb_priv_xforms);
if (comp_dev->xformpool == NULL) {
@@ -365,6 +484,10 @@ qat_comp_dev_create(struct qat_pci_device *qat_pci_dev)
QAT_LOG(ERR, "Compression PMD not supported on QAT dh895xcc");
return 0;
}
+ if (qat_pci_dev->qat_dev_gen == QAT_GEN3) {
+ QAT_LOG(ERR, "Compression PMD not supported on QAT c4xxx");
+ return 0;
+ }
struct rte_compressdev_pmd_init_params init_params = {
.name = "",
--
2.7.4
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [dpdk-dev] [PATCH v5] compress/qat: enable dynamic huffman encoding
2018-10-25 0:40 ` Trahe, Fiona
@ 2018-10-25 6:45 ` Thomas Monjalon
0 siblings, 0 replies; 17+ messages in thread
From: Thomas Monjalon @ 2018-10-25 6:45 UTC (permalink / raw)
To: Trahe, Fiona; +Cc: dev, Akhil Goyal, Jozwiak, TomaszX, Kusztal, ArkadiuszX
25/10/2018 02:40, Trahe, Fiona:
> I'll send a v6.
> On which OS/compiler did this fail to compile?
It fails on i686 of course.
I already sent some general notes in the past, explaining how %lx
is most of the time wrong. %PRIu64 is the right specifier.
https://www.mail-archive.com/dev@dpdk.org/msg90644.html
> From: Thomas Monjalon [mailto:thomas@monjalon.net]
> > 24/10/2018 16:15, Akhil Goyal:
> > >
> > > On 10/18/2018 2:18 AM, Fiona Trahe wrote:
> > > > Enable dynamic huffman encoding in the QAT comp PMD.
> > > >
> > > > Signed-off-by: Tomasz Jozwiak<tomaszx.jozwiak@intel.com>
> > > > Signed-off-by: Fiona Trahe<fiona.trahe@intel.com>
> > > > Acked-by: Arek Kusztal<arkadiuszx.kusztal@intel.com>
> > > > ---
> > > Applied to dpdk-next-crypto
> >
> > error: format ‘%lx’ expects argument of type ‘long unsigned int’, but argument 7 has type ‘phys_addr_t’
> > {aka ‘long long unsigned int’} [-Werror=format=]
> > "%s(): " fmt "\n", __func__, ## args)
> > ^~~~~~~~
> > drivers/compress/qat/qat_comp_pmd.c:194:2: note: in expansion of macro ‘QAT_LOG’
> > QAT_LOG(DEBUG, "Memzone %s: addr = %p, phys = %lx, size required %d,"
> >
> >
> > One more comment about the release notes, please try to integrate
> > compressdev features between cryptodev and eventdev.
> >
>
>
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [dpdk-dev] [PATCH v6] compress/qat: enable dynamic huffman encoding
2018-10-25 1:30 ` [dpdk-dev] [PATCH v6] " Fiona Trahe
@ 2018-10-25 7:34 ` Akhil Goyal
2018-10-26 18:18 ` [dpdk-dev] [PATCH v7] " Fiona Trahe
1 sibling, 0 replies; 17+ messages in thread
From: Akhil Goyal @ 2018-10-25 7:34 UTC (permalink / raw)
To: Fiona Trahe, dev; +Cc: thomas, tomaszx.jozwiak, arkadiuszx.kusztal
Hi Fiona,
On 10/25/2018 7:00 AM, Fiona Trahe wrote:
> Enable dynamic huffman encoding in the QAT comp PMD.
>
> Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
> Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
> Acked-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
> ---
The patch is still failing in i686 and armv7
**************** Testing i686 ***********************
In file included from
/home/b35197/dpdk/drivers/common/qat/qat_device.h:10:0,
from
/home/b35197/dpdk/drivers/compress/qat/qat_comp_pmd.h:13,
from
/home/b35197/dpdk/drivers/compress/qat/qat_comp_pmd.c:6:
/home/b35197/dpdk/drivers/compress/qat/qat_comp_pmd.c: In function
âqat_comp_setup_inter_buffersâ:
/home/b35197/dpdk/drivers/common/qat/qat_logs.h:13:4: error: format
â%ldâ expects argument of type âlong intâ, but argument 9 has type
âsize_t {aka const unsigned int}â [-Werror=format=]
"%s(): " fmt "\n", __func__, ## args)
^
/home/b35197/dpdk/drivers/compress/qat/qat_comp_pmd.c:194:2: note: in
expansion of macro âQAT_LOGâ
QAT_LOG(DEBUG, "Memzone %s: addr = %p, phys = 0x%"PRIx64
^~~~~~~
/home/b35197/dpdk/drivers/compress/qat/qat_comp_pmd.c:195:40: note:
format string is defined here
", size required %d, size created %ld",
~~^
%d
cc1: all warnings being treated as errors
make[5]: *** [qat_comp_pmd.o] Error 1
make[5]: *** Waiting for unfinished jobs....
make[4]: *** [common/qat] Error 2
make[4]: *** Waiting for unfinished jobs....
make[3]: *** [drivers] Error 2
make[2]: *** [all] Error 2
make[1]: *** [pre_install] Error 2
make: *** [install] Error 2
Error in BUILD
**************** Testing armv7 ***********************
/home/b35197/dpdk/drivers/compress/qat/qat_comp.c: In function
'qat_comp_build_request':
/home/b35197/dpdk/drivers/compress/qat/qat_comp.c:33:6: warning: cast
increases required alignment of target type [-Wcast-align]
(struct icp_qat_fw_comp_req *)out_msg;
^
/home/b35197/dpdk/drivers/compress/qat/qat_comp.c: In function
'qat_comp_process_response':
/home/b35197/dpdk/drivers/compress/qat/qat_comp.c:112:4: warning: cast
increases required alignment of target type [-Wcast-align]
(struct icp_qat_fw_comp_resp *)resp;
^
/home/b35197/dpdk/drivers/compress/qat/qat_comp.c:146:6: warning: cast
increases required alignment of target type [-Wcast-align]
*((uint16_t *)(&resp_msg->comn_resp.comn_error));
^
In file included from
/home/b35197/dpdk/drivers/common/qat/qat_device.h:10:0,
from
/home/b35197/dpdk/drivers/compress/qat/qat_comp_pmd.h:13,
from
/home/b35197/dpdk/drivers/compress/qat/qat_comp_pmd.c:6:
/home/b35197/dpdk/drivers/compress/qat/qat_comp_pmd.c: In function
'qat_comp_setup_inter_buffers':
/home/b35197/dpdk/drivers/common/qat/qat_logs.h:13:4: error: format
'%ld' expects argument of type 'long int', but argument 9 has type
'size_t {aka const unsigned int}' [-Werror=format=]
"%s(): " fmt "\n", __func__, ## args)
^
/home/b35197/dpdk/drivers/compress/qat/qat_comp_pmd.c:194:2: note: in
expansion of macro 'QAT_LOG'
QAT_LOG(DEBUG, "Memzone %s: addr = %p, phys = 0x%"PRIx64
^
/home/b35197/dpdk/drivers/compress/qat/qat_comp_pmd.c:199:22: warning:
cast increases required alignment of target type [-Wcast-align]
array_of_pointers = (struct array_of_ptrs *)mz_start;
^
/home/b35197/dpdk/drivers/compress/qat/qat_comp_pmd.c:204:7: warning:
cast increases required alignment of target type [-Wcast-align]
(struct qat_inter_sgl *)(mz_start + curr_sgl_offset);
^
cc1: all warnings being treated as errors
make[5]: *** [qat_comp_pmd.o] Error 1
make[5]: *** Waiting for unfinished jobs....
make[4]: *** [common/qat] Error 2
make[4]: *** Waiting for unfinished jobs....
make[3]: *** [drivers] Error 2
make[2]: *** [all] Error 2
make[1]: *** [pre_install] Error 2
make: *** [install] Error 2
Error in BUILD
^ permalink raw reply [flat|nested] 17+ messages in thread
* [dpdk-dev] [PATCH v7] compress/qat: enable dynamic huffman encoding
2018-10-25 1:30 ` [dpdk-dev] [PATCH v6] " Fiona Trahe
2018-10-25 7:34 ` Akhil Goyal
@ 2018-10-26 18:18 ` Fiona Trahe
2018-10-27 0:06 ` Thomas Monjalon
1 sibling, 1 reply; 17+ messages in thread
From: Fiona Trahe @ 2018-10-26 18:18 UTC (permalink / raw)
To: dev
Cc: thomas, akhil.goyal, tomaszx.jozwiak, arkadiuszx.kusztal,
ferruh.yigit, Fiona Trahe
Enable dynamic huffman encoding in the QAT comp PMD.
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Acked-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
---
v7 changes:
- replace %ld with %zu for printing size_t to fix compiler issue
- replace phys addr with rte_iova_t
v6 changes:
- replace %lx with PRIx64 to fix compiler issue
- reorder entry in release notes so above eventdev items
v5 changes:
- update release note
v4 changes:
- use #define for IM buffer logs, disable all by default
and use param for clearer hexdump length.
v3 changes:
- reverted to 1 buffer per intermediate buffer sgl
v2 changes:
- allocate 2 buffers per intermediate buffer sgl
- Compile out trace for debugging intermediate buffers
config/common_base | 1 +
config/rte_config.h | 1 +
doc/guides/compressdevs/features/qat.ini | 1 +
doc/guides/compressdevs/qat_comp.rst | 7 +-
doc/guides/rel_notes/release_18_11.rst | 5 ++
drivers/common/qat/qat_device.c | 4 +
drivers/common/qat/qat_device.h | 7 ++
drivers/compress/qat/qat_comp.c | 39 +++++++---
drivers/compress/qat/qat_comp.h | 13 ++++
drivers/compress/qat/qat_comp_pmd.c | 125 ++++++++++++++++++++++++++++++-
10 files changed, 186 insertions(+), 17 deletions(-)
diff --git a/config/common_base b/config/common_base
index be7365e..a40c61f 100644
--- a/config/common_base
+++ b/config/common_base
@@ -532,6 +532,7 @@ CONFIG_RTE_LIBRTE_PMD_QAT_SYM=n
#
CONFIG_RTE_PMD_QAT_MAX_PCI_DEVICES=48
CONFIG_RTE_PMD_QAT_COMP_SGL_MAX_SEGMENTS=16
+CONFIG_RTE_PMD_QAT_COMP_IM_BUFFER_SIZE=65536
#
# Compile PMD for virtio crypto devices
diff --git a/config/rte_config.h b/config/rte_config.h
index 816e6f8..333fb0b 100644
--- a/config/rte_config.h
+++ b/config/rte_config.h
@@ -95,6 +95,7 @@
/* Max. number of QuickAssist devices which can be attached */
#define RTE_PMD_QAT_MAX_PCI_DEVICES 48
#define RTE_PMD_QAT_COMP_SGL_MAX_SEGMENTS 16
+#define RTE_PMD_QAT_COMP_IM_BUFFER_SIZE 65536
/* virtio crypto defines */
#define RTE_MAX_VIRTIO_CRYPTO 32
diff --git a/doc/guides/compressdevs/features/qat.ini b/doc/guides/compressdevs/features/qat.ini
index 5cd4524..6b1e7f9 100644
--- a/doc/guides/compressdevs/features/qat.ini
+++ b/doc/guides/compressdevs/features/qat.ini
@@ -13,3 +13,4 @@ Adler32 = Y
Crc32 = Y
Adler32&Crc32 = Y
Fixed = Y
+Dynamic = Y
diff --git a/doc/guides/compressdevs/qat_comp.rst b/doc/guides/compressdevs/qat_comp.rst
index 7bffbe6..aee3b99 100644
--- a/doc/guides/compressdevs/qat_comp.rst
+++ b/doc/guides/compressdevs/qat_comp.rst
@@ -18,11 +18,7 @@ QAT compression PMD has support for:
Compression/Decompression algorithm:
- * DEFLATE
-
-Huffman code type:
-
- * FIXED
+ * DEFLATE - using Fixed and Dynamic Huffman encoding
Window size support:
@@ -36,7 +32,6 @@ Limitations
-----------
* Compressdev level 0, no compression, is not supported.
-* Dynamic Huffman encoding is not yet supported.
* Queue pairs are not thread-safe (that is, within a single queue pair, RX and TX from different lcores is not supported).
* No BSD support as BSD QAT kernel driver not available.
diff --git a/doc/guides/rel_notes/release_18_11.rst b/doc/guides/rel_notes/release_18_11.rst
index 04f3745..2476cea 100644
--- a/doc/guides/rel_notes/release_18_11.rst
+++ b/doc/guides/rel_notes/release_18_11.rst
@@ -166,6 +166,11 @@ New Features
Added the new caam job ring driver for NXP platforms. See the
"NXP CAAM JOB RING (caam_jr)" document for more details on this new driver.
+* **Added support for Dynamic Huffman Encoding to Intel QAT comp PMD.**
+
+ The Intel QuickAssist (QAT) compression PMD has been updated with support
+ for Dynamic Huffman Encoding for the Deflate algorithm.
+
* **Added Event Ethernet Tx Adapter.**
Added event ethernet Tx adapter library that provides configuration and
diff --git a/drivers/common/qat/qat_device.c b/drivers/common/qat/qat_device.c
index 4ff8b88..2a1cf3e 100644
--- a/drivers/common/qat/qat_device.c
+++ b/drivers/common/qat/qat_device.c
@@ -7,6 +7,7 @@
#include "qat_device.h"
#include "adf_transport_access_macros.h"
#include "qat_sym_pmd.h"
+#include "qat_comp_pmd.h"
/* Hardware device information per generation */
__extension__
@@ -14,15 +15,18 @@ struct qat_gen_hw_data qat_gen_config[] = {
[QAT_GEN1] = {
.dev_gen = QAT_GEN1,
.qp_hw_data = qat_gen1_qps,
+ .comp_num_im_bufs_required = QAT_NUM_INTERM_BUFS_GEN1
},
[QAT_GEN2] = {
.dev_gen = QAT_GEN2,
.qp_hw_data = qat_gen1_qps,
/* gen2 has same ring layout as gen1 */
+ .comp_num_im_bufs_required = QAT_NUM_INTERM_BUFS_GEN2
},
[QAT_GEN3] = {
.dev_gen = QAT_GEN3,
.qp_hw_data = qat_gen3_qps,
+ .comp_num_im_bufs_required = QAT_NUM_INTERM_BUFS_GEN3
},
};
diff --git a/drivers/common/qat/qat_device.h b/drivers/common/qat/qat_device.h
index 3a71cd4..eb81c78 100644
--- a/drivers/common/qat/qat_device.h
+++ b/drivers/common/qat/qat_device.h
@@ -16,6 +16,12 @@
#define QAT_DEV_NAME_MAX_LEN 64
+enum qat_comp_num_im_buffers {
+ QAT_NUM_INTERM_BUFS_GEN1 = 12,
+ QAT_NUM_INTERM_BUFS_GEN2 = 20,
+ QAT_NUM_INTERM_BUFS_GEN3 = 20
+};
+
/*
* This struct holds all the data about a QAT pci device
* including data about all services it supports.
@@ -72,6 +78,7 @@ struct qat_pci_device {
struct qat_gen_hw_data {
enum qat_device_gen dev_gen;
const struct qat_qp_hw_data (*qp_hw_data)[ADF_MAX_QPS_ON_ANY_SERVICE];
+ enum qat_comp_num_im_buffers comp_num_im_bufs_required;
};
extern struct qat_gen_hw_data qat_gen_config[];
diff --git a/drivers/compress/qat/qat_comp.c b/drivers/compress/qat/qat_comp.c
index b9336f3..d70c594 100644
--- a/drivers/compress/qat/qat_comp.c
+++ b/drivers/compress/qat/qat_comp.c
@@ -192,7 +192,7 @@ static void qat_comp_create_req_hdr(struct icp_qat_fw_comn_req_hdr *header,
}
static int qat_comp_create_templates(struct qat_comp_xform *qat_xform,
- const struct rte_memzone *interm_buff_mz __rte_unused,
+ const struct rte_memzone *interm_buff_mz,
const struct rte_comp_xform *xform)
{
struct icp_qat_fw_comp_req *comp_req;
@@ -280,10 +280,20 @@ static int qat_comp_create_templates(struct qat_comp_xform *qat_xform,
ICP_QAT_FW_COMN_CURR_ID_SET(&comp_req->comp_cd_ctrl,
ICP_QAT_FW_SLICE_COMP);
} else if (qat_xform->qat_comp_request_type ==
- QAT_COMP_REQUEST_DYNAMIC_COMP_STATELESS) {
+ QAT_COMP_REQUEST_DYNAMIC_COMP_STATELESS) {
- QAT_LOG(ERR, "Dynamic huffman encoding not supported");
- return -EINVAL;
+ ICP_QAT_FW_COMN_NEXT_ID_SET(&comp_req->comp_cd_ctrl,
+ ICP_QAT_FW_SLICE_XLAT);
+ ICP_QAT_FW_COMN_CURR_ID_SET(&comp_req->comp_cd_ctrl,
+ ICP_QAT_FW_SLICE_COMP);
+
+ ICP_QAT_FW_COMN_NEXT_ID_SET(&comp_req->u2.xlt_cd_ctrl,
+ ICP_QAT_FW_SLICE_DRAM_WR);
+ ICP_QAT_FW_COMN_CURR_ID_SET(&comp_req->u2.xlt_cd_ctrl,
+ ICP_QAT_FW_SLICE_XLAT);
+
+ comp_req->u1.xlt_pars.inter_buff_ptr =
+ interm_buff_mz->phys_addr;
}
#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
@@ -334,12 +344,6 @@ qat_comp_private_xform_create(struct rte_compressdev *dev,
(struct qat_comp_xform *)*private_xform;
if (xform->type == RTE_COMP_COMPRESS) {
- if (xform->compress.deflate.huffman ==
- RTE_COMP_HUFFMAN_DYNAMIC) {
- QAT_LOG(ERR,
- "QAT device doesn't support dynamic compression");
- return -ENOTSUP;
- }
if (xform->compress.deflate.huffman == RTE_COMP_HUFFMAN_FIXED ||
((xform->compress.deflate.huffman == RTE_COMP_HUFFMAN_DEFAULT)
@@ -347,6 +351,21 @@ qat_comp_private_xform_create(struct rte_compressdev *dev,
qat_xform->qat_comp_request_type =
QAT_COMP_REQUEST_FIXED_COMP_STATELESS;
+ else if ((xform->compress.deflate.huffman ==
+ RTE_COMP_HUFFMAN_DYNAMIC ||
+ xform->compress.deflate.huffman ==
+ RTE_COMP_HUFFMAN_DEFAULT) &&
+ qat->interm_buff_mz != NULL)
+
+ qat_xform->qat_comp_request_type =
+ QAT_COMP_REQUEST_DYNAMIC_COMP_STATELESS;
+
+ else {
+ QAT_LOG(ERR,
+ "IM buffers needed for dynamic deflate. Set size in config file");
+ return -EINVAL;
+ }
+
qat_xform->checksum_type = xform->compress.chksum;
} else {
diff --git a/drivers/compress/qat/qat_comp.h b/drivers/compress/qat/qat_comp.h
index 8d315ef..99a4462 100644
--- a/drivers/compress/qat/qat_comp.h
+++ b/drivers/compress/qat/qat_comp.h
@@ -15,6 +15,10 @@
#include "icp_qat_fw_comp.h"
#include "icp_qat_fw_la.h"
+#define QAT_64_BYTE_ALIGN_MASK (~0x3f)
+#define QAT_64_BYTE_ALIGN (64)
+#define QAT_NUM_BUFS_IN_IM_SGL 1
+
#define ERR_CODE_QAT_COMP_WRONG_FW -99
enum qat_comp_request_type {
@@ -24,6 +28,15 @@ enum qat_comp_request_type {
REQ_COMP_END
};
+struct array_of_ptrs {
+ phys_addr_t pointer[0];
+};
+
+struct qat_inter_sgl {
+ qat_sgl_hdr;
+ struct qat_flat_buf buffers[QAT_NUM_BUFS_IN_IM_SGL];
+} __rte_packed __rte_cache_aligned;
+
struct qat_comp_sgl {
qat_sgl_hdr;
struct qat_flat_buf buffers[RTE_PMD_QAT_COMP_SGL_MAX_SEGMENTS];
diff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c
index 63af23a..01dd736 100644
--- a/drivers/compress/qat/qat_comp_pmd.c
+++ b/drivers/compress/qat/qat_comp_pmd.c
@@ -14,6 +14,7 @@ static const struct rte_compressdev_capabilities qat_comp_gen_capabilities[] = {
RTE_COMP_FF_CRC32_ADLER32_CHECKSUM |
RTE_COMP_FF_SHAREABLE_PRIV_XFORM |
RTE_COMP_FF_HUFFMAN_FIXED |
+ RTE_COMP_FF_HUFFMAN_DYNAMIC |
RTE_COMP_FF_OOP_SGL_IN_SGL_OUT |
RTE_COMP_FF_OOP_SGL_IN_LB_OUT |
RTE_COMP_FF_OOP_LB_IN_SGL_OUT,
@@ -112,7 +113,7 @@ qat_comp_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,
/* store a link to the qp in the qat_pci_device */
qat_private->qat_dev->qps_in_use[QAT_SERVICE_COMPRESSION][qp_id]
- = *qp_addr;
+ = *qp_addr;
qp = (struct qat_qp *)*qp_addr;
@@ -135,6 +136,103 @@ qat_comp_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,
return ret;
}
+
+#define QAT_IM_BUFFER_DEBUG 0
+static const struct rte_memzone *
+qat_comp_setup_inter_buffers(struct qat_comp_dev_private *comp_dev,
+ uint32_t buff_size)
+{
+ char inter_buff_mz_name[RTE_MEMZONE_NAMESIZE];
+ const struct rte_memzone *memzone;
+ uint8_t *mz_start = NULL;
+ rte_iova_t mz_start_phys = 0;
+ struct array_of_ptrs *array_of_pointers;
+ int size_of_ptr_array;
+ uint32_t full_size;
+ uint32_t offset_of_sgls, offset_of_flat_buffs = 0;
+ int i;
+ int num_im_sgls = qat_gen_config[
+ comp_dev->qat_dev->qat_dev_gen].comp_num_im_bufs_required;
+
+ QAT_LOG(DEBUG, "QAT COMP device %s needs %d sgls",
+ comp_dev->qat_dev->name, num_im_sgls);
+ snprintf(inter_buff_mz_name, RTE_MEMZONE_NAMESIZE,
+ "%s_inter_buff", comp_dev->qat_dev->name);
+ memzone = rte_memzone_lookup(inter_buff_mz_name);
+ if (memzone != NULL) {
+ QAT_LOG(DEBUG, "QAT COMP im buffer memzone created already");
+ return memzone;
+ }
+
+ /* Create a memzone to hold intermediate buffers and associated
+ * meta-data needed by the firmware. The memzone contains:
+ * - a list of num_im_sgls physical pointers to sgls
+ * - the num_im_sgl sgl structures, each pointing to 2 flat buffers
+ * - the flat buffers: num_im_sgl * 2
+ * where num_im_sgls depends on the hardware generation of the device
+ */
+
+ size_of_ptr_array = num_im_sgls * sizeof(phys_addr_t);
+ offset_of_sgls = (size_of_ptr_array + (~QAT_64_BYTE_ALIGN_MASK))
+ & QAT_64_BYTE_ALIGN_MASK;
+ offset_of_flat_buffs =
+ offset_of_sgls + num_im_sgls * sizeof(struct qat_inter_sgl);
+ full_size = offset_of_flat_buffs +
+ num_im_sgls * buff_size * QAT_NUM_BUFS_IN_IM_SGL;
+
+ memzone = rte_memzone_reserve_aligned(inter_buff_mz_name, full_size,
+ comp_dev->compressdev->data->socket_id,
+ RTE_MEMZONE_2MB, QAT_64_BYTE_ALIGN);
+ if (memzone == NULL) {
+ QAT_LOG(ERR, "Can't allocate intermediate buffers"
+ " for device %s", comp_dev->qat_dev->name);
+ return NULL;
+ }
+
+ mz_start = (uint8_t *)memzone->addr;
+ mz_start_phys = memzone->phys_addr;
+ QAT_LOG(DEBUG, "Memzone %s: addr = %p, phys = 0x%"PRIx64
+ ", size required %d, size created %zu",
+ inter_buff_mz_name, mz_start, mz_start_phys,
+ full_size, memzone->len);
+
+ array_of_pointers = (struct array_of_ptrs *)mz_start;
+ for (i = 0; i < num_im_sgls; i++) {
+ uint32_t curr_sgl_offset =
+ offset_of_sgls + i * sizeof(struct qat_inter_sgl);
+ struct qat_inter_sgl *sgl =
+ (struct qat_inter_sgl *)(mz_start + curr_sgl_offset);
+ array_of_pointers->pointer[i] = mz_start_phys + curr_sgl_offset;
+
+ sgl->num_bufs = QAT_NUM_BUFS_IN_IM_SGL;
+ sgl->num_mapped_bufs = 0;
+ sgl->resrvd = 0;
+ sgl->buffers[0].addr = mz_start_phys + offset_of_flat_buffs +
+ ((i * QAT_NUM_BUFS_IN_IM_SGL) * buff_size);
+ sgl->buffers[0].len = buff_size;
+ sgl->buffers[0].resrvd = 0;
+ sgl->buffers[1].addr = mz_start_phys + offset_of_flat_buffs +
+ (((i * QAT_NUM_BUFS_IN_IM_SGL) + 1) * buff_size);
+ sgl->buffers[1].len = buff_size;
+ sgl->buffers[1].resrvd = 0;
+
+#if QAT_IM_BUFFER_DEBUG
+ QAT_LOG(DEBUG, " : phys addr of sgl[%i] in array_of_pointers"
+ "= 0x%"PRIx64, i, array_of_pointers->pointer[i]);
+ QAT_LOG(DEBUG, " : virt address of sgl[%i] = %p", i, sgl);
+ QAT_LOG(DEBUG, " : sgl->buffers[0].addr = 0x%"PRIx64", len=%d",
+ sgl->buffers[0].addr, sgl->buffers[0].len);
+ QAT_LOG(DEBUG, " : sgl->buffers[1].addr = 0x%"PRIx64", len=%d",
+ sgl->buffers[1].addr, sgl->buffers[1].len);
+#endif
+ }
+#if QAT_IM_BUFFER_DEBUG
+ QAT_DP_HEXDUMP_LOG(DEBUG, "IM buffer memzone start:",
+ mz_start, offset_of_flat_buffs + 32);
+#endif
+ return memzone;
+}
+
static struct rte_mempool *
qat_comp_create_xform_pool(struct qat_comp_dev_private *comp_dev,
uint32_t num_elements)
@@ -176,6 +274,12 @@ qat_comp_create_xform_pool(struct qat_comp_dev_private *comp_dev,
static void
_qat_comp_dev_config_clear(struct qat_comp_dev_private *comp_dev)
{
+ /* Free intermediate buffers */
+ if (comp_dev->interm_buff_mz) {
+ rte_memzone_free(comp_dev->interm_buff_mz);
+ comp_dev->interm_buff_mz = NULL;
+ }
+
/* Free private_xform pool */
if (comp_dev->xformpool) {
/* Free internal mempool for private xforms */
@@ -197,6 +301,21 @@ qat_comp_dev_config(struct rte_compressdev *dev,
return -EINVAL;
}
+ if (RTE_PMD_QAT_COMP_IM_BUFFER_SIZE == 0) {
+ QAT_LOG(WARNING,
+ "RTE_PMD_QAT_COMP_IM_BUFFER_SIZE = 0 in config file, so"
+ " QAT device can't be used for Dynamic Deflate. "
+ "Did you really intend to do this?");
+ } else {
+ comp_dev->interm_buff_mz =
+ qat_comp_setup_inter_buffers(comp_dev,
+ RTE_PMD_QAT_COMP_IM_BUFFER_SIZE);
+ if (comp_dev->interm_buff_mz == NULL) {
+ ret = -ENOMEM;
+ goto error_out;
+ }
+ }
+
comp_dev->xformpool = qat_comp_create_xform_pool(comp_dev,
config->max_nb_priv_xforms);
if (comp_dev->xformpool == NULL) {
@@ -365,6 +484,10 @@ qat_comp_dev_create(struct qat_pci_device *qat_pci_dev)
QAT_LOG(ERR, "Compression PMD not supported on QAT dh895xcc");
return 0;
}
+ if (qat_pci_dev->qat_dev_gen == QAT_GEN3) {
+ QAT_LOG(ERR, "Compression PMD not supported on QAT c4xxx");
+ return 0;
+ }
struct rte_compressdev_pmd_init_params init_params = {
.name = "",
--
2.7.4
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [dpdk-dev] [PATCH v7] compress/qat: enable dynamic huffman encoding
2018-10-26 18:18 ` [dpdk-dev] [PATCH v7] " Fiona Trahe
@ 2018-10-27 0:06 ` Thomas Monjalon
0 siblings, 0 replies; 17+ messages in thread
From: Thomas Monjalon @ 2018-10-27 0:06 UTC (permalink / raw)
To: Fiona Trahe
Cc: dev, akhil.goyal, tomaszx.jozwiak, arkadiuszx.kusztal, ferruh.yigit
26/10/2018 20:18, Fiona Trahe:
> Enable dynamic huffman encoding in the QAT comp PMD.
>
> Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
> Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
> Acked-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
Applied, thanks
^ permalink raw reply [flat|nested] 17+ messages in thread
end of thread, other threads:[~2018-10-27 0:06 UTC | newest]
Thread overview: 17+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-07-20 17:46 [dpdk-dev] [PATCH] compress/qat: enable dynamic huffman encoding Fiona Trahe
2018-10-05 16:18 ` [dpdk-dev] [PATCH v2] " Fiona Trahe
2018-10-09 11:01 ` Akhil Goyal
2018-10-09 14:09 ` Trahe, Fiona
2018-10-12 11:39 ` Akhil Goyal
2018-10-11 17:03 ` [dpdk-dev] [PATCH v3] " Fiona Trahe
2018-10-15 23:16 ` [dpdk-dev] [PATCH v4] " Fiona Trahe
2018-10-17 10:29 ` Kusztal, ArkadiuszX
2018-10-17 20:48 ` [dpdk-dev] [PATCH v5] " Fiona Trahe
2018-10-24 14:15 ` Akhil Goyal
2018-10-24 21:30 ` Thomas Monjalon
2018-10-25 0:40 ` Trahe, Fiona
2018-10-25 6:45 ` Thomas Monjalon
2018-10-25 1:30 ` [dpdk-dev] [PATCH v6] " Fiona Trahe
2018-10-25 7:34 ` Akhil Goyal
2018-10-26 18:18 ` [dpdk-dev] [PATCH v7] " Fiona Trahe
2018-10-27 0:06 ` Thomas Monjalon
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