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Thu, 3 Jan 2019 15:06:37 +0000 From: Mordechay Haimovsky To: "dev@dpdk.org" CC: Mordechay Haimovsky Thread-Topic: [PATCH v4 3/3] net/mlx5: support flow counters using devx Thread-Index: AQHUo3XsWv4itrzii0O2P934Y8lkiQ== Date: Thu, 3 Jan 2019 15:06:37 +0000 Message-ID: <1546527981-23028-4-git-send-email-motih@mellanox.com> References: <1546422185-30813-4-git-send-email-motih@mellanox.com> In-Reply-To: <1546422185-30813-4-git-send-email-motih@mellanox.com> Accept-Language: he-IL, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: LO2P265CA0219.GBRP265.PROD.OUTLOOK.COM (2603:10a6:600:b::15) To AM0PR05MB4435.eurprd05.prod.outlook.com (2603:10a6:208:5a::20) authentication-results: spf=none (sender IP is ) smtp.mailfrom=motih@mellanox.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 1.7.1 x-originating-ip: [37.142.13.130] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; AM0PR05MB4194; 6:Ju+fgCzbD/PuVu4UR33SxZI+Jf1vpWDyUObhcKGwx4azmptDA/7hnhbIFr76Y/Q7dtsVBh52TTmT6MRXAPvBsXgztom360FSGFpc1evDRzfGQY7HMoTYSiqVuYm5RblThJb23ZVeBjXfCH6zR1t22AMkDCa9aaHprW0lC9ijPy51ATWBsBnaBxBZwCh9rDctRoL0qdolh2nUyoz5yW2v34hOc6LWfZGvYXHgCqmgJaXK/g+8GlnzmSNB+h+Rj00N4gsr4nsscWot8sU3K1/TSYX5HQITqe9BJlSJoK7hd+wSfcoX0hEA+tMnq0qhaXMPpjBsF/aphMST9/xysorFAB+gbslWHdMFFvJJXOHS0bE4F5cY7jr/6Z5wgmi2pyLtnFd/+gqpM1XI5sPyJYF3JjYnxrV9zG8QllS2qLgXGZ7pparYs3/JbcDJb0U7KNw4/hqGWMZt9/Q2Phu5KLjcLQ==; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Mellanox.com X-MS-Exchange-CrossTenant-Network-Message-Id: 68ace9a7-38e0-42f6-5bd6-08d6718d0edc X-MS-Exchange-CrossTenant-originalarrivaltime: 03 Jan 2019 15:06:36.9381 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: a652971c-7d2e-4d9b-a6a4-d149256f461b X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR05MB4194 Subject: [dpdk-dev] [PATCH v4 3/3] net/mlx5: support flow counters using devx X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 03 Jan 2019 15:06:39 -0000 This commit adds counters support when creating flows via direct verbs. The implementation uses devx interface in order to create query and delete the counters. This support requires MLNX_OFED_LINUX-4.5-0.1.0.1 installation. Signed-off-by: Moti Haimovsky --- --- v2: * Modifications according to code review, See message Id: 1545748697-3385-4-git-send-email-motih@mellanox.com v3: * Modified calls to devx routins to be done through the glue interface. See message Id: 1545949196-3355-4-git-send-email-motih@mellanox.com v4: * Fixed compilation errors with old rdma-core packages --- drivers/net/mlx5/Makefile | 6 + drivers/net/mlx5/meson.build | 3 + drivers/net/mlx5/mlx5.c | 16 ++- drivers/net/mlx5/mlx5.h | 15 +++ drivers/net/mlx5/mlx5_devx_cmds.c | 107 +++++++++++++++++ drivers/net/mlx5/mlx5_flow.h | 10 +- drivers/net/mlx5/mlx5_flow_dv.c | 234 ++++++++++++++++++++++++++++++++++= ++-- drivers/net/mlx5/mlx5_prm.h | 71 ++++++++++++ 8 files changed, 447 insertions(+), 15 deletions(-) create mode 100644 drivers/net/mlx5/mlx5_devx_cmds.c diff --git a/drivers/net/mlx5/Makefile b/drivers/net/mlx5/Makefile index 8ddad1a..a1749e4 100644 --- a/drivers/net/mlx5/Makefile +++ b/drivers/net/mlx5/Makefile @@ -36,6 +36,7 @@ SRCS-$(CONFIG_RTE_LIBRTE_MLX5_PMD) +=3D mlx5_flow_tcf.c SRCS-$(CONFIG_RTE_LIBRTE_MLX5_PMD) +=3D mlx5_flow_verbs.c SRCS-$(CONFIG_RTE_LIBRTE_MLX5_PMD) +=3D mlx5_socket.c SRCS-$(CONFIG_RTE_LIBRTE_MLX5_PMD) +=3D mlx5_nl.c +SRCS-$(CONFIG_RTE_LIBRTE_MLX5_PMD) +=3D mlx5_devx_cmds.c =20 ifeq ($(CONFIG_RTE_LIBRTE_MLX5_DLOPEN_DEPS),y) INSTALL-$(CONFIG_RTE_LIBRTE_MLX5_PMD)-lib +=3D $(LIB_GLUE) @@ -153,6 +154,11 @@ mlx5_autoconf.h.new: $(RTE_SDK)/buildtools/auto-config= -h.sh func mlx5dv_devx_obj_create \ $(AUTOCONF_OUTPUT) $Q sh -- '$<' '$@' \ + HAVE_IBV_FLOW_DEVX_COUNTERS \ + infiniband/mlx5dv.h \ + enum MLX5DV_FLOW_ACTION_COUNTER_DEVX \ + $(AUTOCONF_OUTPUT) + $Q sh -- '$<' '$@' \ HAVE_ETHTOOL_LINK_MODE_25G \ /usr/include/linux/ethtool.h \ enum ETHTOOL_LINK_MODE_25000baseCR_Full_BIT \ diff --git a/drivers/net/mlx5/meson.build b/drivers/net/mlx5/meson.build index e2fc4ea..e9db36c 100644 --- a/drivers/net/mlx5/meson.build +++ b/drivers/net/mlx5/meson.build @@ -46,6 +46,7 @@ if build 'mlx5_trigger.c', 'mlx5_txq.c', 'mlx5_vlan.c', + 'mlx5_devx_cmds.c', ) if dpdk_conf.has('RTE_ARCH_X86_64') or dpdk_conf.has('RTE_ARCH_ARM64') sources +=3D files('mlx5_rxtx_vec.c') @@ -106,6 +107,8 @@ if build 'IBV_WQ_FLAG_RX_END_PADDING' ], [ 'HAVE_IBV_DEVX_OBJ', 'infiniband/mlx5dv.h', 'mlx5dv_devx_obj_create' ], + [ 'HAVE_IBV_FLOW_DEVX_COUNTERS', 'infiniband/mlx5dv.h', + 'MLX5DV_FLOW_ACTION_COUNTER_DEVX' ], [ 'HAVE_SUPPORTED_40000baseKR4_Full', 'linux/ethtool.h', 'SUPPORTED_40000baseKR4_Full' ], [ 'HAVE_SUPPORTED_40000baseCR4_Full', 'linux/ethtool.h', diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c index 4521045..c5ed402 100644 --- a/drivers/net/mlx5/mlx5.c +++ b/drivers/net/mlx5/mlx5.c @@ -727,7 +727,7 @@ struct mlx5_dev_config config, const struct mlx5_switch_info *switch_info) { - struct ibv_context *ctx; + struct ibv_context *ctx =3D NULL; struct ibv_device_attr_ex attr; struct ibv_port_attr port_attr; struct ibv_pd *pd =3D NULL; @@ -786,10 +786,16 @@ /* Prepare shared data between primary and secondary process. */ mlx5_prepare_shared_data(); errno =3D 0; - ctx =3D mlx5_glue->open_device(ibv_dev); - if (!ctx) { - rte_errno =3D errno ? errno : ENODEV; - return NULL; + ctx =3D mlx5_glue->dv_open_device(ibv_dev); + if (ctx) { + config.devx =3D 1; + DRV_LOG(DEBUG, "DEVX is supported"); + } else { + ctx =3D mlx5_glue->open_device(ibv_dev); + if (!ctx) { + rte_errno =3D errno ? errno : ENODEV; + return NULL; + } } #ifdef HAVE_IBV_MLX5_MOD_SWP dv_attr.comp_mask |=3D MLX5DV_CONTEXT_MASK_SWP; diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index b48cd94..45f0398 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -98,6 +98,12 @@ struct mlx5_stats_ctrl { uint64_t imissed_base; }; =20 +/* devx counter object */ +struct mlx5_devx_counter_set { + struct mlx5dv_devx_obj *obj; + int id; /* Flow counter ID */ +}; + /* Flow list . */ TAILQ_HEAD(mlx5_flows, rte_flow); =20 @@ -131,6 +137,7 @@ struct mlx5_dev_config { unsigned int vf_nl_en:1; /* Enable Netlink requests in VF mode. */ unsigned int dv_flow_en:1; /* Enable DV flow. */ unsigned int swp:1; /* Tx generic tunnel checksum and TSO offload. */ + unsigned int devx:1; /* Whether devx interface is available or not. */ struct { unsigned int enabled:1; /* Whether MPRQ is enabled. */ unsigned int stride_num_n; /* Number of strides. */ @@ -412,4 +419,12 @@ int mlx5_nl_mac_addr_remove(struct rte_eth_dev *dev, s= truct ether_addr *mac, int mlx5_nl_switch_info(int nl, unsigned int ifindex, struct mlx5_switch_info *info); =20 +/* mlx5_devx_cmds.c */ + +int mlx5_devx_cmd_flow_counter_alloc(struct ibv_context *ctx, + struct mlx5_devx_counter_set *dcx); +int mlx5_devx_cmd_flow_counter_free(struct mlx5dv_devx_obj *obj); +int mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_counter_set *dcx, + int clear, + uint64_t *pkts, uint64_t *bytes); #endif /* RTE_PMD_MLX5_H_ */ diff --git a/drivers/net/mlx5/mlx5_devx_cmds.c b/drivers/net/mlx5/mlx5_devx= _cmds.c new file mode 100644 index 0000000..a9dff58 --- /dev/null +++ b/drivers/net/mlx5/mlx5_devx_cmds.c @@ -0,0 +1,107 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* Copyright 2018 Mellanox Technologies, Ltd */ + +#include + +#include "mlx5.h" +#include "mlx5_glue.h" +#include "mlx5_prm.h" + +/** + * Allocate flow counters via devx interface. + * + * @param[in] ctx + * ibv contexts returned from mlx5dv_open_device. + * @param dcs + * Pointer to counters properties structure to be filled by the routine. + * + * @return + * 0 on success, a negative value otherwise. + */ +int mlx5_devx_cmd_flow_counter_alloc(struct ibv_context *ctx, + struct mlx5_devx_counter_set *dcs) +{ + uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)] =3D {0}; + uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] =3D {0}; + int status, syndrome; + + MLX5_SET(alloc_flow_counter_in, in, opcode, + MLX5_CMD_OP_ALLOC_FLOW_COUNTER); + dcs->obj =3D mlx5_glue->devx_obj_create(ctx, in, + sizeof(in), out, sizeof(out)); + if (!dcs->obj) + return -errno; + status =3D MLX5_GET(query_flow_counter_out, out, status); + syndrome =3D MLX5_GET(query_flow_counter_out, out, syndrome); + if (status) { + DRV_LOG(DEBUG, "Failed to create devx counters, " + "status %x, syndrome %x", status, syndrome); + return -1; + } + dcs->id =3D MLX5_GET(alloc_flow_counter_out, + out, flow_counter_id); + return 0; +} + +/** + * Free flow counters obtained via devx interface. + * + * @param[in] obj + * devx object that was obtained from mlx5_devx_cmd_fc_alloc. + * + * @return + * 0 on success, a negative value otherwise. + */ +int mlx5_devx_cmd_flow_counter_free(struct mlx5dv_devx_obj *obj) +{ + return mlx5_glue->devx_obj_destroy(obj); +} + +/** + * Query flow counters values. + * + * @param[in] dcs + * devx object that was obtained from mlx5_devx_cmd_fc_alloc. + * @param[in] clear + * Whether hardware should clear the counters after the query or not. + * @param pkts + * The number of packets that matched the flow. + * @param bytes + * The number of bytes that matched the flow. + * + * @return + * 0 on success, a negative value otherwise. + */ +int +mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_counter_set *dcs, + int clear __rte_unused, + uint64_t *pkts, uint64_t *bytes) +{ + uint32_t out[MLX5_ST_SZ_BYTES(query_flow_counter_out) + + MLX5_ST_SZ_BYTES(traffic_counter)] =3D {0}; + uint32_t in[MLX5_ST_SZ_DW(query_flow_counter_in)] =3D {0}; + void *stats; + int status, syndrome, rc; + + MLX5_SET(query_flow_counter_in, in, opcode, + MLX5_CMD_OP_QUERY_FLOW_COUNTER); + MLX5_SET(query_flow_counter_in, in, op_mod, 0); + MLX5_SET(query_flow_counter_in, in, flow_counter_id, dcs->id); + rc =3D mlx5_glue->devx_obj_query(dcs->obj, + in, sizeof(in), out, sizeof(out)); + if (rc) + return rc; + status =3D MLX5_GET(query_flow_counter_out, out, status); + syndrome =3D MLX5_GET(query_flow_counter_out, out, syndrome); + if (status) { + DRV_LOG(DEBUG, "Failed to query devx counters, " + "id %d, status %x, syndrome =3D %x", + status, syndrome, dcs->id); + return -1; + } + stats =3D MLX5_ADDR_OF(query_flow_counter_out, + out, flow_statistics); + *pkts =3D MLX5_GET64(traffic_counter, stats, packets); + *bytes =3D MLX5_GET64(traffic_counter, stats, octets); + return 0; +} diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h index cb1e6fd..ad9abb1 100644 --- a/drivers/net/mlx5/mlx5_flow.h +++ b/drivers/net/mlx5/mlx5_flow.h @@ -21,6 +21,9 @@ #pragma GCC diagnostic error "-Wpedantic" #endif =20 +#include "mlx5.h" +#include "mlx5_prm.h" + /* Pattern outer Layer bits. */ #define MLX5_FLOW_LAYER_OUTER_L2 (1u << 0) #define MLX5_FLOW_LAYER_OUTER_L3_IPV4 (1u << 1) @@ -319,11 +322,14 @@ struct mlx5_flow_counter { uint32_t shared:1; /**< Share counter ID with other flow rules. */ uint32_t ref_cnt:31; /**< Reference counter. */ uint32_t id; /**< Counter ID. */ + union { /**< Holds the counters for the rule. */ #if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) - struct ibv_counter_set *cs; /**< Holds the counters for the rule. */ + struct ibv_counter_set *cs; #elif defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45) - struct ibv_counters *cs; /**< Holds the counters for the rule. */ + struct ibv_counters *cs; #endif + struct mlx5_devx_counter_set *dcs; + }; uint64_t hits; /**< Number of packets matched by the rule. */ uint64_t bytes; /**< Number of bytes matched by the rule. */ }; diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_d= v.c index 4c0b7ed..1e9dabd 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -35,6 +35,10 @@ =20 #ifdef HAVE_IBV_FLOW_DV_SUPPORT =20 +#ifndef HAVE_IBV_FLOW_DEVX_COUNTERS +#define MLX5DV_FLOW_ACTION_COUNTER_DEVX 0 +#endif + union flow_dv_attr { struct { uint32_t valid:1; @@ -569,6 +573,36 @@ struct field_modify_info modify_tcp[] =3D { } =20 /** + * Validate count action. + * + * @param[in] dev + * device otr. + * @param[out] error + * Pointer to error structure. + * + * @return + * 0 on success, a negative errno value otherwise and rte_errno is set. + */ +static int +flow_dv_validate_action_count(struct rte_eth_dev *dev, + struct rte_flow_error *error) +{ + struct priv *priv =3D dev->data->dev_private; + + if (!priv->config.devx) + goto notsup_err; +#ifdef HAVE_IBV_FLOW_DEVX_COUNTERS + return 0; +#endif +notsup_err: + return rte_flow_error_set + (error, ENOTSUP, + RTE_FLOW_ERROR_TYPE_UNSPECIFIED, + NULL, + "count action not supported"); +} + +/** * Validate the L2 encap action. * * @param[in] action_flags @@ -1456,6 +1490,87 @@ struct field_modify_info modify_tcp[] =3D { } =20 /** + * Get or create a flow counter. + * + * @param[in] dev + * Pointer to the Ethernet device structure. + * @param[in] shared + * Indicate if this counter is shared with other flows. + * @param[in] id + * Counter identifier. + * + * @return + * pointer to flow counter on success, NULL otherwise and rte_errno is s= et. + */ +static struct mlx5_flow_counter * +flow_dv_counter_new(struct rte_eth_dev *dev, uint32_t shared, uint32_t id) +{ + struct priv *priv =3D dev->data->dev_private; + struct mlx5_flow_counter *cnt =3D NULL; + struct mlx5_devx_counter_set *dcs =3D NULL; + int ret; + + if (!priv->config.devx) { + ret =3D -ENOTSUP; + goto error_exit; + } + if (shared) { + LIST_FOREACH(cnt, &priv->flow_counters, next) { + if (cnt->shared && cnt->id =3D=3D id) { + cnt->ref_cnt++; + return cnt; + } + } + } + cnt =3D rte_calloc(__func__, 1, sizeof(*cnt), 0); + dcs =3D rte_calloc(__func__, 1, sizeof(*dcs), 0); + if (!dcs || !cnt) { + ret =3D -ENOMEM; + goto error_exit; + } + ret =3D mlx5_devx_cmd_flow_counter_alloc(priv->ctx, dcs); + if (ret) + goto error_exit; + struct mlx5_flow_counter tmpl =3D { + .shared =3D shared, + .ref_cnt =3D 1, + .id =3D id, + .dcs =3D dcs, + }; + *cnt =3D tmpl; + LIST_INSERT_HEAD(&priv->flow_counters, cnt, next); + return cnt; +error_exit: + rte_free(cnt); + rte_free(dcs); + rte_errno =3D -ret; + return NULL; +} + +/** + * Release a flow counter. + * + * @param[in] counter + * Pointer to the counter handler. + */ +static void +flow_dv_counter_release(struct mlx5_flow_counter *counter) +{ + int ret; + + if (!counter) + return; + if (--counter->ref_cnt =3D=3D 0) { + ret =3D mlx5_devx_cmd_flow_counter_free(counter->dcs->obj); + if (ret) + DRV_LOG(ERR, "Failed to free devx counters, %d", ret); + LIST_REMOVE(counter, next); + rte_free(counter->dcs); + rte_free(counter); + } +} + +/** * Verify the @p attributes will be correctly understood by the NIC and st= ore * them in the @p flow if everything is correct. * @@ -1717,7 +1832,7 @@ struct field_modify_info modify_tcp[] =3D { ++actions_n; break; case RTE_FLOW_ACTION_TYPE_COUNT: - ret =3D mlx5_flow_validate_action_count(dev, attr, error); + ret =3D flow_dv_validate_action_count(dev, error); if (ret < 0) return ret; action_flags |=3D MLX5_FLOW_ACTION_COUNT; @@ -2741,6 +2856,7 @@ struct field_modify_info modify_tcp[] =3D { const struct rte_flow_action_queue *queue; const struct rte_flow_action_rss *rss; const struct rte_flow_action *action =3D actions; + const struct rte_flow_action_count *count =3D action->conf; const uint8_t *rss_key; =20 switch (actions->type) { @@ -2789,6 +2905,37 @@ struct field_modify_info modify_tcp[] =3D { flow->rss.level =3D rss->level; action_flags |=3D MLX5_FLOW_ACTION_RSS; break; + case RTE_FLOW_ACTION_TYPE_COUNT: + if (!priv->config.devx) { + rte_errno =3D ENOTSUP; + goto cnt_err; + } + flow->counter =3D + flow_dv_counter_new(dev, + count->shared, count->id); + if (flow->counter =3D=3D NULL) + goto cnt_err; + dev_flow->dv.actions[actions_n].type =3D + MLX5DV_FLOW_ACTION_COUNTER_DEVX; + dev_flow->dv.actions[actions_n].obj =3D + flow->counter->dcs->obj; + action_flags |=3D MLX5_FLOW_ACTION_COUNT; + ++actions_n; + break; +cnt_err: + if (rte_errno =3D=3D ENOTSUP) + return rte_flow_error_set + (error, ENOTSUP, + RTE_FLOW_ERROR_TYPE_UNSPECIFIED, + NULL, + "count action not supported"); + else + return rte_flow_error_set + (error, rte_errno, + RTE_FLOW_ERROR_TYPE_ACTION, + action, + "cannot create counter" + " object."); case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP: case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP: if (flow_dv_create_action_l2_encap(dev, actions, @@ -3279,8 +3426,6 @@ struct field_modify_info modify_tcp[] =3D { dv->hrxq =3D NULL; } } - if (flow->counter) - flow->counter =3D NULL; } =20 /** @@ -3299,6 +3444,10 @@ struct field_modify_info modify_tcp[] =3D { if (!flow) return; flow_dv_remove(dev, flow); + if (flow->counter) { + flow_dv_counter_release(flow->counter); + flow->counter =3D NULL; + } while (!LIST_EMPTY(&flow->dev_flows)) { dev_flow =3D LIST_FIRST(&flow->dev_flows); LIST_REMOVE(dev_flow, next); @@ -3313,22 +3462,91 @@ struct field_modify_info modify_tcp[] =3D { } =20 /** + * Query a dv flow rule for its statistics via devx. + * + * @param[in] dev + * Pointer to Ethernet device. + * @param[in] flow + * Pointer to the sub flow. + * @param[out] data + * data retrieved by the query. + * @param[out] error + * Perform verbose error reporting if not NULL. + * + * @return + * 0 on success, a negative errno value otherwise and rte_errno is set. + */ +static int +flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow, + void *data, struct rte_flow_error *error) +{ + struct priv *priv =3D dev->data->dev_private; + struct rte_flow_query_count *qc =3D data; + uint64_t pkts =3D 0; + uint64_t bytes =3D 0; + int err; + + if (!priv->config.devx) + return rte_flow_error_set(error, ENOTSUP, + RTE_FLOW_ERROR_TYPE_UNSPECIFIED, + NULL, + "counters are not supported"); + if (flow->counter) { + err =3D mlx5_devx_cmd_flow_counter_query + (flow->counter->dcs, + qc->reset, &pkts, &bytes); + if (err) + return rte_flow_error_set + (error, err, + RTE_FLOW_ERROR_TYPE_UNSPECIFIED, + NULL, + "cannot read counters"); + qc->hits_set =3D 1; + qc->bytes_set =3D 1; + qc->hits =3D pkts - flow->counter->hits; + qc->bytes =3D bytes - flow->counter->bytes; + if (qc->reset) { + flow->counter->hits =3D pkts; + flow->counter->bytes =3D bytes; + } + return 0; + } + return rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_UNSPECIFIED, + NULL, + "counters are not available"); +} + +/** * Query a flow. * * @see rte_flow_query() * @see rte_flow_ops */ static int -flow_dv_query(struct rte_eth_dev *dev __rte_unused, +flow_dv_query(struct rte_eth_dev *dev, struct rte_flow *flow __rte_unused, const struct rte_flow_action *actions __rte_unused, void *data __rte_unused, struct rte_flow_error *error __rte_unused) { - return rte_flow_error_set(error, ENOTSUP, - RTE_FLOW_ERROR_TYPE_UNSPECIFIED, - NULL, - "flow query with DV is not supported"); + int ret =3D -EINVAL; + + for (; actions->type !=3D RTE_FLOW_ACTION_TYPE_END; actions++) { + switch (actions->type) { + case RTE_FLOW_ACTION_TYPE_VOID: + break; + case RTE_FLOW_ACTION_TYPE_COUNT: + ret =3D flow_dv_query_count(dev, flow, data, error); + break; + default: + return rte_flow_error_set(error, ENOTSUP, + RTE_FLOW_ERROR_TYPE_ACTION, + actions, + "action not supported"); + } + } + return ret; } =20 =20 diff --git a/drivers/net/mlx5/mlx5_prm.h b/drivers/net/mlx5/mlx5_prm.h index 5c39036..da1219e 100644 --- a/drivers/net/mlx5/mlx5_prm.h +++ b/drivers/net/mlx5/mlx5_prm.h @@ -368,6 +368,7 @@ struct mlx5_modification_cmd { #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - \ (__mlx5_bit_off(typ, fld) & 0x1f)) #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32) +#define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64) #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << \ __mlx5_dw_bit_off(typ, fld)) #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1= )) @@ -375,6 +376,7 @@ struct mlx5_modification_cmd { #define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - \ (__mlx5_bit_off(typ, fld) & 0xf)) #define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) -= 1)) +#define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8) #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32) #define MLX5_ST_SZ_DB(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8) #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8) @@ -391,10 +393,16 @@ struct mlx5_modification_cmd { (((_v) & __mlx5_mask(typ, fld)) << \ __mlx5_dw_bit_off(typ, fld))); \ } while (0) +#define MLX5_GET(typ, p, fld) \ + ((rte_be_to_cpu_32(*((__be32 *)(p) +\ + __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \ + __mlx5_mask(typ, fld)) #define MLX5_GET16(typ, p, fld) \ ((rte_be_to_cpu_16(*((__be16 *)(p) + \ __mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \ __mlx5_mask16(typ, fld)) +#define MLX5_GET64(typ, p, fld) rte_be_to_cpu_64(*((__be64 *)(p) + \ + __mlx5_64_off(typ, fld))) #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8) =20 struct mlx5_ifc_fte_match_set_misc_bits { @@ -500,6 +508,69 @@ enum { MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT }; =20 +enum { + MLX5_CMD_OP_ALLOC_FLOW_COUNTER =3D 0x939, + MLX5_CMD_OP_QUERY_FLOW_COUNTER =3D 0x93b, +}; + +/* Flow counters. */ +struct mlx5_ifc_alloc_flow_counter_out_bits { + u8 status[0x8]; + u8 reserved_at_8[0x18]; + u8 syndrome[0x20]; + u8 flow_counter_id[0x20]; + u8 reserved_at_60[0x20]; +}; + +struct mlx5_ifc_alloc_flow_counter_in_bits { + u8 opcode[0x10]; + u8 reserved_at_10[0x10]; + u8 reserved_at_20[0x10]; + u8 op_mod[0x10]; + u8 reserved_at_40[0x40]; +}; + +struct mlx5_ifc_dealloc_flow_counter_out_bits { + u8 status[0x8]; + u8 reserved_at_8[0x18]; + u8 syndrome[0x20]; + u8 reserved_at_40[0x40]; +}; + +struct mlx5_ifc_dealloc_flow_counter_in_bits { + u8 opcode[0x10]; + u8 reserved_at_10[0x10]; + u8 reserved_at_20[0x10]; + u8 op_mod[0x10]; + u8 flow_counter_id[0x20]; + u8 reserved_at_60[0x20]; +}; + +struct mlx5_ifc_traffic_counter_bits { + u8 packets[0x40]; + u8 octets[0x40]; +}; + +struct mlx5_ifc_query_flow_counter_out_bits { + u8 status[0x8]; + u8 reserved_at_8[0x18]; + u8 syndrome[0x20]; + u8 reserved_at_40[0x40]; + struct mlx5_ifc_traffic_counter_bits flow_statistics[]; +}; + +struct mlx5_ifc_query_flow_counter_in_bits { + u8 opcode[0x10]; + u8 reserved_at_10[0x10]; + u8 reserved_at_20[0x10]; + u8 op_mod[0x10]; + u8 reserved_at_40[0x80]; + u8 clear[0x1]; + u8 reserved_at_c1[0xf]; + u8 num_of_counters[0x10]; + u8 flow_counter_id[0x20]; +}; + /* CQE format mask. */ #define MLX5E_CQE_FORMAT_MASK 0xc =20 --=20 1.8.3.1