Re: [dpdk-dev] [EXT] [PATCH] config: change default cache line size for ARMv8 with meson

[Luca Boccassi <bluca@debian.org>]

On Wed, 2019-01-09 at 10:09 +0000, Jerin Jacob Kollanukkaran wrote:
> On Wed, 2019-01-09 at 01:39 -0800, Yongseok Koh wrote:
> > 
> > -------------------------------------------------------------------
> > ---
> > In config/arm64_armv8_linuxapp_gcc, maximum available cache line
> > size
> > (128B) in arm64 implementations is set by default for generic
> > config.
> > However, setting 64B is preferable for meson build in order to
> > support
> > majority of CPUs which don't have Implementor ID or Part Number
> > programmed
> > on chip.
> 
> Adding Luca to get input from distro build perspective.
> 
> If I understand it correctly, distro build will be using
> the generic config/arm/arm64_armv8_linuxapp_gcc for generic build.
> If so, We can not change cache line size for generic config
> as mentined the reason are
> https://mails.dpdk.org/archives/dev/2019-January/122441.html
> 
> 
> I think, I way forward is to add config/arm/arm64_a72_linuxapp_gcc
> for meson. This config can be used for all SoC with A72 armv8 
> implementation and may have sym link to specfific SoC to avoid
> confusion to end users.

For Meson, I recently sent a patch to use a common and stable baseline
machine arg if the uses sets it to "default":

https://patches.dpdk.org/patch/49477/

For distros, I think if, within that path, the cache size is set to the
minimum common denominator like the -march is, it will be fine.

At that point, what happens for "native" or otherwise specified builds
it will not affect distros (as long as they use "default" like Debian
and Ubuntu do).

Does this answer your question?

> > 
> > Signed-off-by: Yongseok Koh <yskoh@mellanox.com>
> > ---
> > 
> > Discussion on the mailing list:
> >     https://mails.dpdk.org/archives/dev/2019-January/122441.html
> > 
> >  config/arm/meson.build | 11 +++++++----
> >  1 file changed, 7 insertions(+), 4 deletions(-)
> > 
> > diff --git a/config/arm/meson.build b/config/arm/meson.build
> > index dae55d6b26..3af256a5ec 100644
> > --- a/config/arm/meson.build
> > +++ b/config/arm/meson.build
> > @@ -47,8 +47,7 @@ flags_common_default = [
> >  flags_generic = [
> >  	['RTE_MACHINE', '"armv8a"'],
> >  	['RTE_MAX_LCORE', 256],
> > -	['RTE_USE_C11_MEM_MODEL', true],
> > -	['RTE_CACHE_LINE_SIZE', 128]]
> > +	['RTE_USE_C11_MEM_MODEL', true]]
> >  flags_cavium = [
> >  	['RTE_MACHINE', '"thunderx"'],
> >  	['RTE_CACHE_LINE_SIZE', 128],
> > @@ -89,15 +88,19 @@ impl_dpaa2 = ['NXP DPAA2', flags_dpaa2,
> > machine_args_generic]
> >  
> >  dpdk_conf.set('RTE_FORCE_INTRINSICS', 1)
> >  
> > +# In config/arm64_armv8_linuxapp_gcc, maximum available cache line
> > size (128B)
> > +# in arm64 implementations is set by default for generic config.
> > However,
> > +# setting 64B is preferable for meson build in order to support
> > majority of CPUs
> > +# which don't have Implementor ID or Part Number programmed on
> > chip.
> > +dpdk_conf.set('RTE_CACHE_LINE_SIZE', 64)
> > +
> >  if cc.sizeof('void *') != 8
> > -	dpdk_conf.set('RTE_CACHE_LINE_SIZE', 64)
> >  	dpdk_conf.set('RTE_ARCH_ARM', 1)
> >  	dpdk_conf.set('RTE_ARCH_ARMv7', 1)
> >  	# the minimum architecture supported, armv7-a, needs the
> > following,
> >  	# mk/machine/armv7a/rte.vars.mk sets it too
> >  	machine_args += '-mfpu=neon'
> >  else
> > -	dpdk_conf.set('RTE_CACHE_LINE_SIZE', 128)
> >  	dpdk_conf.set('RTE_ARCH_ARM64', 1)
> >  	dpdk_conf.set('RTE_ARCH_64', 1)
> >  

-- 
Kind regards,
Luca Boccassi