From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm1-f67.google.com (mail-wm1-f67.google.com [209.85.128.67]) by dpdk.org (Postfix) with ESMTP id 2C9051B465 for ; Wed, 9 Jan 2019 11:19:59 +0100 (CET) Received: by mail-wm1-f67.google.com with SMTP id m22so7586567wml.3 for ; Wed, 09 Jan 2019 02:19:59 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:message-id:subject:from:to:cc:date:in-reply-to :references:content-transfer-encoding:mime-version; bh=6ey2nGfKdZmr8klnU47HYscARA8/u631r7/BpzFug18=; b=IJUBrt+li9i5nH47g5mx7+BoamoSlYZVYADB3GmI+m1HB+x8UzICfey9LhPdPK6Yk9 l/7vdV2q5Pj03lnQg4zGbj/szv3LM5sMO1DjGfv38nCcVpO6qWppjEtStKp+RtfnT9yD xI2hm0uwN6gTMFeMSNmwLLF4D3F505NyAc7gE2eSnx3dD6SqrpibRPzDaRzk1B5pYLqP l8R/UxyPbR9ynZ6sHK0DUAAzYalrgNpNoOLD7q8rbqLG1Bhmuro7Ts83JF9iGPZJj4wd wstljUyF4QriWngUC9v7nrr7VaNpEjfwGoRts4evpENqBm1HkVC/sOyKs98Zwf6g+GKf ozDQ== X-Gm-Message-State: AJcUuke6HWFrn5wiLyeStAihXRrbf4vLPmkxBNsSZOj8B6+GBLnQNeg3 BeTOydkNfNuFlwii1l4kyKs= X-Google-Smtp-Source: ALg8bN47HTpeDFK+37ebRZpy/VmMF8AZkCI3DJCRKRsjEi7O0Uq9Brk4sheUVl7wZkVtjAqjIScgEA== X-Received: by 2002:a1c:b189:: with SMTP id a131mr5215503wmf.38.1547029198529; Wed, 09 Jan 2019 02:19:58 -0800 (PST) Received: from localhost ([2001:1be0:110d:fcfe:132c:a71a:1896:1395]) by smtp.gmail.com with ESMTPSA id 67sm85710794wra.37.2019.01.09.02.19.57 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 09 Jan 2019 02:19:57 -0800 (PST) Message-ID: <1547029195.6022.54.camel@debian.org> From: Luca Boccassi To: Jerin Jacob Kollanukkaran , "thomas@monjalon.net" , "yskoh@mellanox.com" Cc: "shahafs@mellanox.com" , "Gavin.Hu@arm.com" , "dev@dpdk.org" Date: Wed, 09 Jan 2019 10:19:55 +0000 In-Reply-To: <68eb1e77e09e396a229920f10487b6e95ddce5c8.camel@marvell.com> References: <20190109093915.40882-1-yskoh@mellanox.com> <68eb1e77e09e396a229920f10487b6e95ddce5c8.camel@marvell.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Mailer: Evolution 3.22.6-1+deb9u1 Mime-Version: 1.0 Subject: Re: [dpdk-dev] [EXT] [PATCH] config: change default cache line size for ARMv8 with meson X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 09 Jan 2019 10:19:59 -0000 On Wed, 2019-01-09 at 10:09 +0000, Jerin Jacob Kollanukkaran wrote: > On Wed, 2019-01-09 at 01:39 -0800, Yongseok Koh wrote: > >=20 > > ------------------------------------------------------------------- > > --- > > In config/arm64_armv8_linuxapp_gcc, maximum available cache line > > size > > (128B) in arm64 implementations is set by default for generic > > config. > > However, setting 64B is preferable for meson build in order to > > support > > majority of CPUs which don't have Implementor ID or Part Number > > programmed > > on chip. >=20 > Adding Luca to get input from distro build perspective. >=20 > If I understand it correctly, distro build will be using > the generic config/arm/arm64_armv8_linuxapp_gcc for generic build. > If so, We can not change cache line size for generic config > as mentined the reason are > https://mails.dpdk.org/archives/dev/2019-January/122441.html >=20 >=20 > I think, I way forward is to add config/arm/arm64_a72_linuxapp_gcc > for meson. This config can be used for all SoC with A72 armv8=C2=A0 > implementation and may have sym link to specfific SoC to avoid > confusion to end users. For Meson, I recently sent a patch to use a common and stable baseline machine arg if the uses sets it to "default": https://patches.dpdk.org/patch/49477/ For distros, I think if, within that path, the cache size is set to the minimum common denominator like the -march is, it will be fine. At that point, what happens for "native" or otherwise specified builds it will not affect distros (as long as they use "default" like Debian and Ubuntu do). Does this answer your question? > >=20 > > Signed-off-by: Yongseok Koh > > --- > >=20 > > Discussion on the mailing list: > > =C2=A0=C2=A0=C2=A0=C2=A0https://mails.dpdk.org/archives/dev/2019-Januar= y/122441.html > >=20 > > =C2=A0config/arm/meson.build | 11 +++++++---- > > =C2=A01 file changed, 7 insertions(+), 4 deletions(-) > >=20 > > diff --git a/config/arm/meson.build b/config/arm/meson.build > > index dae55d6b26..3af256a5ec 100644 > > --- a/config/arm/meson.build > > +++ b/config/arm/meson.build > > @@ -47,8 +47,7 @@ flags_common_default =3D [ > > =C2=A0flags_generic =3D [ > > =C2=A0 ['RTE_MACHINE', '"armv8a"'], > > =C2=A0 ['RTE_MAX_LCORE', 256], > > - ['RTE_USE_C11_MEM_MODEL', true], > > - ['RTE_CACHE_LINE_SIZE', 128]] > > + ['RTE_USE_C11_MEM_MODEL', true]] > > =C2=A0flags_cavium =3D [ > > =C2=A0 ['RTE_MACHINE', '"thunderx"'], > > =C2=A0 ['RTE_CACHE_LINE_SIZE', 128], > > @@ -89,15 +88,19 @@ impl_dpaa2 =3D ['NXP DPAA2', flags_dpaa2, > > machine_args_generic] > > =C2=A0 > > =C2=A0dpdk_conf.set('RTE_FORCE_INTRINSICS', 1) > > =C2=A0 > > +# In config/arm64_armv8_linuxapp_gcc, maximum available cache line > > size (128B) > > +# in arm64 implementations is set by default for generic config. > > However, > > +# setting 64B is preferable for meson build in order to support > > majority of CPUs > > +# which don't have Implementor ID or Part Number programmed on > > chip. > > +dpdk_conf.set('RTE_CACHE_LINE_SIZE', 64) > > + > > =C2=A0if cc.sizeof('void *') !=3D 8 > > - dpdk_conf.set('RTE_CACHE_LINE_SIZE', 64) > > =C2=A0 dpdk_conf.set('RTE_ARCH_ARM', 1) > > =C2=A0 dpdk_conf.set('RTE_ARCH_ARMv7', 1) > > =C2=A0 # the minimum architecture supported, armv7-a, needs the > > following, > > =C2=A0 # mk/machine/armv7a/rte.vars.mk sets it too > > =C2=A0 machine_args +=3D '-mfpu=3Dneon' > > =C2=A0else > > - dpdk_conf.set('RTE_CACHE_LINE_SIZE', 128) > > =C2=A0 dpdk_conf.set('RTE_ARCH_ARM64', 1) > > =C2=A0 dpdk_conf.set('RTE_ARCH_64', 1) > > =C2=A0 --=20 Kind regards, Luca Boccassi