From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dispatch1-us1.ppe-hosted.com (dispatch1-us1.ppe-hosted.com [67.231.154.164]) by dpdk.org (Postfix) with ESMTP id 6FFBB1B578 for ; Thu, 7 Feb 2019 17:30:37 +0100 (CET) X-Virus-Scanned: Proofpoint Essentials engine Received: from webmail.solarflare.com (webmail.solarflare.com [12.187.104.26]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits)) (No client certificate requested) by mx1-us3.ppe-hosted.com (Proofpoint Essentials ESMTP Server) with ESMTPS id 43103B8006C; Thu, 7 Feb 2019 16:30:36 +0000 (UTC) Received: from ocex03.SolarFlarecom.com (10.20.40.36) by ocex03.SolarFlarecom.com (10.20.40.36) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 7 Feb 2019 08:30:31 -0800 Received: from opal.uk.solarflarecom.com (10.17.10.1) by ocex03.SolarFlarecom.com (10.20.40.36) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Thu, 7 Feb 2019 08:30:31 -0800 Received: from ukv-loginhost.uk.solarflarecom.com (ukv-loginhost.uk.solarflarecom.com [10.17.10.39]) by opal.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id x17GUUC1015324; Thu, 7 Feb 2019 16:30:30 GMT Received: from ukv-loginhost.uk.solarflarecom.com (localhost [127.0.0.1]) by ukv-loginhost.uk.solarflarecom.com (Postfix) with ESMTP id 0CC741613EB; Thu, 7 Feb 2019 16:30:30 +0000 (GMT) From: Andrew Rybchenko To: CC: Igor Romanov Date: Thu, 7 Feb 2019 16:29:24 +0000 Message-ID: <1549556983-10896-20-git-send-email-arybchenko@solarflare.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1549556983-10896-1-git-send-email-arybchenko@solarflare.com> References: <1549556983-10896-1-git-send-email-arybchenko@solarflare.com> MIME-Version: 1.0 Content-Type: text/plain X-TM-AS-Product-Ver: SMEX-12.5.0.1300-8.5.1010-24412.006 X-TM-AS-Result: Yes-4.353000-4.000000-11 X-TMASE-MatchedRID: n7nN31NWDDqL06bhI7iKZEf49ONH0RaSrMFnULqstthTorRIuadptHB4 4IkzjfYy4ZH8wasvhJeIukMxD7tJAY/opKiQWjqUyDp+jSvEtWtKKWJchzA/cZwLKCK/wCJ9MFd dv+pLbrdxe/mAKzaU+FHovnik60pnrQBOOK5IkYlLc5N+0s1+DdvhKQZ2RM31grAXgr/AjP2Zih rH2a5I27Um7psYhp0tgDLqnrRlXrZ8nn9tnqel2K6NVEWSRWyb3SgBIfy0ZFd55GRuo4ZdUV0fW KHZz3eMFXrL8KhVqZbhMHRcbKniWRYhl+3Hr4wAXQQxYVvzjLCCmGAP55/3Del/pavUZx5D8Oyc cFNBL2TKhETi2//sjuP9Cb59K8ACZrS+A8PszW9A/zCH/Tq5HQ== X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 11-4.353000-4.000000 X-TMASE-Version: SMEX-12.5.0.1300-8.5.1010-24412.006 X-MDID: 1549557036-mik2FssZdxvJ Subject: [dpdk-dev] [PATCH 19/38] net/sfc/base: support different Rx descriptor sizes X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 07 Feb 2019 16:30:38 -0000 From: Igor Romanov For consistency with the size of Tx descriptors, the size of Rx descriptors should be a part of NIC config, not a macro that is common for all NIC families. Signed-off-by: Igor Romanov Signed-off-by: Andrew Rybchenko --- drivers/net/sfc/base/ef10_impl.h | 1 + drivers/net/sfc/base/ef10_rx.c | 5 +++-- drivers/net/sfc/base/efx.h | 21 +++++++++++++++++++++ drivers/net/sfc/base/efx_rx.c | 18 ++++++++++++++++++ drivers/net/sfc/base/hunt_nic.c | 1 + drivers/net/sfc/base/medford2_nic.c | 1 + drivers/net/sfc/base/medford_nic.c | 1 + drivers/net/sfc/base/siena_impl.h | 1 + drivers/net/sfc/base/siena_nic.c | 1 + 9 files changed, 48 insertions(+), 2 deletions(-) diff --git a/drivers/net/sfc/base/ef10_impl.h b/drivers/net/sfc/base/ef10_impl.h index 0116bc91c..11c61d9e6 100644 --- a/drivers/net/sfc/base/ef10_impl.h +++ b/drivers/net/sfc/base/ef10_impl.h @@ -19,6 +19,7 @@ extern "C" { #define EF10_TXQ_MINNDESCS 512 +#define EF10_RXQ_DESC_SIZE (sizeof (efx_qword_t)) #define EF10_TXQ_DESC_SIZE (sizeof (efx_qword_t)) /* Maximum independent of EFX_BUG35388_WORKAROUND. */ diff --git a/drivers/net/sfc/base/ef10_rx.c b/drivers/net/sfc/base/ef10_rx.c index f2b72571a..23b80d78f 100644 --- a/drivers/net/sfc/base/ef10_rx.c +++ b/drivers/net/sfc/base/ef10_rx.c @@ -31,7 +31,7 @@ efx_mcdi_init_rxq( efx_mcdi_req_t req; EFX_MCDI_DECLARE_BUF(payload, MC_CMD_INIT_RXQ_V3_IN_LEN, MC_CMD_INIT_RXQ_V3_OUT_LEN); - int npages = EFX_RXQ_NBUFS(ndescs); + int npages = efx_rxq_nbufs(enp, ndescs); int i; efx_qword_t *dma_addr; uint64_t addr; @@ -41,7 +41,8 @@ efx_mcdi_init_rxq( EFSYS_ASSERT3U(ndescs, <=, encp->enc_rxq_max_ndescs); - if ((esmp == NULL) || (EFSYS_MEM_SIZE(esmp) < EFX_RXQ_SIZE(ndescs))) { + if ((esmp == NULL) || + (EFSYS_MEM_SIZE(esmp) < efx_rxq_size(enp, ndescs))) { rc = EINVAL; goto fail1; } diff --git a/drivers/net/sfc/base/efx.h b/drivers/net/sfc/base/efx.h index 506bdb5e1..101bb4cd2 100644 --- a/drivers/net/sfc/base/efx.h +++ b/drivers/net/sfc/base/efx.h @@ -1284,6 +1284,7 @@ typedef struct efx_nic_cfg_s { uint32_t enc_evq_timer_quantum_ns; uint32_t enc_evq_timer_max_us; uint32_t enc_clk_mult; + uint32_t enc_rx_desc_size; uint32_t enc_tx_desc_size; uint32_t enc_rx_prefix_size; uint32_t enc_rx_buf_align_start; @@ -2478,8 +2479,28 @@ efx_pseudo_hdr_pkt_length_get( #define EFX_RXQ_MAXNDESCS 4096 #define EFX_RXQ_MINNDESCS 512 +/* + * This macro is deprecated and will be removed. + * Use the function efx_rxq_size() instead. + */ #define EFX_RXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t)) + +/* + * This macro is deprecated and will be removed. + * Use the function efx_rxq_nbufs() instead. + */ #define EFX_RXQ_NBUFS(_ndescs) (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE) + +extern __checkReturn size_t +efx_rxq_size( + __in const efx_nic_t *enp, + __in unsigned int ndescs); + +extern __checkReturn unsigned int +efx_rxq_nbufs( + __in const efx_nic_t *enp, + __in unsigned int ndescs); + #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16) typedef enum efx_rxq_type_e { diff --git a/drivers/net/sfc/base/efx_rx.c b/drivers/net/sfc/base/efx_rx.c index 8910cd5f7..c0d738128 100644 --- a/drivers/net/sfc/base/efx_rx.c +++ b/drivers/net/sfc/base/efx_rx.c @@ -766,6 +766,24 @@ efx_rx_qflush( return (rc); } + __checkReturn size_t +efx_rxq_size( + __in const efx_nic_t *enp, + __in unsigned int ndescs) +{ + const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp); + + return (ndescs * encp->enc_rx_desc_size); +} + + __checkReturn unsigned int +efx_rxq_nbufs( + __in const efx_nic_t *enp, + __in unsigned int ndescs) +{ + return (efx_rxq_size(enp, ndescs) / EFX_BUF_SIZE); +} + void efx_rx_qenable( __in efx_rxq_t *erp) diff --git a/drivers/net/sfc/base/hunt_nic.c b/drivers/net/sfc/base/hunt_nic.c index b4fc3cc9e..2fb54d85a 100644 --- a/drivers/net/sfc/base/hunt_nic.c +++ b/drivers/net/sfc/base/hunt_nic.c @@ -186,6 +186,7 @@ hunt_board_cfg( /* Checksums for TSO sends can be incorrect on Huntington. */ encp->enc_bug61297_workaround = B_TRUE; + encp->enc_rx_desc_size = EF10_RXQ_DESC_SIZE; encp->enc_tx_desc_size = EF10_TXQ_DESC_SIZE; /* Alignment for receive packet DMA buffers */ diff --git a/drivers/net/sfc/base/medford2_nic.c b/drivers/net/sfc/base/medford2_nic.c index 9cfc5077c..7d0c80047 100644 --- a/drivers/net/sfc/base/medford2_nic.c +++ b/drivers/net/sfc/base/medford2_nic.c @@ -101,6 +101,7 @@ medford2_board_cfg( encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns << FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000; + encp->enc_rx_desc_size = EF10_RXQ_DESC_SIZE; encp->enc_tx_desc_size = EF10_TXQ_DESC_SIZE; /* Alignment for receive packet DMA buffers */ diff --git a/drivers/net/sfc/base/medford_nic.c b/drivers/net/sfc/base/medford_nic.c index 3f2c5b877..fd711a96f 100644 --- a/drivers/net/sfc/base/medford_nic.c +++ b/drivers/net/sfc/base/medford_nic.c @@ -99,6 +99,7 @@ medford_board_cfg( encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns << FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000; + encp->enc_rx_desc_size = EF10_RXQ_DESC_SIZE; encp->enc_tx_desc_size = EF10_TXQ_DESC_SIZE; /* Alignment for receive packet DMA buffers */ diff --git a/drivers/net/sfc/base/siena_impl.h b/drivers/net/sfc/base/siena_impl.h index 6f07b1ec7..068960025 100644 --- a/drivers/net/sfc/base/siena_impl.h +++ b/drivers/net/sfc/base/siena_impl.h @@ -34,6 +34,7 @@ extern "C" { #define SIENA_RXQ_MAXNDESCS 4096 #define SIENA_RXQ_MINNDESCS 512 +#define SIENA_RXQ_DESC_SIZE (sizeof (efx_qword_t)) #define SIENA_TXQ_DESC_SIZE (sizeof (efx_qword_t)) #define SIENA_NVRAM_CHUNK 0x80 diff --git a/drivers/net/sfc/base/siena_nic.c b/drivers/net/sfc/base/siena_nic.c index 987a32d2f..894cf8144 100644 --- a/drivers/net/sfc/base/siena_nic.c +++ b/drivers/net/sfc/base/siena_nic.c @@ -104,6 +104,7 @@ siena_board_cfg( encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns << FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000; + encp->enc_rx_desc_size = SIENA_RXQ_DESC_SIZE; encp->enc_tx_desc_size = SIENA_TXQ_DESC_SIZE; /* When hash header insertion is enabled, Siena inserts 16 bytes */ -- 2.17.1