From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dispatch1-us1.ppe-hosted.com (dispatch1-us1.ppe-hosted.com [67.231.154.164]) by dpdk.org (Postfix) with ESMTP id 27AE51B56F for ; Thu, 7 Feb 2019 17:30:35 +0100 (CET) X-Virus-Scanned: Proofpoint Essentials engine Received: from webmail.solarflare.com (webmail.solarflare.com [12.187.104.26]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits)) (No client certificate requested) by mx1-us4.ppe-hosted.com (Proofpoint Essentials ESMTP Server) with ESMTPS id 9C22EB40123; Thu, 7 Feb 2019 16:30:33 +0000 (UTC) Received: from ocex03.SolarFlarecom.com (10.20.40.36) by ocex03.SolarFlarecom.com (10.20.40.36) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 7 Feb 2019 08:30:30 -0800 Received: from opal.uk.solarflarecom.com (10.17.10.1) by ocex03.SolarFlarecom.com (10.20.40.36) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Thu, 7 Feb 2019 08:30:30 -0800 Received: from ukv-loginhost.uk.solarflarecom.com (ukv-loginhost.uk.solarflarecom.com [10.17.10.39]) by opal.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id x17GUTnU015266; Thu, 7 Feb 2019 16:30:29 GMT Received: from ukv-loginhost.uk.solarflarecom.com (localhost [127.0.0.1]) by ukv-loginhost.uk.solarflarecom.com (Postfix) with ESMTP id 46E3A1613EB; Thu, 7 Feb 2019 16:30:29 +0000 (GMT) From: Andrew Rybchenko To: CC: Igor Romanov Date: Thu, 7 Feb 2019 16:29:10 +0000 Message-ID: <1549556983-10896-6-git-send-email-arybchenko@solarflare.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1549556983-10896-1-git-send-email-arybchenko@solarflare.com> References: <1549556983-10896-1-git-send-email-arybchenko@solarflare.com> MIME-Version: 1.0 Content-Type: text/plain X-TM-AS-Product-Ver: SMEX-12.5.0.1300-8.5.1010-24412.006 X-TM-AS-Result: No-6.520100-4.000000-10 X-TMASE-MatchedRID: F1cOzWYaEztH6YaT4D0RZl4SsF49N47AG1MJZJUELLgs/uUAk6xP7Ktx F2NIaI5lQVR8eBV4MOl4CMgAuim1qO4dcT3ZaToc4pdq9sdj8LWcXyt+Ve6JFQauykv+8qSO1sT lzu9ctp37sIzcmIKIQ4Ay6p60ZV62fJ5/bZ6npdiyO81X3yak83lAW/TvEn9kbioTqNqRiyy4lz rCo+T4Sq81lK5Eyfqe+VKZulF+Ard+3BndfXUhXQ== X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--6.520100-4.000000 X-TMASE-Version: SMEX-12.5.0.1300-8.5.1010-24412.006 X-MDID: 1549557034-DIjzT5YB_wYL Subject: [dpdk-dev] [PATCH 05/38] net/sfc/base: remove min define for number of Tx descs X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 07 Feb 2019 16:30:35 -0000 From: Igor Romanov EF100/Riverhead has different min limit. So, this limit should be a part of NIC config, not define common for all NIC families. Define maximum Tx descriptor number for Siena in the same way as minimum for consistency. Signed-off-by: Igor Romanov Signed-off-by: Andrew Rybchenko --- drivers/net/sfc/base/ef10_impl.h | 1 + drivers/net/sfc/base/efx.h | 5 +++++ drivers/net/sfc/base/efx_tx.c | 8 ++++---- drivers/net/sfc/base/hunt_nic.c | 1 + drivers/net/sfc/base/medford2_nic.c | 1 + drivers/net/sfc/base/medford_nic.c | 1 + drivers/net/sfc/base/siena_impl.h | 3 +++ drivers/net/sfc/base/siena_nic.c | 3 ++- 8 files changed, 18 insertions(+), 5 deletions(-) diff --git a/drivers/net/sfc/base/ef10_impl.h b/drivers/net/sfc/base/ef10_impl.h index 83a8a2936..165a4013c 100644 --- a/drivers/net/sfc/base/ef10_impl.h +++ b/drivers/net/sfc/base/ef10_impl.h @@ -11,6 +11,7 @@ extern "C" { #endif +#define EF10_TXQ_MINNDESCS 512 /* Number of hardware PIO buffers (for compile-time resource dimensions) */ #define EF10_MAX_PIOBUF_NBUFS (16) diff --git a/drivers/net/sfc/base/efx.h b/drivers/net/sfc/base/efx.h index a612b6988..5b5d790fc 100644 --- a/drivers/net/sfc/base/efx.h +++ b/drivers/net/sfc/base/efx.h @@ -1272,6 +1272,7 @@ typedef struct efx_nic_cfg_s { uint32_t enc_txq_limit; uint32_t enc_rxq_limit; uint32_t enc_txq_max_ndescs; + uint32_t enc_txq_min_ndescs; uint32_t enc_buftbl_limit; uint32_t enc_piobuf_limit; uint32_t enc_piobuf_size; @@ -2627,6 +2628,10 @@ extern void efx_tx_fini( __in efx_nic_t *enp); +/* + * This symbol is deprecated and will be removed. + * Use the field from efx_nic_cfg_t instead. + */ #define EFX_TXQ_MINNDESCS 512 #define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t)) diff --git a/drivers/net/sfc/base/efx_tx.c b/drivers/net/sfc/base/efx_tx.c index 9fa9e2ed1..ebbdeb3d4 100644 --- a/drivers/net/sfc/base/efx_tx.c +++ b/drivers/net/sfc/base/efx_tx.c @@ -923,10 +923,10 @@ siena_tx_qcreate( EFSYS_ASSERT3U(label, <, EFX_EV_TX_NLABELS); EFSYS_ASSERT(ISP2(encp->enc_txq_max_ndescs)); - EFX_STATIC_ASSERT(ISP2(EFX_TXQ_MINNDESCS)); + EFSYS_ASSERT(ISP2(encp->enc_txq_min_ndescs)); if (!ISP2(ndescs) || - (ndescs < EFX_TXQ_MINNDESCS) || + (ndescs < encp->enc_txq_min_ndescs) || (ndescs > encp->enc_txq_max_ndescs)) { rc = EINVAL; goto fail1; @@ -936,9 +936,9 @@ siena_tx_qcreate( goto fail2; } for (size = 0; - (1 << size) <= (int)(encp->enc_txq_max_ndescs / EFX_TXQ_MINNDESCS); + (1U << size) <= encp->enc_txq_max_ndescs / encp->enc_txq_min_ndescs; size++) - if ((1 << size) == (int)(ndescs / EFX_TXQ_MINNDESCS)) + if ((1U << size) == (uint32_t)ndescs / encp->enc_txq_min_ndescs) break; if (id + (1 << size) >= encp->enc_buftbl_limit) { rc = EINVAL; diff --git a/drivers/net/sfc/base/hunt_nic.c b/drivers/net/sfc/base/hunt_nic.c index ca30e90f7..adb2b17eb 100644 --- a/drivers/net/sfc/base/hunt_nic.c +++ b/drivers/net/sfc/base/hunt_nic.c @@ -195,6 +195,7 @@ hunt_board_cfg( * descriptor writes, preventing the use of 4096 descriptor TXQs. */ encp->enc_txq_max_ndescs = encp->enc_bug35388_workaround ? 2048 : 4096; + encp->enc_txq_min_ndescs = EF10_TXQ_MINNDESCS; EFX_STATIC_ASSERT(HUNT_PIOBUF_NBUFS <= EF10_MAX_PIOBUF_NBUFS); encp->enc_piobuf_limit = HUNT_PIOBUF_NBUFS; diff --git a/drivers/net/sfc/base/medford2_nic.c b/drivers/net/sfc/base/medford2_nic.c index 6bc1e87cc..2cc87e3a9 100644 --- a/drivers/net/sfc/base/medford2_nic.c +++ b/drivers/net/sfc/base/medford2_nic.c @@ -120,6 +120,7 @@ medford2_board_cfg( * stuffing. */ encp->enc_txq_max_ndescs = 2048; + encp->enc_txq_min_ndescs = EF10_TXQ_MINNDESCS; EFX_STATIC_ASSERT(MEDFORD2_PIOBUF_NBUFS <= EF10_MAX_PIOBUF_NBUFS); encp->enc_piobuf_limit = MEDFORD2_PIOBUF_NBUFS; diff --git a/drivers/net/sfc/base/medford_nic.c b/drivers/net/sfc/base/medford_nic.c index bfe01ca93..b72881179 100644 --- a/drivers/net/sfc/base/medford_nic.c +++ b/drivers/net/sfc/base/medford_nic.c @@ -118,6 +118,7 @@ medford_board_cfg( * stuffing. */ encp->enc_txq_max_ndescs = 2048; + encp->enc_txq_min_ndescs = EF10_TXQ_MINNDESCS; EFX_STATIC_ASSERT(MEDFORD_PIOBUF_NBUFS <= EF10_MAX_PIOBUF_NBUFS); encp->enc_piobuf_limit = MEDFORD_PIOBUF_NBUFS; diff --git a/drivers/net/sfc/base/siena_impl.h b/drivers/net/sfc/base/siena_impl.h index d70bbff8f..549712377 100644 --- a/drivers/net/sfc/base/siena_impl.h +++ b/drivers/net/sfc/base/siena_impl.h @@ -24,6 +24,9 @@ extern "C" { #endif #define EFX_TXQ_DC_NDESCS(_dcsize) (8 << (_dcsize)) +#define SIENA_TXQ_MAXNDESCS 4096 +#define SIENA_TXQ_MINNDESCS 512 + #define SIENA_NVRAM_CHUNK 0x80 diff --git a/drivers/net/sfc/base/siena_nic.c b/drivers/net/sfc/base/siena_nic.c index fca17171b..0f02195c0 100644 --- a/drivers/net/sfc/base/siena_nic.c +++ b/drivers/net/sfc/base/siena_nic.c @@ -149,7 +149,8 @@ siena_board_cfg( encp->enc_rxq_limit = MIN(EFX_RXQ_LIMIT_TARGET, nrxq); encp->enc_txq_limit = MIN(EFX_TXQ_LIMIT_TARGET, ntxq); - encp->enc_txq_max_ndescs = 4096; + encp->enc_txq_max_ndescs = SIENA_TXQ_MAXNDESCS; + encp->enc_txq_min_ndescs = SIENA_TXQ_MINNDESCS; encp->enc_buftbl_limit = SIENA_SRAM_ROWS - (encp->enc_txq_limit * EFX_TXQ_DC_NDESCS(EFX_TXQ_DC_SIZE)) - -- 2.17.1