From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dispatch1-us1.ppe-hosted.com (dispatch1-us1.ppe-hosted.com [67.231.154.164]) by dpdk.org (Postfix) with ESMTP id A18B31B580 for ; Thu, 7 Feb 2019 17:30:35 +0100 (CET) X-Virus-Scanned: Proofpoint Essentials engine Received: from webmail.solarflare.com (webmail.solarflare.com [12.187.104.26]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits)) (No client certificate requested) by mx1-us4.ppe-hosted.com (Proofpoint Essentials ESMTP Server) with ESMTPS id 73127B401B4; Thu, 7 Feb 2019 16:30:34 +0000 (UTC) Received: from ocex03.SolarFlarecom.com (10.20.40.36) by ocex03.SolarFlarecom.com (10.20.40.36) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 7 Feb 2019 08:30:30 -0800 Received: from opal.uk.solarflarecom.com (10.17.10.1) by ocex03.SolarFlarecom.com (10.20.40.36) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Thu, 7 Feb 2019 08:30:30 -0800 Received: from ukv-loginhost.uk.solarflarecom.com (ukv-loginhost.uk.solarflarecom.com [10.17.10.39]) by opal.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id x17GUTjp015276; Thu, 7 Feb 2019 16:30:29 GMT Received: from ukv-loginhost.uk.solarflarecom.com (localhost [127.0.0.1]) by ukv-loginhost.uk.solarflarecom.com (Postfix) with ESMTP id 63A861613F0; Thu, 7 Feb 2019 16:30:29 +0000 (GMT) From: Andrew Rybchenko To: CC: Igor Romanov Date: Thu, 7 Feb 2019 16:29:12 +0000 Message-ID: <1549556983-10896-8-git-send-email-arybchenko@solarflare.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1549556983-10896-1-git-send-email-arybchenko@solarflare.com> References: <1549556983-10896-1-git-send-email-arybchenko@solarflare.com> MIME-Version: 1.0 Content-Type: text/plain X-TM-AS-Product-Ver: SMEX-12.5.0.1300-8.5.1010-24412.006 X-TM-AS-Result: No-3.182900-4.000000-10 X-TMASE-MatchedRID: t0V6V3Db6XA2jeY+Udg/Im4gfPq9dKeJ7qPKKDEKjrIs/uUAk6xP7ICu qghmtWfXmyr1EA+2/DDHdRuTe36BzNfV8L2ZOXrNyeVujmXuYYXEoDEGChh7CRS11FlOYRohS0e iOsrXcTgzkoS7NSD9vWJVHm/j9yxpSgu5Yo8VqDhDmVmiQbM5ql+iEcKpKdpuw01zN1c0miJRUx WIvi1rmuLzNWBegCW2wgn7iDBesS1YF3qW3Je6+z2akx8hsGa7joGo9Bys9BDNPyw27KIAX55rS oTnjQ35jZnMJwYLFegmsYD3iS8m3qyAkCkhGgUlMwyGG7Ram2nH9bg6UMZEH71NuKS30BZnQIFI ZLtsgG0DUH+nVLNyiCsqIP9TxvtJhyLR7CBmZbR+3BndfXUhXQ== X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--3.182900-4.000000 X-TMASE-Version: SMEX-12.5.0.1300-8.5.1010-24412.006 X-MDID: 1549557035-6QmrfS2q4B2V Subject: [dpdk-dev] [PATCH 07/38] net/sfc/base: remove min/max defines for number of Rx descs X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 07 Feb 2019 16:30:35 -0000 From: Igor Romanov EF100/Riverhead has different min/max limits. So, these limits should be a part of NIC config, not defines common for all NIC families. Signed-off-by: Igor Romanov Signed-off-by: Andrew Rybchenko --- drivers/net/sfc/base/ef10_impl.h | 3 +++ drivers/net/sfc/base/ef10_rx.c | 9 +++++---- drivers/net/sfc/base/efx.h | 10 ++++++++-- drivers/net/sfc/base/efx_rx.c | 12 +++++++----- drivers/net/sfc/base/hunt_nic.c | 3 +++ drivers/net/sfc/base/medford2_nic.c | 3 +++ drivers/net/sfc/base/medford_nic.c | 3 +++ drivers/net/sfc/base/siena_impl.h | 3 +++ drivers/net/sfc/base/siena_nic.c | 3 +++ 9 files changed, 38 insertions(+), 11 deletions(-) diff --git a/drivers/net/sfc/base/ef10_impl.h b/drivers/net/sfc/base/ef10_impl.h index 165a4013c..bf71b5a18 100644 --- a/drivers/net/sfc/base/ef10_impl.h +++ b/drivers/net/sfc/base/ef10_impl.h @@ -11,6 +11,9 @@ extern "C" { #endif +#define EF10_RXQ_MAXNDESCS 4096 +#define EF10_RXQ_MINNDESCS 512 + #define EF10_TXQ_MINNDESCS 512 /* Number of hardware PIO buffers (for compile-time resource dimensions) */ diff --git a/drivers/net/sfc/base/ef10_rx.c b/drivers/net/sfc/base/ef10_rx.c index d18010d0f..1f2a6e009 100644 --- a/drivers/net/sfc/base/ef10_rx.c +++ b/drivers/net/sfc/base/ef10_rx.c @@ -39,7 +39,7 @@ efx_mcdi_init_rxq( uint32_t dma_mode; boolean_t want_outer_classes; - EFSYS_ASSERT3U(ndescs, <=, EFX_RXQ_MAXNDESCS); + EFSYS_ASSERT3U(ndescs, <=, encp->enc_rxq_max_ndescs); if ((esmp == NULL) || (EFSYS_MEM_SIZE(esmp) < EFX_RXQ_SIZE(ndescs))) { rc = EINVAL; @@ -1012,11 +1012,12 @@ ef10_rx_qcreate( EFSYS_ASSERT3U(label, <, EFX_EV_RX_NLABELS); EFSYS_ASSERT3U(enp->en_rx_qcount + 1, <, encp->enc_rxq_limit); - EFX_STATIC_ASSERT(ISP2(EFX_RXQ_MAXNDESCS)); - EFX_STATIC_ASSERT(ISP2(EFX_RXQ_MINNDESCS)); + EFSYS_ASSERT(ISP2(encp->enc_rxq_max_ndescs)); + EFSYS_ASSERT(ISP2(encp->enc_rxq_min_ndescs)); if (!ISP2(ndescs) || - (ndescs < EFX_RXQ_MINNDESCS) || (ndescs > EFX_RXQ_MAXNDESCS)) { + (ndescs < encp->enc_rxq_min_ndescs) || + (ndescs > encp->enc_rxq_max_ndescs)) { rc = EINVAL; goto fail1; } diff --git a/drivers/net/sfc/base/efx.h b/drivers/net/sfc/base/efx.h index 5b5d790fc..06ce3d2fc 100644 --- a/drivers/net/sfc/base/efx.h +++ b/drivers/net/sfc/base/efx.h @@ -1271,6 +1271,8 @@ typedef struct efx_nic_cfg_s { uint32_t enc_evq_limit; uint32_t enc_txq_limit; uint32_t enc_rxq_limit; + uint32_t enc_rxq_max_ndescs; + uint32_t enc_rxq_min_ndescs; uint32_t enc_txq_max_ndescs; uint32_t enc_txq_min_ndescs; uint32_t enc_buftbl_limit; @@ -2462,8 +2464,12 @@ efx_pseudo_hdr_pkt_length_get( __in uint8_t *buffer, __out uint16_t *pkt_lengthp); -#define EFX_RXQ_MAXNDESCS 4096 -#define EFX_RXQ_MINNDESCS 512 +/* + * These symbols are deprecated and will be removed. + * Use the fields from efx_nic_cfg_t instead. + */ +#define EFX_RXQ_MAXNDESCS 4096 +#define EFX_RXQ_MINNDESCS 512 #define EFX_RXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t)) #define EFX_RXQ_NBUFS(_ndescs) (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE) diff --git a/drivers/net/sfc/base/efx_rx.c b/drivers/net/sfc/base/efx_rx.c index afa3ac588..332f8c800 100644 --- a/drivers/net/sfc/base/efx_rx.c +++ b/drivers/net/sfc/base/efx_rx.c @@ -1590,11 +1590,12 @@ siena_rx_qcreate( EFSYS_ASSERT3U(label, <, EFX_EV_RX_NLABELS); EFSYS_ASSERT3U(enp->en_rx_qcount + 1, <, encp->enc_rxq_limit); - EFX_STATIC_ASSERT(ISP2(EFX_RXQ_MAXNDESCS)); - EFX_STATIC_ASSERT(ISP2(EFX_RXQ_MINNDESCS)); + EFSYS_ASSERT(ISP2(encp->enc_rxq_max_ndescs)); + EFSYS_ASSERT(ISP2(encp->enc_rxq_min_ndescs)); if (!ISP2(ndescs) || - (ndescs < EFX_RXQ_MINNDESCS) || (ndescs > EFX_RXQ_MAXNDESCS)) { + (ndescs < encp->enc_rxq_min_ndescs) || + (ndescs > encp->enc_rxq_max_ndescs)) { rc = EINVAL; goto fail1; } @@ -1602,9 +1603,10 @@ siena_rx_qcreate( rc = EINVAL; goto fail2; } - for (size = 0; (1 << size) <= (EFX_RXQ_MAXNDESCS / EFX_RXQ_MINNDESCS); + for (size = 0; + (1U << size) <= encp->enc_rxq_max_ndescs / encp->enc_rxq_min_ndescs; size++) - if ((1 << size) == (int)(ndescs / EFX_RXQ_MINNDESCS)) + if ((1U << size) == (uint32_t)ndescs / encp->enc_rxq_min_ndescs) break; if (id + (1 << size) >= encp->enc_buftbl_limit) { rc = EINVAL; diff --git a/drivers/net/sfc/base/hunt_nic.c b/drivers/net/sfc/base/hunt_nic.c index 6605cfce4..ae8a0085e 100644 --- a/drivers/net/sfc/base/hunt_nic.c +++ b/drivers/net/sfc/base/hunt_nic.c @@ -190,6 +190,9 @@ hunt_board_cfg( encp->enc_rx_buf_align_start = 1; encp->enc_rx_buf_align_end = 64; /* RX DMA end padding */ + encp->enc_rxq_max_ndescs = EF10_RXQ_MAXNDESCS; + encp->enc_rxq_min_ndescs = EF10_RXQ_MINNDESCS; + /* * The workaround for bug35388 uses the top bit of transmit queue * descriptor writes, preventing the use of 4096 descriptor TXQs. diff --git a/drivers/net/sfc/base/medford2_nic.c b/drivers/net/sfc/base/medford2_nic.c index 020c37fd9..87c97b5db 100644 --- a/drivers/net/sfc/base/medford2_nic.c +++ b/drivers/net/sfc/base/medford2_nic.c @@ -114,6 +114,9 @@ medford2_board_cfg( } encp->enc_rx_buf_align_end = end_padding; + encp->enc_rxq_max_ndescs = EF10_RXQ_MAXNDESCS; + encp->enc_rxq_min_ndescs = EF10_RXQ_MINNDESCS; + /* * The maximum supported transmit queue size is 2048. TXQs with 4096 * descriptors are not supported as the top bit is used for vfifo diff --git a/drivers/net/sfc/base/medford_nic.c b/drivers/net/sfc/base/medford_nic.c index 171e39b03..c5d919742 100644 --- a/drivers/net/sfc/base/medford_nic.c +++ b/drivers/net/sfc/base/medford_nic.c @@ -112,6 +112,9 @@ medford_board_cfg( } encp->enc_rx_buf_align_end = end_padding; + encp->enc_rxq_max_ndescs = EF10_RXQ_MAXNDESCS; + encp->enc_rxq_min_ndescs = EF10_RXQ_MINNDESCS; + /* * The maximum supported transmit queue size is 2048. TXQs with 4096 * descriptors are not supported as the top bit is used for vfifo diff --git a/drivers/net/sfc/base/siena_impl.h b/drivers/net/sfc/base/siena_impl.h index 549712377..90f71d9c4 100644 --- a/drivers/net/sfc/base/siena_impl.h +++ b/drivers/net/sfc/base/siena_impl.h @@ -27,6 +27,9 @@ extern "C" { #define SIENA_TXQ_MAXNDESCS 4096 #define SIENA_TXQ_MINNDESCS 512 +#define SIENA_RXQ_MAXNDESCS 4096 +#define SIENA_RXQ_MINNDESCS 512 + #define SIENA_NVRAM_CHUNK 0x80 diff --git a/drivers/net/sfc/base/siena_nic.c b/drivers/net/sfc/base/siena_nic.c index 0f02195c0..341abd8f6 100644 --- a/drivers/net/sfc/base/siena_nic.c +++ b/drivers/net/sfc/base/siena_nic.c @@ -149,6 +149,9 @@ siena_board_cfg( encp->enc_rxq_limit = MIN(EFX_RXQ_LIMIT_TARGET, nrxq); encp->enc_txq_limit = MIN(EFX_TXQ_LIMIT_TARGET, ntxq); + encp->enc_rxq_max_ndescs = EF10_RXQ_MAXNDESCS; + encp->enc_rxq_min_ndescs = EF10_RXQ_MINNDESCS; + encp->enc_txq_max_ndescs = SIENA_TXQ_MAXNDESCS; encp->enc_txq_min_ndescs = SIENA_TXQ_MINNDESCS; -- 2.17.1