[dpdk-dev] [DPDK v3] net/ipn3ke: modifications on AFU configurations

[Dan Wei <dan.wei@intel.com>]

Modify AFU configurations for new BBS(Blue Bitstream) of A10 on N3000 card:
- AFU register access: RTL changes the UPL(User Programable Logic which
is the container of vBNG IP) base address and the read/write commands of
register indirect access.
- Poll the INIT_STS register to wait for the vBNG IP and DDR reset
completion.
- Refine log for debug: print UPL_version not only for vBNG bit stream,
but also for other bit streams.

Fixes: c01c748e4ae6 ("net/ipn3ke: add new driver")
Cc: rosen.xu@intel.com
Cc: stable@dpdk.org

Signed-off-by: Dan Wei <dan.wei@intel.com>
---
 drivers/net/ipn3ke/ipn3ke_ethdev.c | 35 ++++++++++++++++++++++++++++++++---
 drivers/net/ipn3ke/ipn3ke_ethdev.h | 12 ++++++++----
 drivers/net/ipn3ke/ipn3ke_flow.c   |  1 +
 3 files changed, 41 insertions(+), 7 deletions(-)

diff --git a/drivers/net/ipn3ke/ipn3ke_ethdev.c b/drivers/net/ipn3ke/ipn3ke_ethdev.c
index 9079b57..ac8ecc2 100644
--- a/drivers/net/ipn3ke/ipn3ke_ethdev.c
+++ b/drivers/net/ipn3ke/ipn3ke_ethdev.c
@@ -192,6 +192,26 @@
 }
 
 static int
+ipn3ke_vbng_init_done(struct ipn3ke_hw *hw)
+{
+	uint32_t timeout = 10000;
+	while (timeout > 0) {
+		if (IPN3KE_READ_REG(hw, IPN3KE_VBNG_INIT_STS)
+			== IPN3KE_VBNG_INIT_DONE)
+			break;
+		rte_delay_us(1000);
+		timeout--;
+	}
+
+	if (!timeout) {
+		IPN3KE_AFU_PMD_ERR("IPN3KE vBNG INIT timeout.\n");
+		return -1;
+	}
+
+	return 0;
+}
+
+static int
 ipn3ke_hw_init(struct rte_afu_device *afu_dev,
 	struct ipn3ke_hw *hw)
 {
@@ -223,15 +243,24 @@
 				"LineSideMACType", &mac_type);
 	hw->retimer.mac_type = (int)mac_type;
 
+	IPN3KE_AFU_PMD_DEBUG("UPL_version is 0x%x\n", IPN3KE_READ_REG(hw, 0));
+
 	if (afu_dev->id.uuid.uuid_low == IPN3KE_UUID_VBNG_LOW &&
 		afu_dev->id.uuid.uuid_high == IPN3KE_UUID_VBNG_HIGH) {
+		/* After power on, wait until init done */
+		if (ipn3ke_vbng_init_done(hw))
+			return -1;
+
 		ipn3ke_hw_cap_init(hw);
-		IPN3KE_AFU_PMD_DEBUG("UPL_version is 0x%x\n",
-			IPN3KE_READ_REG(hw, 0));
 
-		/* Reset FPGA IP */
+		/* Reset vBNG IP */
 		IPN3KE_WRITE_REG(hw, IPN3KE_CTRL_RESET, 1);
+		rte_delay_us(10);
 		IPN3KE_WRITE_REG(hw, IPN3KE_CTRL_RESET, 0);
+
+		/* After reset, wait until init done */
+		if (ipn3ke_vbng_init_done(hw))
+			return -1;
 	}
 
 	if (hw->retimer.mac_type == IFPGA_RAWDEV_RETIMER_MAC_TYPE_10GE_XFI) {
diff --git a/drivers/net/ipn3ke/ipn3ke_ethdev.h b/drivers/net/ipn3ke/ipn3ke_ethdev.h
index bfda9d5..29ab41c 100644
--- a/drivers/net/ipn3ke/ipn3ke_ethdev.h
+++ b/drivers/net/ipn3ke/ipn3ke_ethdev.h
@@ -344,7 +344,8 @@ static inline uint32_t ipn3ke_read_addr(volatile void *addr)
 
 #define WCMD 0x8000000000000000
 #define RCMD 0x4000000000000000
-#define UPL_BASE 0x10000
+#define INDRCT_CTRL 0x30
+#define INDRCT_STS 0x38
 static inline uint32_t _ipn3ke_indrct_read(struct ipn3ke_hw *hw,
 		uint32_t addr)
 {
@@ -355,13 +356,13 @@ static inline uint32_t _ipn3ke_indrct_read(struct ipn3ke_hw *hw,
 
 	word_offset = (addr & 0x1FFFFFF) >> 2;
 	indirect_value = RCMD | word_offset << 32;
-	indirect_addrs = hw->hw_addr + (uint32_t)(UPL_BASE | 0x10);
+	indirect_addrs = hw->hw_addr + (uint32_t)(INDRCT_CTRL);
 
 	rte_delay_us(10);
 
 	rte_write64((rte_cpu_to_le_64(indirect_value)), indirect_addrs);
 
-	indirect_addrs = hw->hw_addr + (uint32_t)(UPL_BASE | 0x18);
+	indirect_addrs = hw->hw_addr + (uint32_t)(INDRCT_STS);
 	while ((read_data >> 32) != 1)
 		read_data = rte_read64(indirect_addrs);
 
@@ -377,7 +378,7 @@ static inline void _ipn3ke_indrct_write(struct ipn3ke_hw *hw,
 
 	word_offset = (addr & 0x1FFFFFF) >> 2;
 	indirect_value = WCMD | word_offset << 32 | value;
-	indirect_addrs = hw->hw_addr + (uint32_t)(UPL_BASE | 0x10);
+	indirect_addrs = hw->hw_addr + (uint32_t)(INDRCT_CTRL);
 
 	rte_write64((rte_cpu_to_le_64(indirect_value)), indirect_addrs);
 	rte_delay_us(10);
@@ -410,6 +411,9 @@ static inline void _ipn3ke_indrct_write(struct ipn3ke_hw *hw,
 #define IPN3KE_DEV_PRIVATE_TO_TM(dev) \
 	(&(((struct ipn3ke_rpst *)(dev)->data->dev_private)->tm))
 
+#define IPN3KE_VBNG_INIT_DONE                      (0x3)
+#define IPN3KE_VBNG_INIT_STS                      (0x204)
+
 /* Byte address of IPN3KE internal module */
 #define IPN3KE_TM_VERSION                     (IPN3KE_QM_OFFSET + 0x0000)
 #define IPN3KE_TM_SCRATCH                     (IPN3KE_QM_OFFSET + 0x0004)
diff --git a/drivers/net/ipn3ke/ipn3ke_flow.c b/drivers/net/ipn3ke/ipn3ke_flow.c
index e5937df..ff9f064 100644
--- a/drivers/net/ipn3ke/ipn3ke_flow.c
+++ b/drivers/net/ipn3ke/ipn3ke_flow.c
@@ -1360,6 +1360,7 @@ int ipn3ke_flow_init(void *dev)
 						IPN3KE_CLF_EM_NUM,
 						0,
 						0xFFFFFFFF);
+	IPN3KE_AFU_PMD_DEBUG("IPN3KE_CLF_EN_NUM: %x\n", hw->flow_max_entries);
 	hw->flow_num_entries = 0;
 
 	return 0;
-- 
1.8.3.1