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From: Rosen Xu <rosen.xu@intel.com>
To: dev@dpdk.org
Cc: ferruh.yigit@intel.com, tianfei.zhang@intel.com, rosen.xu@intel.com,
andy.pei@intel.com, david.lomartire@intel.com, qi.z.zhang@intel.com,
xiaolong.ye@intel.com
Date: Thu, 8 Aug 2019 16:46:06 +0800
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Subject: [dpdk-dev] [PATCH v3 05/13] raw/ifpga_rawdev/base: add device tree
support
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From: Tianfei zhang <tianfei.zhang@intel.com>
In PAC N3000 card, this is a BMC chip which using MAX10 FPGA
to manage the board configuration, like sensors, flash controller,
QSFP, powers. And this is a SPI bus connected between A10 FPGA and
MAX10, we can access the MAX10 registers over this SPI bus.
In BMC, there are about 19 sensors in MAX10 chip, including the FPGA
core temperature, Board temperature, board current, voltage and so on.
We use DTB (Device tree table) to describe it. This DTB file is store
in nor flash partition, which will flashed in Factory when the boards
delivery to customers. And the same time, the customers can easy to
customizate the BMC configuration like change the sensors.
Add device tree support by using libfdt library in Linux distribution.
The end-user should pre-install the libfdt and libfdt-devel package
before use DPDK on PAC N3000 Card.
For Centos 7.x: sudo yum install libfdt libfdt-devel
For Ubuntu 18.04: sudo apt install libfdt-dev libfdt1
Signed-off-by: Tianfei zhang <tianfei.zhang@intel.com>
---
drivers/raw/ifpga_rawdev/base/opae_intel_max10.c | 183 +++++++++++++++++++++++
drivers/raw/ifpga_rawdev/base/opae_intel_max10.h | 10 ++
mk/rte.app.mk | 2 +-
3 files changed, 194 insertions(+), 1 deletion(-)
diff --git a/drivers/raw/ifpga_rawdev/base/opae_intel_max10.c b/drivers/raw/ifpga_rawdev/base/opae_intel_max10.c
index 9ed10e2..305baba 100644
--- a/drivers/raw/ifpga_rawdev/base/opae_intel_max10.c
+++ b/drivers/raw/ifpga_rawdev/base/opae_intel_max10.c
@@ -3,6 +3,7 @@
*/
#include "opae_intel_max10.h"
+#include <libfdt.h>
static struct intel_max10_device *g_max10;
@@ -26,6 +27,174 @@ int max10_reg_write(unsigned int reg, unsigned int val)
reg, 4, (unsigned char *)&tmp);
}
+static struct max10_compatible_id max10_id_table[] = {
+ {.compatible = MAX10_PAC,},
+ {.compatible = MAX10_PAC_N3000,},
+ {.compatible = MAX10_PAC_END,}
+};
+
+static struct max10_compatible_id *max10_match_compatible(const char *fdt_root)
+{
+ struct max10_compatible_id *id = max10_id_table;
+
+ for (; strcmp(id->compatible, MAX10_PAC_END); id++) {
+ if (fdt_node_check_compatible(fdt_root, 0, id->compatible))
+ continue;
+
+ return id;
+ }
+
+ return NULL;
+}
+
+static inline bool
+is_max10_pac_n3000(struct intel_max10_device *max10)
+{
+ return max10->id && !strcmp(max10->id->compatible,
+ MAX10_PAC_N3000);
+}
+
+static void max10_check_capability(struct intel_max10_device *max10)
+{
+ if (!max10->fdt_root)
+ return;
+
+ if (is_max10_pac_n3000(max10)) {
+ max10->flags |= MAX10_FLAGS_NO_I2C2 |
+ MAX10_FLAGS_NO_BMCIMG_FLASH;
+ dev_info(max10, "found %s card\n", max10->id->compatible);
+ }
+}
+
+static int altera_nor_flash_read(u32 offset,
+ void *buffer, u32 len)
+{
+ int word_len;
+ int i;
+ unsigned int *buf = (unsigned int *)buffer;
+ unsigned int value;
+ int ret;
+
+ if (!buffer || len <= 0)
+ return -ENODEV;
+
+ word_len = len/4;
+
+ for (i = 0; i < word_len; i++) {
+ ret = max10_reg_read(offset + i*4,
+ &value);
+ if (ret)
+ return -EBUSY;
+
+ *buf++ = value;
+ }
+
+ return 0;
+}
+
+static int enable_nor_flash(bool on)
+{
+ unsigned int val = 0;
+ int ret;
+
+ ret = max10_reg_read(RSU_REG_OFF, &val);
+ if (ret) {
+ dev_err(NULL "enabling flash error\n");
+ return ret;
+ }
+
+ if (on)
+ val |= RSU_ENABLE;
+ else
+ val &= ~RSU_ENABLE;
+
+ return max10_reg_write(RSU_REG_OFF, val);
+}
+
+static int init_max10_device_table(struct intel_max10_device *max10)
+{
+ struct max10_compatible_id *id;
+ struct fdt_header hdr;
+ char *fdt_root = NULL;
+
+ u32 dt_size, dt_addr, val;
+ int ret;
+
+ ret = max10_reg_read(DT_AVAIL_REG_OFF, &val);
+ if (ret) {
+ dev_err(max10 "cannot read DT_AVAIL_REG\n");
+ return ret;
+ }
+
+ if (!(val & DT_AVAIL)) {
+ dev_err(max10 "DT not available\n");
+ return -EINVAL;
+ }
+
+ ret = max10_reg_read(DT_BASE_ADDR_REG_OFF, &dt_addr);
+ if (ret) {
+ dev_info(max10 "cannot get base addr of device table\n");
+ return ret;
+ }
+
+ ret = enable_nor_flash(true);
+ if (ret) {
+ dev_err(max10 "fail to enable flash\n");
+ return ret;
+ }
+
+ ret = altera_nor_flash_read(dt_addr, &hdr, sizeof(hdr));
+ if (ret) {
+ dev_err(max10 "read fdt header fail\n");
+ goto done;
+ }
+
+ ret = fdt_check_header(&hdr);
+ if (ret) {
+ dev_err(max10 "check fdt header fail\n");
+ goto done;
+ }
+
+ dt_size = fdt_totalsize(&hdr);
+ if (dt_size > DFT_MAX_SIZE) {
+ dev_err(max10 "invalid device table size\n");
+ ret = -EINVAL;
+ goto done;
+ }
+
+ fdt_root = opae_malloc(dt_size);
+ if (!fdt_root) {
+ ret = -ENOMEM;
+ goto done;
+ }
+
+ ret = altera_nor_flash_read(dt_addr, fdt_root, dt_size);
+ if (ret) {
+ dev_err(max10 "cannot read device table\n");
+ goto done;
+ }
+
+ id = max10_match_compatible(fdt_root);
+ if (!id) {
+ dev_err(max10 "max10 compatible not found\n");
+ ret = -ENODEV;
+ goto done;
+ }
+
+ max10->flags |= MAX10_FLAGS_DEVICE_TABLE;
+
+ max10->id = id;
+ max10->fdt_root = fdt_root;
+
+done:
+ ret = enable_nor_flash(false);
+
+ if (ret && fdt_root)
+ opae_free(fdt_root);
+
+ return ret;
+}
+
struct intel_max10_device *
intel_max10_device_probe(struct altera_spi_device *spi,
int chipselect)
@@ -49,6 +218,15 @@ struct intel_max10_device *
/* set the max10 device firstly */
g_max10 = dev;
+ /* init the MAX10 device table */
+ ret = init_max10_device_table(dev);
+ if (ret) {
+ dev_err(dev, "init max10 device table fail\n");
+ goto free_dev;
+ }
+
+ max10_check_capability(dev);
+
/* read FPGA loading information */
ret = max10_reg_read(FPGA_PAGE_INFO_OFF, &val);
if (ret) {
@@ -60,6 +238,8 @@ struct intel_max10_device *
return dev;
spi_tran_fail:
+ if (dev->fdt_root)
+ opae_free(dev->fdt_root);
spi_transaction_remove(dev->spi_tran_dev);
free_dev:
g_max10 = NULL;
@@ -76,6 +256,9 @@ int intel_max10_device_remove(struct intel_max10_device *dev)
if (dev->spi_tran_dev)
spi_transaction_remove(dev->spi_tran_dev);
+ if (dev->fdt_root)
+ opae_free(dev->fdt_root);
+
g_max10 = NULL;
opae_free(dev);
diff --git a/drivers/raw/ifpga_rawdev/base/opae_intel_max10.h b/drivers/raw/ifpga_rawdev/base/opae_intel_max10.h
index 08b387e..a52b63e 100644
--- a/drivers/raw/ifpga_rawdev/base/opae_intel_max10.h
+++ b/drivers/raw/ifpga_rawdev/base/opae_intel_max10.h
@@ -8,6 +8,14 @@
#include "opae_osdep.h"
#include "opae_spi.h"
+struct max10_compatible_id {
+ char compatible[128];
+};
+
+#define MAX10_PAC "intel,max10"
+#define MAX10_PAC_N3000 "intel,max10-pac-n3000"
+#define MAX10_PAC_END "intel,end"
+
/* max10 capability flags */
#define MAX10_FLAGS_NO_I2C2 BIT(0)
#define MAX10_FLAGS_NO_BMCIMG_FLASH BIT(1)
@@ -20,6 +28,8 @@ struct intel_max10_device {
unsigned int flags; /*max10 hardware capability*/
struct altera_spi_device *spi_master;
struct spi_transaction_dev *spi_tran_dev;
+ struct max10_compatible_id *id; /*max10 compatible*/
+ char *fdt_root;
};
/* retimer speed */
diff --git a/mk/rte.app.mk b/mk/rte.app.mk
index a277c80..c880506 100644
--- a/mk/rte.app.mk
+++ b/mk/rte.app.mk
@@ -319,7 +319,7 @@ _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_DPAA2_QDMA_RAWDEV) += -lrte_pmd_dpaa2_qdma
endif # CONFIG_RTE_LIBRTE_FSLMC_BUS
_LDLIBS-$(CONFIG_RTE_LIBRTE_IFPGA_BUS) += -lrte_bus_ifpga
ifeq ($(CONFIG_RTE_LIBRTE_IFPGA_BUS),y)
-_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_IFPGA_RAWDEV) += -lrte_pmd_ifpga_rawdev
+_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_IFPGA_RAWDEV) += -lrte_pmd_ifpga_rawdev -lfdt
_LDLIBS-$(CONFIG_RTE_LIBRTE_IPN3KE_PMD) += -lrte_pmd_ipn3ke
endif # CONFIG_RTE_LIBRTE_IFPGA_BUS
_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_IOAT_RAWDEV) += -lrte_pmd_ioat_rawdev
--
1.8.3.1